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hv: remove ACRN_REQUEST_TMR_UPDATE and unnecessary codes

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Because ACRN_REQUEST_TMR_UPDATE is not needed anymore, this commit remove
the MACRO definition and its related logic, including following functions:
- apicv_batch_set_tmr()
- vlapic_apicv_batch_set_tmr()
- vlapic_set_tmr_one_vec()
- vioapic_update_tmr()

Tracked-On: #2343
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yan, Like
2019-01-14 21:48:52 +08:00
committed by wenlingz
parent fc61536b07
commit 6641bc7949
6 changed files with 9 additions and 129 deletions
Download Patch File Download Diff File Expand all files Collapse all files

67
hypervisor/arch/x86/guest/vlapic.c
View File

@@ -83,9 +83,6 @@ apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector);
static int32_t
apicv_pending_intr(const struct acrn_vlapic *vlapic);
static void
apicv_batch_set_tmr(const struct acrn_vlapic *vlapic);
/*
* Post an interrupt to the vcpu running on 'hostcpu'. This will use a
* hardware assist if available (e.g. Posted Interrupt) or fall back to
@@ -1866,45 +1863,6 @@ vlapic_enabled(const struct acrn_vlapic *vlapic)
return ret;
}
/*
* APICv batch set tmr will try to set multi vec at the same time
* to avoid unnecessary VMCS read/update.
*/
void
vlapic_apicv_batch_set_tmr(struct acrn_vlapic *vlapic)
{
if (is_apicv_intr_delivery_supported()) {
apicv_batch_set_tmr(vlapic);
}
}
void
vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
uint32_t vector, bool level)
{
ASSERT(vector <= NR_MAX_VECTOR,
"invalid vector %u", vector);
/*
* A level trigger is valid only for fixed and lowprio delivery modes.
*/
if ((delmode != APIC_DELMODE_FIXED) && (delmode != APIC_DELMODE_LOWPRIO)) {
dev_dbg(ACRN_DBG_LAPIC,
"Ignoring level trigger-mode for delivery-mode %u",
delmode);
} else {
/* NOTE
* We don't check whether the vcpu is in the dest here. That means
* all vcpus of vm will do tmr update.
*
* If there is new caller to this function, need to refine this
* part of work.
*/
dev_dbg(ACRN_DBG_LAPIC, "vector %u set to level-triggered", vector);
vlapic_set_tmr(vlapic, vector, level);
}
}
/*
* @pre vcpu != NULL
* @pre vector <= 255U
@@ -2312,31 +2270,6 @@ apicv_pending_intr(const struct acrn_vlapic *vlapic)
return ret;
}
/* Update the VMX_EOI_EXIT according to related tmr */
#define EOI_STEP_LEN (64U)
#define TMR_STEP_LEN (32U)
static void
apicv_batch_set_tmr(const struct acrn_vlapic *vlapic)
{
const struct lapic_regs *lapic = &(vlapic->apic_page);
uint64_t val;
const struct lapic_reg *ptr;
uint32_t s, e;
ptr = &lapic->tmr[0];
s = 0U;
e = 256U;
while (s < e) {
val = ptr[(s / TMR_STEP_LEN) + 1].v;
val <<= TMR_STEP_LEN;
val |= ptr[s / TMR_STEP_LEN].v;
exec_vmwrite64(vmx_eoi_exit(s), val);
s += EOI_STEP_LEN;
}
}
/**
*APIC-v: Get the HPA to APIC-access page
* **/

4
hypervisor/arch/x86/virq.c
View File

@@ -405,10 +405,6 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
flush_vpid_single(arch->vpid);
}
if (bitmap_test_and_clear_lock(ACRN_REQUEST_TMR_UPDATE, pending_req_bits)) {
vioapic_update_tmr(vcpu);
}
if (bitmap_test_and_clear_lock(ACRN_REQUEST_EOI_EXIT_UPDATE, pending_req_bits)) {
vcpu_set_vmcs_eoi_exit(vcpu);
}