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HV: cpu: convert hexadecimals used in bitops to unsigned
Per MISRA C, operands to bit-wise operations should have unsigned
types. However, C99 prioritizes to use signed integers for hexadecimal constants
without the 'U' suffixes, leading to tons of bit operations on signed integers.
This patch series add the 'U' suffixes to the constants which are used in bit
operations, and add the intended width of these integers when applicable
(i.e. the target value is at least 32-bit wide) to avoid functional differences
due to signed vs. unsigned extensions. The rule of thumb is:
'0' for signed char/short/int
'0U' for unsigned char/short/int
'0L' for signed long (should be 64-bit)
'0UL' for unsigned long (should be 64-bit)
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
@@ -41,80 +41,80 @@
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/* Define page size */
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#define CPU_PAGE_SHIFT 12
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#define CPU_PAGE_SIZE 0x1000
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#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000
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#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL
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#define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT
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#define MMU_PDE_PAGE_SHIFT 21
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/* Define CPU stack alignment */
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#define CPU_STACK_ALIGN 16
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#define CPU_STACK_ALIGN 16UL
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/* CR0 register definitions */
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#define CR0_PG (1<<31) /* paging enable */
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#define CR0_CD (1<<30) /* cache disable */
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#define CR0_NW (1<<29) /* not write through */
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#define CR0_AM (1<<18) /* alignment mask */
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#define CR0_WP (1<<16) /* write protect */
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#define CR0_NE (1<<5) /* numeric error */
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#define CR0_ET (1<<4) /* extension type */
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#define CR0_TS (1<<3) /* task switched */
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#define CR0_EM (1<<2) /* emulation */
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#define CR0_MP (1<<1) /* monitor coprocessor */
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#define CR0_PE (1<<0) /* protected mode enabled */
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#define CR0_PG (1U<<31) /* paging enable */
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#define CR0_CD (1U<<30) /* cache disable */
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#define CR0_NW (1U<<29) /* not write through */
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#define CR0_AM (1U<<18) /* alignment mask */
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#define CR0_WP (1U<<16) /* write protect */
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#define CR0_NE (1U<<5) /* numeric error */
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#define CR0_ET (1U<<4) /* extension type */
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#define CR0_TS (1U<<3) /* task switched */
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#define CR0_EM (1U<<2) /* emulation */
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#define CR0_MP (1U<<1) /* monitor coprocessor */
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#define CR0_PE (1U<<0) /* protected mode enabled */
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/* CR3 register definitions */
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#define CR3_PWT (1<<3) /* page-level write through */
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#define CR3_PCD (1<<4) /* page-level cache disable */
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#define CR3_PWT (1U<<3) /* page-level write through */
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#define CR3_PCD (1U<<4) /* page-level cache disable */
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/* CR4 register definitions */
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#define CR4_VME (1<<0) /* virtual 8086 mode extensions */
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#define CR4_PVI (1<<1) /* protected mode virtual interrupts */
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#define CR4_TSD (1<<2) /* time stamp disable */
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#define CR4_DE (1<<3) /* debugging extensions */
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#define CR4_PSE (1<<4) /* page size extensions */
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#define CR4_PAE (1<<5) /* physical address extensions */
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#define CR4_MCE (1<<6) /* machine check enable */
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#define CR4_PGE (1<<7) /* page global enable */
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#define CR4_PCE (1<<8)
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#define CR4_VME (1U<<0) /* virtual 8086 mode extensions */
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#define CR4_PVI (1U<<1) /* protected mode virtual interrupts */
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#define CR4_TSD (1U<<2) /* time stamp disable */
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#define CR4_DE (1U<<3) /* debugging extensions */
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#define CR4_PSE (1U<<4) /* page size extensions */
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#define CR4_PAE (1U<<5) /* physical address extensions */
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#define CR4_MCE (1U<<6) /* machine check enable */
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#define CR4_PGE (1U<<7) /* page global enable */
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#define CR4_PCE (1U<<8)
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/* performance monitoring counter enable */
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#define CR4_OSFXSR (1<<9) /* OS support for FXSAVE/FXRSTOR */
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#define CR4_OSXMMEXCPT (1<<10)
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#define CR4_OSFXSR (1U<<9) /* OS support for FXSAVE/FXRSTOR */
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#define CR4_OSXMMEXCPT (1U<<10)
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/* OS support for unmasked SIMD floating point exceptions */
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#define CR4_VMXE (1<<13) /* VMX enable */
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#define CR4_SMXE (1<<14) /* SMX enable */
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#define CR4_PCIDE (1<<17) /* PCID enable */
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#define CR4_OSXSAVE (1<<18)
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#define CR4_SMEP (1<<20)
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#define CR4_SMAP (1<<21)
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#define CR4_VMXE (1U<<13) /* VMX enable */
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#define CR4_SMXE (1U<<14) /* SMX enable */
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#define CR4_PCIDE (1U<<17) /* PCID enable */
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#define CR4_OSXSAVE (1U<<18)
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#define CR4_SMEP (1U<<20)
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#define CR4_SMAP (1U<<21)
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/* XSAVE and Processor Extended States enable bit */
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/*
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* Entries in the Interrupt Descriptor Table (IDT)
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*/
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#define IDT_DE 0 /* #DE: Divide Error */
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#define IDT_DB 1 /* #DB: Debug */
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#define IDT_NMI 2 /* Nonmaskable External Interrupt */
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#define IDT_BP 3 /* #BP: Breakpoint */
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#define IDT_OF 4 /* #OF: Overflow */
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#define IDT_BR 5 /* #BR: Bound Range Exceeded */
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#define IDT_UD 6 /* #UD: Undefined/Invalid Opcode */
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#define IDT_NM 7 /* #NM: No Math Coprocessor */
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#define IDT_DF 8 /* #DF: Double Fault */
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#define IDT_FPUGP 9 /* Coprocessor Segment Overrun */
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#define IDT_TS 10 /* #TS: Invalid TSS */
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#define IDT_NP 11 /* #NP: Segment Not Present */
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#define IDT_SS 12 /* #SS: Stack Segment Fault */
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#define IDT_GP 13 /* #GP: General Protection Fault */
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#define IDT_PF 14 /* #PF: Page Fault */
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#define IDT_MF 16 /* #MF: FPU Floating-Point Error */
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#define IDT_AC 17 /* #AC: Alignment Check */
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#define IDT_MC 18 /* #MC: Machine Check */
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#define IDT_XF 19 /* #XF: SIMD Floating-Point Exception */
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#define IDT_VE 20 /* #VE: Virtualization Exception */
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#define IDT_DE 0U /* #DE: Divide Error */
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#define IDT_DB 1U /* #DB: Debug */
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#define IDT_NMI 2U /* Nonmaskable External Interrupt */
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#define IDT_BP 3U /* #BP: Breakpoint */
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#define IDT_OF 4U /* #OF: Overflow */
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#define IDT_BR 5U /* #BR: Bound Range Exceeded */
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#define IDT_UD 6U /* #UD: Undefined/Invalid Opcode */
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#define IDT_NM 7U /* #NM: No Math Coprocessor */
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#define IDT_DF 8U /* #DF: Double Fault */
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#define IDT_FPUGP 9U /* Coprocessor Segment Overrun */
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#define IDT_TS 10U /* #TS: Invalid TSS */
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#define IDT_NP 11U /* #NP: Segment Not Present */
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#define IDT_SS 12U /* #SS: Stack Segment Fault */
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#define IDT_GP 13U /* #GP: General Protection Fault */
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#define IDT_PF 14U /* #PF: Page Fault */
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#define IDT_MF 16U /* #MF: FPU Floating-Point Error */
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#define IDT_AC 17U /* #AC: Alignment Check */
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#define IDT_MC 18U /* #MC: Machine Check */
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#define IDT_XF 19U /* #XF: SIMD Floating-Point Exception */
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#define IDT_VE 20U /* #VE: Virtualization Exception */
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/*Bits in EFER special registers */
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#define EFER_LMA 0x000000400 /* Long mode active (R) */
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#define EFER_LMA 0x00000400U /* Long mode active (R) */
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/* CPU clock frequencies (FSB) */
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#define CPU_FSB_83KHZ 83200
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@@ -140,7 +140,7 @@
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#define CPU_STATE_DEAD 4
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/* hypervisor stack bottom magic('intl') */
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#define SP_BOTTOM_MAGIC 0x696e746c
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#define SP_BOTTOM_MAGIC 0x696e746cUL
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/* type of speculation control
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* 0 - no speculation control support
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@@ -310,7 +310,7 @@ void start_cpus();
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/* This macro writes the stack pointer. */
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#define CPU_SP_WRITE(stack_ptr) \
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{ \
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uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1); \
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uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1UL); \
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asm volatile ("movq %0, %%rsp" : : "r"(rsp)); \
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}
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