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hv: vpci: modify Interrupt Line Register as writable
According to PCIe Spec, for a RW register bits, If the optional feature that is associated with the bits is not implemented, the bits are permitted to be hardwired to 0b. However Zephyr would use INTx Line Register as writable even this PCI device has no INTx, so emulate INTx Line Register as writable. Tracked-On: #6330 Signed-off-by: Fei Li <fei1.li@intel.com>
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@ -482,6 +482,17 @@ static void write_cfg_header(struct pci_vdev *vdev,
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pci_vdev_write_vcfg(vdev, offset, bytes, val);
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}
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}
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/* According to PCIe Spec, for a RW register bits, If the optional feature
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* that is associated with the bits is not implemented, the bits are permitted
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* to be hardwired to 0b. However Zephyr would use INTx Line Register as writable
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* even this PCI device has no INTx, so emulate INTx Line Register as writable.
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*/
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if (offset == PCIR_INTERRUPT_LINE) {
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val &= 0xfU;
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pci_vdev_write_vcfg(vdev, offset, bytes, val);
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}
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}
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}
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