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hv: vpci: modify Interrupt Line Register as writable

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According to PCIe Spec, for a RW register bits, If the optional feature
that is associated with the bits is not implemented, the bits are permitted
to be hardwired to 0b. However Zephyr would use INTx Line Register as writable
even this PCI device has no INTx, so emulate INTx Line Register as writable.

Tracked-On: #6330
Signed-off-by: Fei Li <fei1.li@intel.com>
This commit is contained in:
Fei Li 2021-07-23 08:59:35 +08:00 committed by Xie, Nanlin
parent 9948dea338
commit 89c25b008a
1 changed files with 11 additions and 0 deletions
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11
hypervisor/dm/vpci/vpci.c
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@ -482,6 +482,17 @@ static void write_cfg_header(struct pci_vdev *vdev,
pci_vdev_write_vcfg(vdev, offset, bytes, val);
}
}
/* According to PCIe Spec, for a RW register bits, If the optional feature
* that is associated with the bits is not implemented, the bits are permitted
* to be hardwired to 0b. However Zephyr would use INTx Line Register as writable
* even this PCI device has no INTx, so emulate INTx Line Register as writable.
*/
if (offset == PCIR_INTERRUPT_LINE) {
val &= 0xfU;
pci_vdev_write_vcfg(vdev, offset, bytes, val);
}
}
}