github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-22 13:37:10 +00:00
Code Issues Projects Releases Wiki Activity

HV: clean up redundant macro in lapic.h

Browse Source 
Some MACROs in lapic.h are duplicated with apicreg.h, and some MACROs are
never referenced, remove them.

Tracked-On: #4268

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Victor Sun 2019-12-16 22:16:05 +08:00 committed by wenlingz
parent 46ed0b1582
commit 9ecac8629a
2 changed files with 9 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hypervisor/arch/x86/lapic.c
View File

@ -76,17 +76,17 @@ void init_lapic(uint16_t pcpu_id)
{
per_cpu(lapic_ldr, pcpu_id) = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LDR);
/* Mask all LAPIC LVT entries before enabling the local APIC */
msr_write(MSR_IA32_EXT_APIC_LVT_CMCI, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_THERMAL, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_PMI, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_LINT0, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_LINT1, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_ERROR, LAPIC_LVT_MASK);
msr_write(MSR_IA32_EXT_APIC_LVT_CMCI, APIC_LVT_M);
msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, APIC_LVT_M);
msr_write(MSR_IA32_EXT_APIC_LVT_THERMAL, APIC_LVT_M);
msr_write(MSR_IA32_EXT_APIC_LVT_PMI, APIC_LVT_M);
msr_write(MSR_IA32_EXT_APIC_LVT_LINT0, APIC_LVT_M);
msr_write(MSR_IA32_EXT_APIC_LVT_LINT1, APIC_LVT_M);
msr_write(MSR_IA32_EXT_APIC_LVT_ERROR, APIC_LVT_M);
/* Enable Local APIC */
/* TODO: add spurious-interrupt handler */
msr_write(MSR_IA32_EXT_APIC_SIVR, LAPIC_SVR_APIC_ENABLE_MASK | LAPIC_SVR_VECTOR);
msr_write(MSR_IA32_EXT_APIC_SIVR, APIC_SVR_ENABLE | APIC_SVR_VECTOR);
/* Ensure there are no ISR bits set. */
clear_lapic_isr();
@ -146,7 +146,7 @@ void suspend_lapic(void)
/* disable APIC with software flag */
val = msr_read(MSR_IA32_EXT_APIC_SIVR);
val = (~(uint64_t)LAPIC_SVR_APIC_ENABLE_MASK) & val;
val = (~(uint64_t)APIC_SVR_ENABLE) & val;
msr_write(MSR_IA32_EXT_APIC_SIVR, val);
}

12
hypervisor/include/arch/x86/lapic.h
View File

@ -36,18 +36,6 @@
#define INTR_LAPIC_ICR_ALL_INC_SELF 0x2U
#define INTR_LAPIC_ICR_ALL_EX_SELF 0x3U
/* LAPIC register bit and bitmask definitions */
#define LAPIC_SVR_VECTOR 0x000000FFU
#define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100U
#define LAPIC_LVT_MASK 0x00010000U
#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700U
/* LAPIC Timer bit and bitmask definitions */
#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17U)
#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17U)
#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17U)
enum intr_cpu_startup_shorthand {
INTR_CPU_STARTUP_USE_DEST,
INTR_CPU_STARTUP_ALL_EX_SELF,