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hv: create new file core.c and pci.c

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- move the functions to access physical PCI configuration space from
  pci_pt.c to the new file dm/hw/pci.c, so they can be accessed in
  sharing mode as well. The new folder dm/hw is created in order to
  move APIs talking to physical PCI devices out of dm/vpci.
- move the common vpci code from header file pci_priv.h to core.c.
- move file include/dm/vpci/vpci.h one level up. It seems the folder
  include/dm/vpci is not necessary.
- This patch only moves code around, and doesn't make any logical
  changes. Besides removes the static keyword from pci_pdev_read_cfg()
  and pci_pdev_write_cfg()

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen 2018-09-24 12:12:20 -07:00 committed by Xie, Nanlin
parent 4741fcfff2
commit a6677e6e69
6 changed files with 173 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/Makefile
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@ -100,7 +100,6 @@ INCLUDE_PATH += include/arch/x86/guest
INCLUDE_PATH += include/debug
INCLUDE_PATH += include/public
ifeq ($(CONFIG_PARTITION_MODE),y)
INCLUDE_PATH += include/dm/vpci
INCLUDE_PATH += include/dm
endif
INCLUDE_PATH += bsp/include
@ -183,6 +182,7 @@ C_SRCS += dm/vioapic.c
ifeq ($(CONFIG_PARTITION_MODE),y)
C_SRCS += $(wildcard dm/vpci/*.c)
C_SRCS += $(wildcard partition/*.c)
C_SRCS += dm/hw/pci.c
C_SRCS += dm/vrtc.c
endif

101
hypervisor/dm/hw/pci.c Normal file
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@ -0,0 +1,101 @@
/*
* Copyright (c) 2011 NetApp, Inc.
* Copyright (c) 2018 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <hypervisor.h>
#include <pci.h>
static spinlock_t pci_device_lock = {
.head = 0,
.tail = 0
};
static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
{
uint32_t addr = (uint32_t)bdf.value;
addr <<= 8U;
addr |= (offset | PCI_CFG_ENABLE);
return addr;
}
uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes)
{
uint32_t addr;
uint32_t val;
spinlock_obtain(&pci_device_lock);
addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4U);
/* Read result from DATA register */
switch (bytes) {
case 1U:
val = pio_read8(PCI_CONFIG_DATA + (offset & 3U));
break;
case 2U:
val = pio_read16(PCI_CONFIG_DATA + (offset & 2U));
break;
default:
val = pio_read32(PCI_CONFIG_DATA);
break;
}
spinlock_release(&pci_device_lock);
return val;
}
void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes,
uint32_t val)
{
uint32_t addr;
spinlock_obtain(&pci_device_lock);
addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4U);
/* Write value to DATA register */
switch (bytes) {
case 1U:
pio_write8(val, PCI_CONFIG_DATA + (offset & 3U));
break;
case 2U:
pio_write16(val, PCI_CONFIG_DATA + (offset & 2U));
break;
default:
pio_write32(val, PCI_CONFIG_DATA);
break;
}
spinlock_release(&pci_device_lock);
}

65
hypervisor/dm/vpci/core.c Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2011 NetApp, Inc.
* Copyright (c) 2018 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <hypervisor.h>
#include "pci_priv.h"
inline uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes)
{
uint32_t val;
switch (bytes) {
case 1U:
val = pci_vdev_read_cfg_u8(vdev, offset);
break;
case 2U:
val = pci_vdev_read_cfg_u16(vdev, offset);
break;
default:
val = pci_vdev_read_cfg_u32(vdev, offset);
break;
}
return val;
}
inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
{
switch (bytes) {
case 1U:
pci_vdev_write_cfg_u8(vdev, offset, val);
break;
case 2U:
pci_vdev_write_cfg_u16(vdev, offset, val);
break;
default:
pci_vdev_write_cfg_u32(vdev, offset, val);
break;
}
}

43
hypervisor/dm/vpci/pci_priv.h
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@ -68,43 +68,12 @@ pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
*(uint32_t *)(vdev->cfgdata + offset) = val;
}
static inline uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev,
uint32_t offset, uint32_t bytes)
{
uint32_t val;
uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes);
void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
switch (bytes) {
case 1U:
val = pci_vdev_read_cfg_u8(vdev, offset);
break;
case 2U:
val = pci_vdev_read_cfg_u16(vdev, offset);
break;
default:
val = pci_vdev_read_cfg_u32(vdev, offset);
break;
}
return val;
}
static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t val)
{
switch (bytes) {
case 1U:
pci_vdev_write_cfg_u8(vdev, offset, val);
break;
case 2U:
pci_vdev_write_cfg_u16(vdev, offset, val);
break;
default:
pci_vdev_write_cfg_u32(vdev, offset, val);
break;
}
}
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, union pci_bdf vbdf, uint32_t offset,
uint32_t bytes, uint32_t *val);
uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes);
void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset, uint32_t bytes, uint32_t val);
#endif /* PCI_PRIV_H_ */

70
hypervisor/dm/vpci/pci_pt.c
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@ -32,81 +32,11 @@
#include <hypervisor.h>
#include "pci_priv.h"
static spinlock_t pci_device_lock = { .head = 0, .tail = 0 };
static inline uint32_t pci_bar_base(uint32_t bar)
{
return bar & PCIM_BAR_MEM_BASE;
}
static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
{
uint32_t addr = (uint32_t)bdf.value;
addr <<= 8U;
addr |= (offset | PCI_CFG_ENABLE);
return addr;
}
static uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev,
uint32_t offset, uint32_t bytes)
{
uint32_t addr;
uint32_t val;
spinlock_obtain(&pci_device_lock);
addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4U);
/* Read result from DATA register */
switch (bytes) {
case 1U:
val = pio_read8(PCI_CONFIG_DATA + (offset & 3U));
break;
case 2U:
val = pio_read16(PCI_CONFIG_DATA + (offset & 2U));
break;
default:
val = pio_read32(PCI_CONFIG_DATA);
break;
}
spinlock_release(&pci_device_lock);
return val;
}
static void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset,
uint32_t bytes, uint32_t val)
{
uint32_t addr;
spinlock_obtain(&pci_device_lock);
addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4U);
/* Write value to DATA register */
switch (bytes) {
case 1U:
pio_write8(val, PCI_CONFIG_DATA + (offset & 3U));
break;
case 2U:
pio_write16(val, PCI_CONFIG_DATA + (offset & 2U));
break;
default:
pio_write32(val, PCI_CONFIG_DATA);
break;
}
spinlock_release(&pci_device_lock);
}
static int vdev_pt_init_validate(struct pci_vdev *vdev)
{
uint32_t idx;

0
hypervisor/include/dm/vpci/vpci.h → hypervisor/include/dm/vpci.h
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