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https://github.com/projectacrn/acrn-hypervisor.git
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hv: don't need to save boot context
- Since de-privilege boot is removed, we no longer need to save boot context in boot time. - cpu_primary_start_64 is not an entry for ACRN hypervisor any more, and can be removed. Tracked-On: #5197 Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Zide Chen
wenlingz
parent
2309cadc9a
commit
a776ccca94
@ -206,7 +206,6 @@ endif
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# platform boot component
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BOOT_S_SRCS += arch/x86/boot/cpu_primary.S
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BOOT_S_SRCS += arch/x86/boot/cpu_save_boot_ctx.S
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BOOT_S_SRCS += arch/x86/boot/trampoline.S
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BOOT_C_SRCS += boot/multiboot.c
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ifeq ($(CONFIG_MULTIBOOT2),y)
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@ -160,7 +160,7 @@ cpu_primary_start_32:
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test $0x400, %eax
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/* jump to 64bit entry if it is already in long mode */
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jne cpu_primary_start_64
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jne primary_start_long_mode
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/* Disable paging */
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mov %cr0, %ebx
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@ -219,23 +219,7 @@ jmpbuf_32:
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/* 0x0008 = HOST_GDT_RING0_CODE_SEL */
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.word 0x0008
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/*
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* Offset from the beginning of the entry section.
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* This is to make sure that cpu_primary_start_64 is linked to a known address
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* so that efi-stub knows where to pass control to hypervisor.
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*/
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.org 0x200
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.code64
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.global cpu_primary_start_64
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cpu_primary_start_64:
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/* save the MULTBOOT magic number & MBI */
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lea boot_regs(%rip), %rax
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movl %edi, (%rax)
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movl %esi, 4(%rax)
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/* Save boot context from 64bit mode */
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call cpu_primary_save_64
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.code64
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primary_start_long_mode:
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/* Initialize temporary stack pointer, size = 0x1000 */
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@ -1,60 +0,0 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <boot_context.h>
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.section entry, "ax"
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.align 8
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.code64
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.global cpu_primary_save_64
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cpu_primary_save_64:
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/* save context from 64bit mode */
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lea boot_context(%rip), %r8
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sgdt BOOT_CTX_GDT_OFFSET(%r8)
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sidt BOOT_CTX_IDT_OFFSET(%r8)
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str BOOT_CTX_TR_SEL_OFFSET(%r8)
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sldt BOOT_CTX_LDT_SEL_OFFSET(%r8)
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mov %cr0, %rcx
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mov %rcx, BOOT_CTX_CR0_OFFSET(%r8)
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mov %cr3, %rcx
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mov %rcx, BOOT_CTX_CR3_OFFSET(%r8)
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mov %cr4, %rcx
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mov %rcx, BOOT_CTX_CR4_OFFSET(%r8)
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mov %cs, %cx
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mov %cx, BOOT_CTX_CS_SEL_OFFSET(%r8)
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lar %ecx, %ecx
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/* CS AR start from bit 8 */
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shr $8, %ecx
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/* Clear Limit field, bit 8-11 */
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andl $0x0000f0ff, %ecx
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mov %ecx, BOOT_CTX_CS_AR_OFFSET(%r8)
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/* Save CS limit field */
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mov %cs, %cx
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xor %edx, %edx
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lsl %ecx, %edx
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mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%r8)
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mov %es, BOOT_CTX_ES_SEL_OFFSET(%r8)
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mov %ss, BOOT_CTX_SS_SEL_OFFSET(%r8)
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mov %ds, BOOT_CTX_DS_SEL_OFFSET(%r8)
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mov %fs, BOOT_CTX_FS_SEL_OFFSET(%r8)
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mov %gs, BOOT_CTX_GS_SEL_OFFSET(%r8)
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/* 0xc0000080 = MSR_IA32_EFER */
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movl $0xc0000080, %ecx
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rdmsr
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movl %eax, BOOT_CTX_EFER_LOW_OFFSET(%r8)
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movl %edx, BOOT_CTX_EFER_HIGH_OFFSET(%r8)
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ret
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.text
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.align 8
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.global boot_context
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boot_context:
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.rept SIZE_OF_BOOT_CTX
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.byte 0x00
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.endr
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@ -9,7 +9,6 @@
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#include <errno.h>
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#include <per_cpu.h>
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#include <irq.h>
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#include <boot_context.h>
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#include <boot.h>
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#include <pgtable.h>
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#include <zeropage.h>
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@ -1,51 +0,0 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_CTX_H
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#define BOOT_CTX_H
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#ifdef ASSEMBLER
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#define BOOT_CTX_CR0_OFFSET 176
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#define BOOT_CTX_CR3_OFFSET 192
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#define BOOT_CTX_CR4_OFFSET 184
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#define BOOT_CTX_IDT_OFFSET 144
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#define BOOT_CTX_GDT_OFFSET 128
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#define BOOT_CTX_LDT_SEL_OFFSET 280
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#define BOOT_CTX_TR_SEL_OFFSET 282
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#define BOOT_CTX_CS_SEL_OFFSET 268
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#define BOOT_CTX_SS_SEL_OFFSET 270
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#define BOOT_CTX_DS_SEL_OFFSET 272
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#define BOOT_CTX_ES_SEL_OFFSET 274
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#define BOOT_CTX_FS_SEL_OFFSET 276
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#define BOOT_CTX_GS_SEL_OFFSET 278
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#define BOOT_CTX_CS_AR_OFFSET 248
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#define BOOT_CTX_CS_LIMIT_OFFSET 252
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#define BOOT_CTX_EFER_LOW_OFFSET 200
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#define BOOT_CTX_EFER_HIGH_OFFSET 204
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#define SIZE_OF_BOOT_CTX 296
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#else
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#define BOOT_CTX_CR0_OFFSET 176U
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#define BOOT_CTX_CR3_OFFSET 192U
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#define BOOT_CTX_CR4_OFFSET 184U
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#define BOOT_CTX_IDT_OFFSET 144U
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#define BOOT_CTX_GDT_OFFSET 128U
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#define BOOT_CTX_LDT_SEL_OFFSET 280U
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#define BOOT_CTX_TR_SEL_OFFSET 282U
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#define BOOT_CTX_CS_SEL_OFFSET 268U
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#define BOOT_CTX_SS_SEL_OFFSET 270U
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#define BOOT_CTX_DS_SEL_OFFSET 272U
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#define BOOT_CTX_ES_SEL_OFFSET 274U
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#define BOOT_CTX_FS_SEL_OFFSET 276U
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#define BOOT_CTX_GS_SEL_OFFSET 278U
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#define BOOT_CTX_CS_AR_OFFSET 248U
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#define BOOT_CTX_CS_LIMIT_OFFSET 252U
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#define BOOT_CTX_EFER_LOW_OFFSET 200U
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#define BOOT_CTX_EFER_HIGH_OFFSET 204U
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#define SIZE_OF_BOOT_CTX 296U
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struct acrn_vcpu_regs;
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extern struct acrn_vcpu_regs boot_context;
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#endif /* ASSEMBLER */
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#endif /* BOOT_CTX_H */
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@ -5,7 +5,6 @@
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*/
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#include <util.h>
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#include <boot_context.h>
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#include <acrn_common.h>
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#include <vcpu.h>
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#include <mmu.h>
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@ -36,23 +35,6 @@ typedef int32_t CAT_(CTA_DummyType,__LINE__)[(expr) ? 1 : -1]
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/* Build time sanity checks to make sure hard-coded offset
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* is matching the actual offset!
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*/
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CTASSERT(BOOT_CTX_CR0_OFFSET == offsetof(struct acrn_vcpu_regs, cr0));
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CTASSERT(BOOT_CTX_CR3_OFFSET == offsetof(struct acrn_vcpu_regs, cr3));
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CTASSERT(BOOT_CTX_CR4_OFFSET == offsetof(struct acrn_vcpu_regs, cr4));
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CTASSERT(BOOT_CTX_IDT_OFFSET == offsetof(struct acrn_vcpu_regs, idt));
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CTASSERT(BOOT_CTX_GDT_OFFSET == offsetof(struct acrn_vcpu_regs, gdt));
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CTASSERT(BOOT_CTX_LDT_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ldt_sel));
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CTASSERT(BOOT_CTX_TR_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, tr_sel));
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CTASSERT(BOOT_CTX_CS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, cs_sel));
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CTASSERT(BOOT_CTX_SS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ss_sel));
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CTASSERT(BOOT_CTX_DS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ds_sel));
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CTASSERT(BOOT_CTX_ES_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, es_sel));
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CTASSERT(BOOT_CTX_FS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, fs_sel));
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CTASSERT(BOOT_CTX_GS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, gs_sel));
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CTASSERT(BOOT_CTX_CS_AR_OFFSET == offsetof(struct acrn_vcpu_regs, cs_ar));
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CTASSERT(BOOT_CTX_EFER_LOW_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer));
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CTASSERT(BOOT_CTX_EFER_HIGH_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer) + 4);
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CTASSERT(CPU_CONTEXT_OFFSET_RAX == offsetof(struct acrn_gp_regs, rax));
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CTASSERT(CPU_CONTEXT_OFFSET_RBX == offsetof(struct acrn_gp_regs, rbx));
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CTASSERT(CPU_CONTEXT_OFFSET_RCX == offsetof(struct acrn_gp_regs, rcx));
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