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HV: move the ve820 GPU OpRegion address

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The ve820 table' hpa1_low area is divided into two parts, which
is making the code too complicated and causing problems. Moving
the entries that divides the hpa1_low could make things easier.

This patch moves the GPU OpRegion to the tail area of 2G,
consecutive to the acpi data/nvs area.

before:
|<---low_1M--->|
|<---hpa1_low_part1--->|
|<---SSRAM--->|
|<---GPU_OpRegion--->|
|<---hpa1_low_part2--->|
|<---ACPI DATA--->|
|<---ACPI NVS--->|
---2G---

after:
|<---low_1M--->|
|<---hpa1_low_part1--->|
|<---SSRAM--->|
|<---hpa1_low_part2--->|
|<---GPU_OpRegion--->|
|<---ACPI DATA--->|
|<---ACPI NVS--->|
---2G---

Tracked-On: #6674

Signed-off-by: Zhou, Wu <wu.zhou@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Zhou, Wu
2021-09-03 15:48:25 +08:00
committed by wenlingz
parent e00421d5be
commit f1f6fe11c1
3 changed files with 9 additions and 7 deletions
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3
hypervisor/include/common/ptdev.h
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@@ -9,6 +9,7 @@
#include <list.h>
#include <asm/lib/spinlock.h>
#include <timer.h>
#include <vacpi.h>
enum intx_ctlr {
@@ -20,7 +21,7 @@ enum intx_ctlr {
#define PTDEV_INTR_INTX (1U << 1U)
#define GPU_OPREGION_SIZE 0x5000U
#define GPU_OPREGION_GPA 0x40880000U
#define GPU_OPREGION_GPA (VIRT_ACPI_DATA_ADDR - GPU_OPREGION_SIZE)
#define PCIR_ASLS_CTL 0xfcU /* register offset in PCIe configuration space for Opregion base address */
#define PCIM_ASLS_OPREGION_MASK 0xfffff000U /* opregion need 4KB aligned */