mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-09-01 08:56:55 +00:00
config-tools: update the generic_code with xform output
Replace folllowing python generated files with xslt transform outputs
which are formatted using clang-format:
misc/config_tools/data/generic_board/generic_code/
├── hybrid
│ ├── ivshmem_cfg.h
│ ├── misc_cfg.h
│ ├── pt_intx.c
│ ├── vm_configurations.c
│ └── vm_configurations.h
├── hybrid_rt
│ ├── ivshmem_cfg.h
│ ├── misc_cfg.h
│ ├── pt_intx.c
│ ├── vm_configurations.c
│ └── vm_configurations.h
├── industry
│ ├── ivshmem_cfg.h
│ ├── misc_cfg.h
│ ├── pt_intx.c
│ ├── vm_configurations.c
│ └── vm_configurations.h
└── logical_partition
├── ivshmem_cfg.h
├── misc_cfg.h
├── pt_intx.c
├── vm_configurations.c
└── vm_configurations.h
Tracked-On: #5980
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
This commit is contained in:
Yang,Yu-chu
wenlingz
@@ -1,8 +1,9 @@
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/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IVSHMEM_CFG_H
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#define IVSHMEM_CFG_H
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@@ -7,77 +7,48 @@
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#ifndef MISC_CFG_H
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#define MISC_CFG_H
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#define SOS_ROOTFS "root=/dev/sda3 "
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#define SOS_CONSOLE "console=ttyS0 "
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 5U
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#define SOS_BOOTARGS_DIFF "rw " \
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"rootwait " \
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"console=tty0 " \
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"consoleblank=0 " \
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"no_timer_check " \
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"quiet " \
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"loglevel=3 " \
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"i915.nuclear_pageflip=1 " \
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"swiotlb=131072 " \
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"maxcpus=3"
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#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
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#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
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#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
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#define SOS_ROOTFS "root=/dev/sda3"
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#define SOS_CONSOLE "console=ttyS0"
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#define SOS_COM1_BASE 0x3F8U
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#define SOS_COM1_IRQ 4U
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#define SOS_COM2_BASE 0x2F8U
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#define SOS_COM2_IRQ 5U
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#define SOS_BOOTARGS_DIFF \
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"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
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"swiotlb=131072 maxcpus=3"
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#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
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#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
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#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
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#ifdef CONFIG_RDT_ENABLED
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/*
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* The maximum CLOS that is allowed by ACRN hypervisor,
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* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
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* among all supported RDT resources in the platform. In other words, it is
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* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
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* CLOS allocations between all the RDT resources.
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*/
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#define HV_SUPPORTED_MAX_CLOS 0U
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/*
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* Max number of Cache Mask entries corresponding to each CLOS.
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* This can vary if CDP is enabled vs disabled, as each CLOS entry
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* will have corresponding cache mask values for Data and Code when
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* CDP is enabled.
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*/
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#define MAX_MBA_CLOS_NUM_ENTRIES 0U
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/* Max number of MBA delay entries corresponding to each CLOS. */
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#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
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#define CLOS_MASK_0 0xfffU
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#define CLOS_MASK_1 0xfffU
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#define CLOS_MASK_2 0xfffU
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#define CLOS_MASK_3 0xfffU
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#define CLOS_MASK_4 0xfffU
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#define CLOS_MASK_5 0xfffU
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#define CLOS_MASK_6 0xfffU
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#define CLOS_MASK_7 0xfffU
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#define CLOS_MASK_8 0xfffU
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#define CLOS_MASK_9 0xfffU
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#define CLOS_MASK_10 0xfffU
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#define CLOS_MASK_11 0xfffU
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#define CLOS_MASK_12 0xfffU
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#define CLOS_MASK_13 0xfffU
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#define CLOS_MASK_14 0xfffU
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#define CLOS_MASK_15 0xfffU
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#define VM0_VCPU_CLOS {0U}
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#define VM1_VCPU_CLOS {0U, 0U, 0U}
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#define VM2_VCPU_CLOS {0U}
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#define HV_SUPPORTED_MAX_CLOS 0U
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#define MAX_MBA_CLOS_NUM_ENTRIES 0U
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#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
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#define MBA_MASK_0 0U
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#define CLOS_MASK_0 0xfffU
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#define CLOS_MASK_1 0xfffU
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#define CLOS_MASK_2 0xfffU
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#define CLOS_MASK_3 0xfffU
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#define CLOS_MASK_4 0xfffU
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#define CLOS_MASK_5 0xfffU
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#define CLOS_MASK_6 0xfffU
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#define CLOS_MASK_7 0xfffU
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#define CLOS_MASK_8 0xfffU
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#define CLOS_MASK_9 0xfffU
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#define CLOS_MASK_10 0xfffU
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#define CLOS_MASK_11 0xfffU
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#define CLOS_MASK_12 0xfffU
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#define CLOS_MASK_13 0xfffU
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#define CLOS_MASK_14 0xfffU
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#define CLOS_MASK_15 0xfffU
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#define VM0_VCPU_CLOS \
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{ 0U }
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#define VM1_VCPU_CLOS \
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{ 0U, 0U, 0U }
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#define VM2_VCPU_CLOS \
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{ 0U }
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#endif
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#define VM0_BOOT_ARGS "reboot=acpi"
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#define VM0_PT_INTX_NUM 0U
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#define VM0_PT_INTX_NUM 0U
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#endif /* MISC_CFG_H */
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@@ -4,11 +4,11 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <x86/vm_config.h>
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#include <pci_devices.h>
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#include <vpci.h>
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#include <vbar_base.h>
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#include <mmu.h>
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#include <page.h>
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#include <x86/mmu.h>
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#include <x86/page.h>
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struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
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@@ -1,10 +1,8 @@
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/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <x86/vm_config.h>
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struct pt_intx_config vm0_pt_intx[1U];
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@@ -7,75 +7,68 @@
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#ifndef VBAR_BASE_H_
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#define VBAR_BASE_H_
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#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
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.vbar_base[2] = HI_MMIO_START + 0x0UL
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#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
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#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
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#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
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#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
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#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
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#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
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#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
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#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
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#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
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#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
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#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
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#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
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#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
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#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
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#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
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#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
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#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
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#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
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#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
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#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
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#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
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#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
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#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
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#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
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#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
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#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
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.vbar_base[1] = 0x80000000UL
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#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
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#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
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#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
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#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
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#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
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#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
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#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
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#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
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#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
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#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
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#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
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#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
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#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
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#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
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#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
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#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
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.vbar_base[2] = 0x834e7000UL
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#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
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#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
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.vbar_base[1] = 0x834f6000UL, \
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.vbar_base[5] = 0x834f5000UL
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#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
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#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
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#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
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#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
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#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
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#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
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#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
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#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
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#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
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#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
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#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
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#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
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.vbar_base[2] = 0x834f2000UL
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#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
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#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
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.vbar_base[4] = 0x83200000UL
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#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
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#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
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#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
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#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
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#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
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#endif /* VBAR_BASE_H_ */
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@@ -1,121 +1,133 @@
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/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
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* Copyright (C) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vm_config.h>
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#include <x86/vm_config.h>
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#include <vuart.h>
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#include <pci_dev.h>
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#include <x86/pci_dev.h>
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extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
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extern struct pt_intx_config vm0_pt_intx[1U];
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struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
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{ /* VM0 */
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{
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/* VM0 */
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CONFIG_SAFETY_VM(1),
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.name = "ACRN PRE-LAUNCHED VM0",
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.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
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.guest_flags = 0UL,
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#ifdef CONFIG_RDT_ENABLED
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.clos = VM0_VCPU_CLOS,
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#endif
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.memory = {
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.start_hpa = VM0_CONFIG_MEM_START_HPA,
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.size = VM0_CONFIG_MEM_SIZE,
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.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
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.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
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},
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.os_config = {
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.name = "Zephyr",
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.kernel_type = KERNEL_ZEPHYR,
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.kernel_mod_tag = "Zephyr_RawImage",
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.kernel_load_addr = 0x8000,
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.kernel_entry_addr = 0x8000,
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.bootargs = VM0_BOOT_ARGS,
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},
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.acpi_config = {
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.acpi_mod_tag = "ACPI_VM0",
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},
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.vuart[0] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM1_BASE,
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.irq = COM1_IRQ,
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},
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.vuart[1] = {
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.type = VUART_LEGACY_PIO,
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.addr.port_base = COM2_BASE,
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.irq = COM2_IRQ,
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.t_vuart.vm_id = 1U,
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.t_vuart.vuart_id = 1U,
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},
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.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
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.memory =
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{
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.start_hpa = VM0_CONFIG_MEM_START_HPA,
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.size = VM0_CONFIG_MEM_SIZE,
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.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
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.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
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},
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.os_config =
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{
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.name = "Zephyr",
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.kernel_type = KERNEL_ZEPHYR,
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.kernel_mod_tag = "Zephyr_RawImage",
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.kernel_load_addr = 0x8000,
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.kernel_entry_addr = 0x8000,
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},
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.acpi_config =
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{
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.acpi_mod_tag = "ACPI_VM0",
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},
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.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 1U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
#ifdef VM0_PASSTHROUGH_TPM
|
||||
.pt_tpm2 = true,
|
||||
.mmiodevs[0] = {
|
||||
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
|
||||
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
|
||||
.size = VM0_TPM_BUFFER_SIZE,
|
||||
},
|
||||
.mmiodevs[0] =
|
||||
{
|
||||
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
|
||||
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
|
||||
.size = VM0_TPM_BUFFER_SIZE,
|
||||
},
|
||||
#endif
|
||||
#ifdef P2SB_BAR_ADDR
|
||||
.pt_p2sb_bar = true,
|
||||
.mmiodevs[0] = {
|
||||
.base_gpa = P2SB_BAR_ADDR_GPA,
|
||||
.base_hpa = P2SB_BAR_ADDR,
|
||||
.size = P2SB_BAR_SIZE,
|
||||
},
|
||||
.mmiodevs[0] =
|
||||
{
|
||||
.base_gpa = P2SB_BAR_ADDR_GPA,
|
||||
.base_hpa = P2SB_BAR_ADDR,
|
||||
.size = P2SB_BAR_SIZE,
|
||||
},
|
||||
#endif
|
||||
.pt_intx_num = VM0_PT_INTX_NUM,
|
||||
.pt_intx = &vm0_pt_intx[0U],
|
||||
},
|
||||
{ /* VM1 */
|
||||
{
|
||||
/* VM1 */
|
||||
CONFIG_SOS_VM,
|
||||
.name = "ACRN SOS VM",
|
||||
|
||||
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
|
||||
/* Allow Service VM to reboot the system since it is the highest priority VM. */
|
||||
.guest_flags = 0UL,
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM1_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
|
||||
.memory = {
|
||||
.start_hpa = 0UL,
|
||||
},
|
||||
.os_config = {
|
||||
.name = "ACRN Service OS",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = SOS_VM_BOOTARGS,
|
||||
},
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM1_BASE,
|
||||
.irq = SOS_COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM2_BASE,
|
||||
.irq = SOS_COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.memory =
|
||||
{
|
||||
.start_hpa = 0UL,
|
||||
},
|
||||
.os_config =
|
||||
{
|
||||
.name = "ACRN Service OS",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = SOS_VM_BOOTARGS,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM1_BASE,
|
||||
.irq = SOS_COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM2_BASE,
|
||||
.irq = SOS_COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.pci_dev_num = 0U,
|
||||
.pci_devs = sos_pci_devs,
|
||||
},
|
||||
{ /* VM2 */
|
||||
{
|
||||
/* VM2 */
|
||||
CONFIG_POST_STD_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM2_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
@@ -1,36 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VM_CONFIGURATIONS_H
|
||||
#define VM_CONFIGURATIONS_H
|
||||
|
||||
#include <misc_cfg.h>
|
||||
#include <pci_devices.h>
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U;
|
||||
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
|
||||
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
|
||||
*/
|
||||
#define PRE_VM_NUM 1U
|
||||
#define SOS_VM_NUM 1U
|
||||
#define MAX_POST_VM_NUM 1U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 0U
|
||||
|
||||
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
|
||||
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
|
||||
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
|
||||
|
||||
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
|
||||
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
|
||||
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
|
||||
* bigger than CONFIG_MAX_KATA_VM_NUM. */
|
||||
#define PRE_VM_NUM 1U
|
||||
#define SOS_VM_NUM 1U
|
||||
#define MAX_POST_VM_NUM 1U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 0U
|
||||
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
|
||||
#define DM_OWNED_GUEST_FLAG_MASK \
|
||||
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
|
||||
GUEST_FLAG_IO_COMPLETION_POLLING)
|
||||
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
|
||||
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
|
||||
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
/* SOS_VM == VM1 */
|
||||
#define SOS_VM_BOOTARGS SOS_ROOTFS \
|
||||
SOS_CONSOLE \
|
||||
SOS_IDLE \
|
||||
SOS_BOOTARGS_DIFF
|
||||
#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF
|
||||
|
||||
#endif /* VM_CONFIGURATIONS_H */
|
||||
|
||||
@@ -1,28 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IVSHMEM_CFG_H
|
||||
#define IVSHMEM_CFG_H
|
||||
|
||||
#include <ivshmem.h>
|
||||
#include <pgtable.h>
|
||||
|
||||
#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0"
|
||||
|
||||
/*
|
||||
* The IVSHMEM_SHM_SIZE is the sum of all memory regions.
|
||||
* The size range of each memory region is [2MB, 512MB] and is a power of 2.
|
||||
*/
|
||||
#define IVSHMEM_SHM_SIZE 0x200000UL
|
||||
#define IVSHMEM_DEV_NUM 2UL
|
||||
#include <x86/pgtable.h>
|
||||
#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0"
|
||||
|
||||
/* The IVSHMEM_SHM_SIZE is the sum of all memory regions. The size range of each memory region is [2MB, 512MB] and is a
|
||||
* power of 2. */
|
||||
#define IVSHMEM_SHM_SIZE 0x200000UL
|
||||
#define IVSHMEM_DEV_NUM 2UL
|
||||
/* All user defined memory regions */
|
||||
#define IVSHMEM_SHM_REGIONS \
|
||||
{ \
|
||||
.name = IVSHMEM_SHM_REGION_0, \
|
||||
.size = 0x200000UL, /* 2M */ \
|
||||
#define IVSHMEM_SHM_REGIONS \
|
||||
{ \
|
||||
.name = IVSHMEM_SHM_REGION_0, \
|
||||
.size = 0x200000UL, \
|
||||
},
|
||||
|
||||
#endif /* IVSHMEM_CFG_H */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
@@ -7,87 +7,58 @@
|
||||
#ifndef MISC_CFG_H
|
||||
#define MISC_CFG_H
|
||||
|
||||
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
|
||||
#define SOS_CONSOLE "console=ttyS0 "
|
||||
#define SOS_COM1_BASE 0x3F8U
|
||||
#define SOS_COM1_IRQ 4U
|
||||
#define SOS_COM2_BASE 0x2F8U
|
||||
#define SOS_COM2_IRQ 5U
|
||||
|
||||
#define SOS_BOOTARGS_DIFF "rw " \
|
||||
"rootwait " \
|
||||
"console=tty0 " \
|
||||
"consoleblank=0 " \
|
||||
"no_timer_check " \
|
||||
"quiet " \
|
||||
"loglevel=3 " \
|
||||
"i915.nuclear_pageflip=1 " \
|
||||
"swiotlb=131072 " \
|
||||
"maxcpus=2"
|
||||
|
||||
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
|
||||
|
||||
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
|
||||
#define SOS_ROOTFS "root=/dev/nvme0n1p3"
|
||||
#define SOS_CONSOLE "console=ttyS0"
|
||||
#define SOS_COM1_BASE 0x3F8U
|
||||
#define SOS_COM1_IRQ 4U
|
||||
#define SOS_COM2_BASE 0x2F8U
|
||||
#define SOS_COM2_IRQ 5U
|
||||
|
||||
#define SOS_BOOTARGS_DIFF \
|
||||
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
|
||||
"swiotlb=131072 maxcpus=2"
|
||||
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
|
||||
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
|
||||
/*
|
||||
* The maximum CLOS that is allowed by ACRN hypervisor,
|
||||
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
|
||||
* among all supported RDT resources in the platform. In other words, it is
|
||||
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
|
||||
* CLOS allocations between all the RDT resources.
|
||||
*/
|
||||
#define HV_SUPPORTED_MAX_CLOS 0U
|
||||
|
||||
/*
|
||||
* Max number of Cache Mask entries corresponding to each CLOS.
|
||||
* This can vary if CDP is enabled vs disabled, as each CLOS entry
|
||||
* will have corresponding cache mask values for Data and Code when
|
||||
* CDP is enabled.
|
||||
*/
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
|
||||
|
||||
/* Max number of MBA delay entries corresponding to each CLOS. */
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
|
||||
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
|
||||
#define VM0_VCPU_CLOS {0U, 0U}
|
||||
#define VM1_VCPU_CLOS {0U, 0U}
|
||||
#define VM2_VCPU_CLOS {0U, 0U}
|
||||
#define VM3_VCPU_CLOS {0U}
|
||||
#define HV_SUPPORTED_MAX_CLOS 0U
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
|
||||
#define MBA_MASK_0 0U
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
#define VM0_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM1_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM2_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM3_VCPU_CLOS \
|
||||
{ 0U }
|
||||
#endif
|
||||
#define VM0_CONFIG_PCI_DEV_NUM 4U
|
||||
#define VM2_CONFIG_PCI_DEV_NUM 1U
|
||||
|
||||
#define VM0_CONFIG_PCI_DEV_NUM 4U
|
||||
#define VM2_CONFIG_PCI_DEV_NUM 1U
|
||||
|
||||
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 no_ipi_broadcast=1 \
|
||||
console=ttyS0 noxsave nohpet no_timer_check \
|
||||
ignore_loglevel consoleblank=0 tsc=reliable clocksource=tsc \
|
||||
x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 intel_pstate=disable \
|
||||
mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 \
|
||||
rcu_nocbs=1 nosoftlockup idle=poll irqaffinity=0 \
|
||||
reboot=acpi"
|
||||
|
||||
|
||||
#define VM0_PT_INTX_NUM 0U
|
||||
#define VM0_BOOT_ARGS \
|
||||
"rw rootwait root=/dev/sda3 no_ipi_broadcast=1 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel " \
|
||||
"consoleblank=0 tsc=reliable clocksource=tsc x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 " \
|
||||
"intel_pstate=disable mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 rcu_nocbs=1 nosoftlockup " \
|
||||
"idle=poll irqaffinity=0 reboot=acpi"
|
||||
#define VM0_PT_INTX_NUM 0U
|
||||
|
||||
#endif /* MISC_CFG_H */
|
||||
|
||||
@@ -4,19 +4,19 @@
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
#include <x86/vm_config.h>
|
||||
#include <pci_devices.h>
|
||||
#include <vpci.h>
|
||||
#include <vbar_base.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
#include <x86/mmu.h>
|
||||
#include <x86/page.h>
|
||||
#include <ivshmem_cfg.h>
|
||||
|
||||
/*
|
||||
* TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
|
||||
* passthrough device configuration and shm_name for ivshmem device configuration.
|
||||
*/
|
||||
#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
|
||||
#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
|
||||
|
||||
/*
|
||||
* TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
|
||||
@@ -44,7 +44,7 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U},
|
||||
.vdev_ops = &vpci_ivshmem_ops,
|
||||
.shm_region_name = IVSHMEM_SHM_REGION_0,
|
||||
IVSHMEM_DEVICE_0_VBAR
|
||||
IVSHMEM_DEVICE_0_VBAR,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -55,6 +55,6 @@ struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = {
|
||||
.emu_type = PCI_DEV_TYPE_HVEMUL,
|
||||
.vbdf.value = UNASSIGNED_VBDF,
|
||||
.vdev_ops = &vpci_ivshmem_ops,
|
||||
.shm_region_name = IVSHMEM_SHM_REGION_0
|
||||
.shm_region_name = IVSHMEM_SHM_REGION_0,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -1,10 +1,8 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
|
||||
#include <x86/vm_config.h>
|
||||
struct pt_intx_config vm0_pt_intx[1U];
|
||||
|
||||
|
||||
@@ -7,80 +7,70 @@
|
||||
#ifndef VBAR_BASE_H_
|
||||
#define VBAR_BASE_H_
|
||||
|
||||
#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, \
|
||||
.vbar_base[1] = 0x80001000UL, \
|
||||
.vbar_base[2] = 0x8020000cUL
|
||||
#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, .vbar_base[1] = 0x80001000UL, .vbar_base[2] = 0x8020000cUL
|
||||
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
|
||||
.vbar_base[2] = HI_MMIO_START + 0x0UL
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
|
||||
|
||||
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
|
||||
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
|
||||
|
||||
#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
|
||||
#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
|
||||
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
|
||||
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
|
||||
#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
|
||||
#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
|
||||
#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
|
||||
#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
|
||||
#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
|
||||
#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
|
||||
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
|
||||
.vbar_base[1] = 0x80000000UL
|
||||
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
|
||||
#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
|
||||
#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
|
||||
#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
|
||||
#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
|
||||
#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
|
||||
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
|
||||
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
|
||||
.vbar_base[2] = 0x834e7000UL
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
|
||||
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
|
||||
.vbar_base[1] = 0x834f6000UL, \
|
||||
.vbar_base[5] = 0x834f5000UL
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
|
||||
#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
|
||||
|
||||
#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
|
||||
#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL, \
|
||||
.vbar_base[2] = 0x80002000UL
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
|
||||
.vbar_base[2] = 0x834f2000UL
|
||||
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
|
||||
|
||||
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
|
||||
.vbar_base[4] = 0x83200000UL
|
||||
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
|
||||
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
|
||||
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
|
||||
@@ -1,142 +1,157 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <vm_config.h>
|
||||
#include <vuart.h>
|
||||
#include <pci_dev.h>
|
||||
|
||||
#include <x86/vm_config.h>
|
||||
#include <vuart.h>
|
||||
#include <x86/pci_dev.h>
|
||||
extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
|
||||
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
|
||||
extern struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM];
|
||||
|
||||
extern struct pt_intx_config vm0_pt_intx[1U];
|
||||
|
||||
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
{ /* VM0 */
|
||||
{
|
||||
/* VM0 */
|
||||
CONFIG_PRE_RT_VM(1),
|
||||
.name = "ACRN PRE-LAUNCHED VM0",
|
||||
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
|
||||
.guest_flags = (GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM0_VCPU_CLOS,
|
||||
#endif
|
||||
.memory = {
|
||||
.start_hpa = VM0_CONFIG_MEM_START_HPA,
|
||||
.size = VM0_CONFIG_MEM_SIZE,
|
||||
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
|
||||
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
|
||||
},
|
||||
.os_config = {
|
||||
.name = "PREEMPT-RT",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "RT_bzImage",
|
||||
.bootargs = VM0_BOOT_ARGS,
|
||||
},
|
||||
.acpi_config = {
|
||||
.acpi_mod_tag = "ACPI_VM0",
|
||||
},
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 1U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
|
||||
.memory =
|
||||
{
|
||||
.start_hpa = VM0_CONFIG_MEM_START_HPA,
|
||||
.size = VM0_CONFIG_MEM_SIZE,
|
||||
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
|
||||
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
|
||||
},
|
||||
.os_config =
|
||||
{
|
||||
.name = "PREEMPT-RT",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "RT_bzImage",
|
||||
.bootargs = VM0_BOOT_ARGS,
|
||||
},
|
||||
.acpi_config =
|
||||
{
|
||||
.acpi_mod_tag = "ACPI_VM0",
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 1U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.pci_dev_num = VM0_CONFIG_PCI_DEV_NUM,
|
||||
.pci_devs = vm0_pci_devs,
|
||||
#ifdef VM0_PASSTHROUGH_TPM
|
||||
.pt_tpm2 = true,
|
||||
.mmiodevs[0] = {
|
||||
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
|
||||
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
|
||||
.size = VM0_TPM_BUFFER_SIZE,
|
||||
},
|
||||
.mmiodevs[0] =
|
||||
{
|
||||
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
|
||||
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
|
||||
.size = VM0_TPM_BUFFER_SIZE,
|
||||
},
|
||||
#endif
|
||||
#ifdef P2SB_BAR_ADDR
|
||||
.pt_p2sb_bar = true,
|
||||
.mmiodevs[0] = {
|
||||
.base_gpa = P2SB_BAR_ADDR_GPA,
|
||||
.base_hpa = P2SB_BAR_ADDR,
|
||||
.size = P2SB_BAR_SIZE,
|
||||
},
|
||||
.mmiodevs[0] =
|
||||
{
|
||||
.base_gpa = P2SB_BAR_ADDR_GPA,
|
||||
.base_hpa = P2SB_BAR_ADDR,
|
||||
.size = P2SB_BAR_SIZE,
|
||||
},
|
||||
#endif
|
||||
.pt_intx_num = VM0_PT_INTX_NUM,
|
||||
.pt_intx = &vm0_pt_intx[0U],
|
||||
},
|
||||
{ /* VM1 */
|
||||
{
|
||||
/* VM1 */
|
||||
CONFIG_SOS_VM,
|
||||
.name = "ACRN SOS VM",
|
||||
|
||||
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
|
||||
/* Allow Service VM to reboot the system since it is the highest priority VM. */
|
||||
.guest_flags = 0UL,
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM1_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
|
||||
.memory = {
|
||||
.start_hpa = 0UL,
|
||||
},
|
||||
.os_config = {
|
||||
.name = "ACRN Service OS",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = SOS_VM_BOOTARGS,
|
||||
},
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM1_BASE,
|
||||
.irq = SOS_COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM2_BASE,
|
||||
.irq = SOS_COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.memory =
|
||||
{
|
||||
.start_hpa = 0UL,
|
||||
},
|
||||
.os_config =
|
||||
{
|
||||
.name = "ACRN Service OS",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = SOS_VM_BOOTARGS,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM1_BASE,
|
||||
.irq = SOS_COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM2_BASE,
|
||||
.irq = SOS_COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.pci_dev_num = 0U,
|
||||
.pci_devs = sos_pci_devs,
|
||||
},
|
||||
{ /* VM2 */
|
||||
{
|
||||
/* VM2 */
|
||||
CONFIG_POST_STD_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM2_VCPU_CLOS,
|
||||
#endif
|
||||
/* The PCI device configuration is only for in-hypervisor vPCI devices. */
|
||||
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.pci_dev_num = VM2_CONFIG_PCI_DEV_NUM,
|
||||
.pci_devs = vm2_pci_devs,
|
||||
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
{ /* VM3 */
|
||||
{
|
||||
/* VM3 */
|
||||
CONFIG_POST_STD_VM(2),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM3_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
@@ -1,36 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VM_CONFIGURATIONS_H
|
||||
#define VM_CONFIGURATIONS_H
|
||||
|
||||
#include <misc_cfg.h>
|
||||
#include <pci_devices.h>
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U;
|
||||
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
|
||||
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
|
||||
*/
|
||||
#define PRE_VM_NUM 1U
|
||||
#define SOS_VM_NUM 1U
|
||||
#define MAX_POST_VM_NUM 2U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 0U
|
||||
|
||||
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
|
||||
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
|
||||
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
|
||||
|
||||
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
|
||||
#define VM0_CONFIG_MEM_SIZE 0x40000000UL
|
||||
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
|
||||
* bigger than CONFIG_MAX_KATA_VM_NUM. */
|
||||
#define PRE_VM_NUM 1U
|
||||
#define SOS_VM_NUM 1U
|
||||
#define MAX_POST_VM_NUM 2U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 0U
|
||||
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
|
||||
#define DM_OWNED_GUEST_FLAG_MASK \
|
||||
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
|
||||
GUEST_FLAG_IO_COMPLETION_POLLING)
|
||||
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
|
||||
#define VM0_CONFIG_MEM_SIZE 0x40000000UL
|
||||
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
/* SOS_VM == VM1 */
|
||||
#define SOS_VM_BOOTARGS SOS_ROOTFS \
|
||||
SOS_CONSOLE \
|
||||
SOS_IDLE \
|
||||
SOS_BOOTARGS_DIFF
|
||||
#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF
|
||||
|
||||
#endif /* VM_CONFIGURATIONS_H */
|
||||
|
||||
@@ -1,8 +1,9 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IVSHMEM_CFG_H
|
||||
#define IVSHMEM_CFG_H
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
@@ -7,85 +7,63 @@
|
||||
#ifndef MISC_CFG_H
|
||||
#define MISC_CFG_H
|
||||
|
||||
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
|
||||
#define SOS_CONSOLE "console=ttyS3 "
|
||||
#define SOS_COM1_BASE 0x2E8U
|
||||
#define SOS_COM1_IRQ 3U
|
||||
#define SOS_COM2_BASE 0x3F8U
|
||||
#define SOS_COM2_IRQ 4U
|
||||
|
||||
#define SOS_BOOTARGS_DIFF "rw " \
|
||||
"rootwait " \
|
||||
"console=tty0 " \
|
||||
"consoleblank=0 " \
|
||||
"no_timer_check " \
|
||||
"quiet " \
|
||||
"loglevel=3 " \
|
||||
"i915.nuclear_pageflip=1 " \
|
||||
"swiotlb=131072 " \
|
||||
"maxcpus=4"
|
||||
|
||||
|
||||
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
|
||||
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
|
||||
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define SOS_ROOTFS "root=/dev/nvme0n1p3"
|
||||
#define SOS_CONSOLE "console=ttyS3"
|
||||
#define SOS_COM1_BASE 0x3F8U
|
||||
#define SOS_COM1_IRQ 3U
|
||||
#define SOS_COM2_BASE 0x2F8U
|
||||
#define SOS_COM2_IRQ 4U
|
||||
|
||||
#define SOS_BOOTARGS_DIFF \
|
||||
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
|
||||
"swiotlb=131072 maxcpus=4"
|
||||
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
|
||||
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
|
||||
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
|
||||
/*
|
||||
* The maximum CLOS that is allowed by ACRN hypervisor,
|
||||
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
|
||||
* among all supported RDT resources in the platform. In other words, it is
|
||||
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
|
||||
* CLOS allocations between all the RDT resources.
|
||||
*/
|
||||
#define HV_SUPPORTED_MAX_CLOS 16U
|
||||
|
||||
/*
|
||||
* Max number of Cache Mask entries corresponding to each CLOS.
|
||||
* This can vary if CDP is enabled vs disabled, as each CLOS entry
|
||||
* will have corresponding cache mask values for Data and Code when
|
||||
* CDP is enabled.
|
||||
*/
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 16U
|
||||
|
||||
/* Max number of MBA delay entries corresponding to each CLOS. */
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 16U
|
||||
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
|
||||
#define VM0_VCPU_CLOS {0U}
|
||||
#define VM1_VCPU_CLOS {0U, 0U}
|
||||
#define VM2_VCPU_CLOS {0U, 0U}
|
||||
#define VM3_VCPU_CLOS {0U, 0U}
|
||||
#define VM4_VCPU_CLOS {0U, 0U}
|
||||
#define VM5_VCPU_CLOS {0U, 0U}
|
||||
#define VM6_VCPU_CLOS {0U, 0U}
|
||||
#define VM7_VCPU_CLOS {0U, 0U}
|
||||
#define HV_SUPPORTED_MAX_CLOS 16U
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 16U
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 16U
|
||||
#define MBA_MASK_0 0U
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
#define VM0_VCPU_CLOS \
|
||||
{ 0U }
|
||||
#define VM1_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM2_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM3_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM4_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM5_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM6_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM7_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#define VM0_PT_INTX_NUM 0U
|
||||
#define VM0_PT_INTX_NUM 0U
|
||||
|
||||
#endif /* MISC_CFG_H */
|
||||
|
||||
@@ -4,11 +4,11 @@
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
#include <x86/vm_config.h>
|
||||
#include <pci_devices.h>
|
||||
#include <vpci.h>
|
||||
#include <vbar_base.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
#include <x86/mmu.h>
|
||||
#include <x86/page.h>
|
||||
|
||||
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
|
||||
|
||||
@@ -1,10 +1,8 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
|
||||
#include <x86/vm_config.h>
|
||||
struct pt_intx_config vm0_pt_intx[1U];
|
||||
|
||||
|
||||
@@ -7,75 +7,68 @@
|
||||
#ifndef VBAR_BASE_H_
|
||||
#define VBAR_BASE_H_
|
||||
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
|
||||
.vbar_base[2] = HI_MMIO_START + 0x0UL
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
|
||||
|
||||
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
|
||||
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
|
||||
|
||||
#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
|
||||
#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
|
||||
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
|
||||
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
|
||||
#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
|
||||
#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
|
||||
#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
|
||||
#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
|
||||
#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
|
||||
#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
|
||||
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
|
||||
.vbar_base[1] = 0x80000000UL
|
||||
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
|
||||
#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
|
||||
#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
|
||||
#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
|
||||
#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
|
||||
#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
|
||||
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
|
||||
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
|
||||
.vbar_base[2] = 0x834e7000UL
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
|
||||
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
|
||||
.vbar_base[1] = 0x834f6000UL, \
|
||||
.vbar_base[5] = 0x834f5000UL
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
|
||||
#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
|
||||
|
||||
#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
|
||||
#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
|
||||
.vbar_base[2] = 0x834f2000UL
|
||||
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
|
||||
|
||||
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
|
||||
.vbar_base[4] = 0x83200000UL
|
||||
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
|
||||
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
|
||||
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
|
||||
@@ -1,164 +1,186 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <vm_config.h>
|
||||
|
||||
#include <x86/vm_config.h>
|
||||
#include <vuart.h>
|
||||
#include <pci_dev.h>
|
||||
|
||||
#include <x86/pci_dev.h>
|
||||
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
|
||||
|
||||
extern struct pt_intx_config vm0_pt_intx[1U];
|
||||
|
||||
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
{ /* VM0 */
|
||||
{
|
||||
/* VM0 */
|
||||
CONFIG_SOS_VM,
|
||||
.name = "ACRN SOS VM",
|
||||
|
||||
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
|
||||
/* Allow Service VM to reboot the system since it is the highest priority VM. */
|
||||
.guest_flags = 0UL,
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM0_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
|
||||
.memory = {
|
||||
.start_hpa = 0UL,
|
||||
},
|
||||
.os_config = {
|
||||
.name = "ACRN Service OS",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = SOS_VM_BOOTARGS,
|
||||
},
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM1_BASE,
|
||||
.irq = SOS_COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM2_BASE,
|
||||
.irq = SOS_COM2_IRQ,
|
||||
.t_vuart.vm_id = 2U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.memory =
|
||||
{
|
||||
.start_hpa = 0UL,
|
||||
},
|
||||
.os_config =
|
||||
{
|
||||
.name = "ACRN Service OS",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = SOS_VM_BOOTARGS,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM1_BASE,
|
||||
.irq = SOS_COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = SOS_COM2_BASE,
|
||||
.irq = SOS_COM2_IRQ,
|
||||
.t_vuart.vm_id = 2U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.pci_dev_num = 0U,
|
||||
.pci_devs = sos_pci_devs,
|
||||
},
|
||||
{ /* VM1 */
|
||||
{
|
||||
/* VM1 */
|
||||
CONFIG_POST_STD_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM1_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
{ /* VM2 */
|
||||
{
|
||||
/* VM2 */
|
||||
CONFIG_POST_RT_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM2_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
},
|
||||
{ /* VM3 */
|
||||
{
|
||||
/* VM3 */
|
||||
CONFIG_POST_STD_VM(2),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM3_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
{ /* VM4 */
|
||||
{
|
||||
/* VM4 */
|
||||
CONFIG_POST_STD_VM(3),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM4_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM4_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
{ /* VM5 */
|
||||
{
|
||||
/* VM5 */
|
||||
CONFIG_POST_STD_VM(4),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM5_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM5_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
{ /* VM6 */
|
||||
{
|
||||
/* VM6 */
|
||||
CONFIG_POST_STD_VM(5),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM6_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM6_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
{ /* VM7 */
|
||||
{
|
||||
/* VM7 */
|
||||
CONFIG_KATA_VM(1),
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM7_VCPU_CLOS,
|
||||
#endif
|
||||
.cpu_affinity = VM7_CONFIG_CPU_AFFINITY,
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = INVALID_COM_BASE,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
@@ -1,31 +1,25 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VM_CONFIGURATIONS_H
|
||||
#define VM_CONFIGURATIONS_H
|
||||
|
||||
#include <misc_cfg.h>
|
||||
#include <pci_devices.h>
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U;
|
||||
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
|
||||
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
|
||||
*/
|
||||
#define PRE_VM_NUM 0U
|
||||
#define SOS_VM_NUM 1U
|
||||
#define MAX_POST_VM_NUM 7U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 1U
|
||||
|
||||
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
|
||||
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
|
||||
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
|
||||
* bigger than CONFIG_MAX_KATA_VM_NUM. */
|
||||
#define PRE_VM_NUM 0U
|
||||
#define SOS_VM_NUM 1U
|
||||
#define MAX_POST_VM_NUM 7U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 1U
|
||||
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
|
||||
#define DM_OWNED_GUEST_FLAG_MASK \
|
||||
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
|
||||
GUEST_FLAG_IO_COMPLETION_POLLING)
|
||||
/* SOS_VM == VM0 */
|
||||
#define SOS_VM_BOOTARGS SOS_ROOTFS \
|
||||
SOS_CONSOLE \
|
||||
SOS_IDLE \
|
||||
SOS_BOOTARGS_DIFF
|
||||
#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF
|
||||
|
||||
#endif /* VM_CONFIGURATIONS_H */
|
||||
|
||||
@@ -1,8 +1,9 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef IVSHMEM_CFG_H
|
||||
#define IVSHMEM_CFG_H
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
@@ -7,62 +7,41 @@
|
||||
#ifndef MISC_CFG_H
|
||||
#define MISC_CFG_H
|
||||
|
||||
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
|
||||
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
|
||||
|
||||
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
|
||||
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
|
||||
/*
|
||||
* The maximum CLOS that is allowed by ACRN hypervisor,
|
||||
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
|
||||
* among all supported RDT resources in the platform. In other words, it is
|
||||
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
|
||||
* CLOS allocations between all the RDT resources.
|
||||
*/
|
||||
#define HV_SUPPORTED_MAX_CLOS 0U
|
||||
|
||||
/*
|
||||
* Max number of Cache Mask entries corresponding to each CLOS.
|
||||
* This can vary if CDP is enabled vs disabled, as each CLOS entry
|
||||
* will have corresponding cache mask values for Data and Code when
|
||||
* CDP is enabled.
|
||||
*/
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
|
||||
|
||||
/* Max number of MBA delay entries corresponding to each CLOS. */
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
|
||||
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
|
||||
#define VM0_VCPU_CLOS {0U, 0U}
|
||||
#define VM1_VCPU_CLOS {0U, 0U}
|
||||
#define HV_SUPPORTED_MAX_CLOS 0U
|
||||
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
|
||||
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
|
||||
#define MBA_MASK_0 0U
|
||||
#define CLOS_MASK_0 0xfffU
|
||||
#define CLOS_MASK_1 0xfffU
|
||||
#define CLOS_MASK_2 0xfffU
|
||||
#define CLOS_MASK_3 0xfffU
|
||||
#define CLOS_MASK_4 0xfffU
|
||||
#define CLOS_MASK_5 0xfffU
|
||||
#define CLOS_MASK_6 0xfffU
|
||||
#define CLOS_MASK_7 0xfffU
|
||||
#define CLOS_MASK_8 0xfffU
|
||||
#define CLOS_MASK_9 0xfffU
|
||||
#define CLOS_MASK_10 0xfffU
|
||||
#define CLOS_MASK_11 0xfffU
|
||||
#define CLOS_MASK_12 0xfffU
|
||||
#define CLOS_MASK_13 0xfffU
|
||||
#define CLOS_MASK_14 0xfffU
|
||||
#define CLOS_MASK_15 0xfffU
|
||||
#define VM0_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#define VM1_VCPU_CLOS \
|
||||
{ 0U, 0U }
|
||||
#endif
|
||||
|
||||
|
||||
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \
|
||||
noxsave nohpet no_timer_check ignore_loglevel \
|
||||
log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi"
|
||||
|
||||
#define VM1_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \
|
||||
noxsave nohpet no_timer_check ignore_loglevel \
|
||||
log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi"
|
||||
|
||||
|
||||
#define VM0_PT_INTX_NUM 0U
|
||||
#define VM0_BOOT_ARGS \
|
||||
"rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \
|
||||
"consoleblank=0 tsc=reliable reboot=acpi"
|
||||
#define VM1_BOOT_ARGS \
|
||||
"rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \
|
||||
"consoleblank=0 tsc=reliable reboot=acpi"
|
||||
#define VM0_PT_INTX_NUM 0U
|
||||
|
||||
#endif /* MISC_CFG_H */
|
||||
|
||||
@@ -4,9 +4,9 @@
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
#include <x86/vm_config.h>
|
||||
#include <pci_devices.h>
|
||||
#include <vpci.h>
|
||||
#include <vbar_base.h>
|
||||
#include <mmu.h>
|
||||
#include <page.h>
|
||||
#include <x86/mmu.h>
|
||||
#include <x86/page.h>
|
||||
|
||||
@@ -1,10 +1,8 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <vm_config.h>
|
||||
|
||||
#include <x86/vm_config.h>
|
||||
struct pt_intx_config vm0_pt_intx[1U];
|
||||
|
||||
|
||||
@@ -7,75 +7,68 @@
|
||||
#ifndef VBAR_BASE_H_
|
||||
#define VBAR_BASE_H_
|
||||
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
|
||||
.vbar_base[2] = HI_MMIO_START + 0x0UL
|
||||
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
|
||||
|
||||
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
|
||||
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
|
||||
|
||||
#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
|
||||
#define SYSTEM_PERIPHERAL_1_VBAR .vbar_base[0] = 0x83000000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
|
||||
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = 0x83441000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
|
||||
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = 0x83444000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
|
||||
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = 0x834d8000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
|
||||
#define SERIAL_BUS_CONTROLLER_3_VBAR .vbar_base[0] = 0x83445000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
|
||||
#define SERIAL_BUS_CONTROLLER_4_VBAR .vbar_base[0] = 0x83446000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
|
||||
#define SERIAL_BUS_CONTROLLER_5_VBAR .vbar_base[0] = 0x83447000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
|
||||
#define SERIAL_BUS_CONTROLLER_6_VBAR .vbar_base[0] = 0x83448000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
|
||||
#define SERIAL_BUS_CONTROLLER_7_VBAR .vbar_base[0] = 0x834da000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
|
||||
#define SERIAL_BUS_CONTROLLER_8_VBAR .vbar_base[0] = 0x834dc000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
|
||||
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
|
||||
|
||||
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
|
||||
.vbar_base[1] = 0x80000000UL
|
||||
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
|
||||
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
|
||||
#define COMMUNICATION_CONTROLLER_1_VBAR .vbar_base[0] = 0x845fc000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
|
||||
#define COMMUNICATION_CONTROLLER_2_VBAR .vbar_base[0] = 0x834eb000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
|
||||
#define COMMUNICATION_CONTROLLER_3_VBAR .vbar_base[0] = 0x83449000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
|
||||
#define COMMUNICATION_CONTROLLER_4_VBAR .vbar_base[0] = 0x8344a000UL
|
||||
|
||||
#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
|
||||
#define COMMUNICATION_CONTROLLER_5_VBAR .vbar_base[0] = 0x8344b000UL
|
||||
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
|
||||
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
|
||||
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
|
||||
.vbar_base[2] = 0x834e7000UL
|
||||
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
|
||||
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
|
||||
.vbar_base[1] = 0x834f6000UL, \
|
||||
.vbar_base[5] = 0x834f5000UL
|
||||
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
|
||||
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
|
||||
|
||||
#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
|
||||
#define SD_HOST_CONTROLLER_1_VBAR .vbar_base[0] = 0x834ef000UL
|
||||
|
||||
#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
|
||||
#define NON_VGA_UNCLASSIFIED_DEVICE_0_VBAR .vbar_base[0] = 0x83400000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
|
||||
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
|
||||
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
|
||||
|
||||
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
|
||||
.vbar_base[2] = 0x834f2000UL
|
||||
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
|
||||
|
||||
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
|
||||
.vbar_base[4] = 0x83200000UL
|
||||
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
|
||||
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
|
||||
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL
|
||||
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
|
||||
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = 0x83300000UL
|
||||
|
||||
#endif /* VBAR_BASE_H_ */
|
||||
|
||||
@@ -1,104 +1,116 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <vm_config.h>
|
||||
|
||||
#include <x86/vm_config.h>
|
||||
#include <vuart.h>
|
||||
#include <pci_dev.h>
|
||||
|
||||
|
||||
#include <x86/pci_dev.h>
|
||||
extern struct pt_intx_config vm0_pt_intx[1U];
|
||||
|
||||
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
|
||||
{ /* VM0 */
|
||||
{
|
||||
/* VM0 */
|
||||
CONFIG_PRE_STD_VM(1),
|
||||
.name = "ACRN PRE-LAUNCHED VM0",
|
||||
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
|
||||
.guest_flags = 0UL,
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM0_VCPU_CLOS,
|
||||
#endif
|
||||
.memory = {
|
||||
.start_hpa = VM0_CONFIG_MEM_START_HPA,
|
||||
.size = VM0_CONFIG_MEM_SIZE,
|
||||
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
|
||||
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
|
||||
},
|
||||
.os_config = {
|
||||
.name = "YOCTO",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = VM0_BOOT_ARGS,
|
||||
},
|
||||
.acpi_config = {
|
||||
.acpi_mod_tag = "ACPI_VM0",
|
||||
},
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 1U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
|
||||
.memory =
|
||||
{
|
||||
.start_hpa = VM0_CONFIG_MEM_START_HPA,
|
||||
.size = VM0_CONFIG_MEM_SIZE,
|
||||
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
|
||||
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
|
||||
},
|
||||
.os_config =
|
||||
{
|
||||
.name = "YOCTO",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = VM0_BOOT_ARGS,
|
||||
},
|
||||
.acpi_config =
|
||||
{
|
||||
.acpi_mod_tag = "ACPI_VM0",
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 1U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
#ifdef VM0_PASSTHROUGH_TPM
|
||||
.pt_tpm2 = true,
|
||||
.mmiodevs[0] = {
|
||||
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
|
||||
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
|
||||
.size = VM0_TPM_BUFFER_SIZE,
|
||||
},
|
||||
.mmiodevs[0] =
|
||||
{
|
||||
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
|
||||
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
|
||||
.size = VM0_TPM_BUFFER_SIZE,
|
||||
},
|
||||
#endif
|
||||
#ifdef P2SB_BAR_ADDR
|
||||
.pt_p2sb_bar = true,
|
||||
.mmiodevs[0] = {
|
||||
.base_gpa = P2SB_BAR_ADDR_GPA,
|
||||
.base_hpa = P2SB_BAR_ADDR,
|
||||
.size = P2SB_BAR_SIZE,
|
||||
},
|
||||
.mmiodevs[0] =
|
||||
{
|
||||
.base_gpa = P2SB_BAR_ADDR_GPA,
|
||||
.base_hpa = P2SB_BAR_ADDR,
|
||||
.size = P2SB_BAR_SIZE,
|
||||
},
|
||||
#endif
|
||||
.pt_intx_num = VM0_PT_INTX_NUM,
|
||||
.pt_intx = &vm0_pt_intx[0U],
|
||||
},
|
||||
{ /* VM1 */
|
||||
{
|
||||
/* VM1 */
|
||||
CONFIG_PRE_STD_VM(2),
|
||||
.name = "ACRN PRE-LAUNCHED VM1",
|
||||
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
|
||||
.guest_flags = 0UL,
|
||||
#ifdef CONFIG_RDT_ENABLED
|
||||
.clos = VM1_VCPU_CLOS,
|
||||
#endif
|
||||
.memory = {
|
||||
.start_hpa = VM1_CONFIG_MEM_START_HPA,
|
||||
.size = VM1_CONFIG_MEM_SIZE,
|
||||
.start_hpa2 = VM1_CONFIG_MEM_START_HPA2,
|
||||
.size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2,
|
||||
},
|
||||
.os_config = {
|
||||
.name = "YOCTO",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = VM1_BOOT_ARGS,
|
||||
},
|
||||
.acpi_config = {
|
||||
.acpi_mod_tag = "ACPI_VM1",
|
||||
},
|
||||
.vuart[0] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] = {
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
|
||||
.memory =
|
||||
{
|
||||
.start_hpa = VM1_CONFIG_MEM_START_HPA,
|
||||
.size = VM1_CONFIG_MEM_SIZE,
|
||||
.start_hpa2 = VM1_CONFIG_MEM_START_HPA2,
|
||||
.size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2,
|
||||
},
|
||||
.os_config =
|
||||
{
|
||||
.name = "YOCTO",
|
||||
.kernel_type = KERNEL_BZIMAGE,
|
||||
.kernel_mod_tag = "Linux_bzImage",
|
||||
.bootargs = VM1_BOOT_ARGS,
|
||||
},
|
||||
.acpi_config =
|
||||
{
|
||||
.acpi_mod_tag = "ACPI_VM1",
|
||||
},
|
||||
.vuart[0] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM1_BASE,
|
||||
.irq = COM1_IRQ,
|
||||
},
|
||||
.vuart[1] =
|
||||
{
|
||||
.type = VUART_LEGACY_PIO,
|
||||
.addr.port_base = COM2_BASE,
|
||||
.irq = COM2_IRQ,
|
||||
.t_vuart.vm_id = 0U,
|
||||
.t_vuart.vuart_id = 1U,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
@@ -1,33 +1,28 @@
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
* Copyright (C) 2021 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VM_CONFIGURATIONS_H
|
||||
#define VM_CONFIGURATIONS_H
|
||||
|
||||
#include <misc_cfg.h>
|
||||
#include <pci_devices.h>
|
||||
|
||||
/* SOS_VM_NUM can only be 0U or 1U;
|
||||
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
|
||||
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
|
||||
*/
|
||||
#define PRE_VM_NUM 2U
|
||||
#define SOS_VM_NUM 0U
|
||||
#define MAX_POST_VM_NUM 0U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 0U
|
||||
|
||||
#define DM_OWNED_GUEST_FLAG_MASK 0UL
|
||||
|
||||
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
|
||||
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
|
||||
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
|
||||
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
|
||||
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
|
||||
#define VM1_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
|
||||
* bigger than CONFIG_MAX_KATA_VM_NUM. */
|
||||
#define PRE_VM_NUM 2U
|
||||
#define SOS_VM_NUM 0U
|
||||
#define MAX_POST_VM_NUM 0U
|
||||
#define CONFIG_MAX_KATA_VM_NUM 0U
|
||||
#define DM_OWNED_GUEST_FLAG_MASK 0UL
|
||||
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
|
||||
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
|
||||
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
|
||||
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
|
||||
#define VM1_CONFIG_MEM_START_HPA2 0x0UL
|
||||
#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL
|
||||
|
||||
#endif /* VM_CONFIGURATIONS_H */
|
||||
|
||||
@@ -96,7 +96,7 @@
|
||||
<kern_type>KERNEL_ZEPHYR</kern_type>
|
||||
<kern_mod>Zephyr_RawImage</kern_mod>
|
||||
<ramdisk_mod/>
|
||||
<bootargs>reboot=acpi</bootargs>
|
||||
<bootargs></bootargs>
|
||||
<kern_load_addr>0x8000</kern_load_addr>
|
||||
<kern_entry_addr>0x8000</kern_entry_addr>
|
||||
</os_config>
|
||||
|
||||
Reference in New Issue
Block a user