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config-tools: update the generic_code with xform output

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Replace folllowing python generated files with xslt transform outputs
which are formatted using clang-format:

misc/config_tools/data/generic_board/generic_code/
├── hybrid
│   ├── ivshmem_cfg.h
│   ├── misc_cfg.h
│   ├── pt_intx.c
│   ├── vm_configurations.c
│   └── vm_configurations.h
├── hybrid_rt
│   ├── ivshmem_cfg.h
│   ├── misc_cfg.h
│   ├── pt_intx.c
│   ├── vm_configurations.c
│   └── vm_configurations.h
├── industry
│   ├── ivshmem_cfg.h
│   ├── misc_cfg.h
│   ├── pt_intx.c
│   ├── vm_configurations.c
│   └── vm_configurations.h
└── logical_partition
    ├── ivshmem_cfg.h
    ├── misc_cfg.h
    ├── pt_intx.c
    ├── vm_configurations.c
    └── vm_configurations.h

Tracked-On: #5980
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
This commit is contained in:
Yang,Yu-chu
2021-04-14 16:16:40 -07:00
committed by wenlingz
parent 5f2f82f4d8
commit f3305b6373
29 changed files with 824 additions and 928 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h
View File

@@ -1,8 +1,9 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H

55
misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,51 +7,24 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/sda3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_ROOTFS "root=/dev/sda3"
#define SOS_CONSOLE "console=ttyS0"
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 5U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"swiotlb=131072 " \
"maxcpus=3"
#define SOS_BOOTARGS_DIFF \
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
"swiotlb=131072 maxcpus=3"
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define MBA_MASK_0 0U
#define CLOS_MASK_0 0xfffU
#define CLOS_MASK_1 0xfffU
#define CLOS_MASK_2 0xfffU
@@ -68,16 +41,14 @@
#define CLOS_MASK_13 0xfffU
#define CLOS_MASK_14 0xfffU
#define CLOS_MASK_15 0xfffU
#define VM0_VCPU_CLOS {0U}
#define VM1_VCPU_CLOS {0U, 0U, 0U}
#define VM2_VCPU_CLOS {0U}
#define VM0_VCPU_CLOS \
{ 0U }
#define VM1_VCPU_CLOS \
{ 0U, 0U, 0U }
#define VM2_VCPU_CLOS \
{ 0U }
#endif
#define VM0_BOOT_ARGS "reboot=acpi"
#define VM0_PT_INTX_NUM 0U
#endif /* MISC_CFG_H */

6
misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c
View File

@@ -4,11 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>
#include <x86/mmu.h>
#include <x86/page.h>
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];

6
misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c
View File

@@ -1,10 +1,8 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U];

19
misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h
View File

@@ -7,8 +7,7 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
.vbar_base[2] = HI_MMIO_START + 0x0UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
@@ -34,8 +33,7 @@
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
.vbar_base[1] = 0x80000000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
@@ -51,12 +49,9 @@
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
.vbar_base[2] = 0x834e7000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
.vbar_base[1] = 0x834f6000UL, \
.vbar_base[5] = 0x834f5000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
@@ -68,11 +63,9 @@
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
.vbar_base[2] = 0x834f2000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
.vbar_base[4] = 0x83200000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL

64
misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c
View File

@@ -1,48 +1,51 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
#include <x86/pci_dev.h>
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
extern struct pt_intx_config vm0_pt_intx[1U];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
{
/* VM0 */
CONFIG_SAFETY_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.memory = {
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.memory =
{
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.os_config =
{
.name = "Zephyr",
.kernel_type = KERNEL_ZEPHYR,
.kernel_mod_tag = "Zephyr_RawImage",
.kernel_load_addr = 0x8000,
.kernel_entry_addr = 0x8000,
.bootargs = VM0_BOOT_ARGS,
},
.acpi_config = {
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
@@ -51,7 +54,8 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
},
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.mmiodevs[0] =
{
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
@@ -59,7 +63,8 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
#endif
#ifdef P2SB_BAR_ADDR
.pt_p2sb_bar = true,
.mmiodevs[0] = {
.mmiodevs[0] =
{
.base_gpa = P2SB_BAR_ADDR_GPA,
.base_hpa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
@@ -68,31 +73,35 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pt_intx_num = VM0_PT_INTX_NUM,
.pt_intx = &vm0_pt_intx[0U],
},
{ /* VM1 */
{
/* VM1 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
/* Allow Service VM to reboot the system since it is the highest priority VM. */
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
.memory = {
.memory =
{
.start_hpa = 0UL,
},
.os_config = {
.os_config =
{
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM1_BASE,
.irq = SOS_COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM2_BASE,
.irq = SOS_COM2_IRQ,
@@ -102,18 +111,21 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pci_dev_num = 0U,
.pci_devs = sos_pci_devs,
},
{ /* VM2 */
{
/* VM2 */
CONFIG_POST_STD_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM2_VCPU_CLOS,
#endif
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},

25
misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h
View File

@@ -1,36 +1,29 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
* bigger than CONFIG_MAX_KATA_VM_NUM. */
#define PRE_VM_NUM 1U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 1U
#define CONFIG_MAX_KATA_VM_NUM 0U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
#define DM_OWNED_GUEST_FLAG_MASK \
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
GUEST_FLAG_IO_COMPLETION_POLLING)
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
/* SOS_VM == VM1 */
#define SOS_VM_BOOTARGS SOS_ROOTFS \
SOS_CONSOLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF
#endif /* VM_CONFIGURATIONS_H */

15
misc/config_tools/data/generic_board/generic_code/hybrid_rt/ivshmem_cfg.h
View File

@@ -1,28 +1,25 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H
#include <ivshmem.h>
#include <pgtable.h>
#include <x86/pgtable.h>
#define IVSHMEM_SHM_REGION_0 "hv:/shm_region_0"
/*
* The IVSHMEM_SHM_SIZE is the sum of all memory regions.
* The size range of each memory region is [2MB, 512MB] and is a power of 2.
*/
/* The IVSHMEM_SHM_SIZE is the sum of all memory regions. The size range of each memory region is [2MB, 512MB] and is a
* power of 2. */
#define IVSHMEM_SHM_SIZE 0x200000UL
#define IVSHMEM_DEV_NUM 2UL
/* All user defined memory regions */
#define IVSHMEM_SHM_REGIONS \
{ \
.name = IVSHMEM_SHM_REGION_0, \
.size = 0x200000UL, /* 2M */ \
.size = 0x200000UL, \
},
#endif /* IVSHMEM_CFG_H */

69
misc/config_tools/data/generic_board/generic_code/hybrid_rt/misc_cfg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,52 +7,25 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_ROOTFS "root=/dev/nvme0n1p3"
#define SOS_CONSOLE "console=ttyS0"
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 5U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"swiotlb=131072 " \
"maxcpus=2"
#define SOS_BOOTARGS_DIFF \
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
"swiotlb=131072 maxcpus=2"
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define MBA_MASK_0 0U
#define CLOS_MASK_0 0xfffU
#define CLOS_MASK_1 0xfffU
#define CLOS_MASK_2 0xfffU
@@ -69,25 +42,23 @@
#define CLOS_MASK_13 0xfffU
#define CLOS_MASK_14 0xfffU
#define CLOS_MASK_15 0xfffU
#define VM0_VCPU_CLOS {0U, 0U}
#define VM1_VCPU_CLOS {0U, 0U}
#define VM2_VCPU_CLOS {0U, 0U}
#define VM3_VCPU_CLOS {0U}
#define VM0_VCPU_CLOS \
{ 0U, 0U }
#define VM1_VCPU_CLOS \
{ 0U, 0U }
#define VM2_VCPU_CLOS \
{ 0U, 0U }
#define VM3_VCPU_CLOS \
{ 0U }
#endif
#define VM0_CONFIG_PCI_DEV_NUM 4U
#define VM2_CONFIG_PCI_DEV_NUM 1U
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 no_ipi_broadcast=1 \
console=ttyS0 noxsave nohpet no_timer_check \
ignore_loglevel consoleblank=0 tsc=reliable clocksource=tsc \
x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 intel_pstate=disable \
mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 \
rcu_nocbs=1 nosoftlockup idle=poll irqaffinity=0 \
reboot=acpi"
#define VM0_BOOT_ARGS \
"rw rootwait root=/dev/sda3 no_ipi_broadcast=1 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel " \
"consoleblank=0 tsc=reliable clocksource=tsc x2apic_phys processor.max_cstate=0 intel_idle.max_cstate=0 " \
"intel_pstate=disable mce=ignore_ce audit=0 isolcpus=nohz,domain,1 nohz_full=1 rcu_nocbs=1 nosoftlockup " \
"idle=poll irqaffinity=0 reboot=acpi"
#define VM0_PT_INTX_NUM 0U
#endif /* MISC_CFG_H */

10
misc/config_tools/data/generic_board/generic_code/hybrid_rt/pci_dev.c
View File

@@ -4,12 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>
#include <x86/mmu.h>
#include <x86/page.h>
#include <ivshmem_cfg.h>
/*
@@ -44,7 +44,7 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
.vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U},
.vdev_ops = &vpci_ivshmem_ops,
.shm_region_name = IVSHMEM_SHM_REGION_0,
IVSHMEM_DEVICE_0_VBAR
IVSHMEM_DEVICE_0_VBAR,
},
};
@@ -55,6 +55,6 @@ struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = {
.emu_type = PCI_DEV_TYPE_HVEMUL,
.vbdf.value = UNASSIGNED_VBDF,
.vdev_ops = &vpci_ivshmem_ops,
.shm_region_name = IVSHMEM_SHM_REGION_0
.shm_region_name = IVSHMEM_SHM_REGION_0,
},
};

6
misc/config_tools/data/generic_board/generic_code/hybrid_rt/pt_intx.c
View File

@@ -1,10 +1,8 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U];

26
misc/config_tools/data/generic_board/generic_code/hybrid_rt/vbar_base.h
View File

@@ -7,12 +7,9 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, \
.vbar_base[1] = 0x80001000UL, \
.vbar_base[2] = 0x8020000cUL
#define IVSHMEM_DEVICE_0_VBAR .vbar_base[0] = 0x80000000UL, .vbar_base[1] = 0x80001000UL, .vbar_base[2] = 0x8020000cUL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
.vbar_base[2] = HI_MMIO_START + 0x0UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
@@ -38,8 +35,7 @@
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
.vbar_base[1] = 0x80000000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
@@ -55,12 +51,9 @@
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
.vbar_base[2] = 0x834e7000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
.vbar_base[1] = 0x834f6000UL, \
.vbar_base[5] = 0x834f5000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
@@ -70,14 +63,11 @@
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = 0x83500000UL
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL, \
.vbar_base[2] = 0x80002000UL
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
.vbar_base[2] = 0x834f2000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
.vbar_base[4] = 0x83200000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL

77
misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.c
View File

@@ -1,48 +1,52 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
#include <x86/vm_config.h>
#include <vuart.h>
#include <x86/pci_dev.h>
extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
extern struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM];
extern struct pt_intx_config vm0_pt_intx[1U];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
{
/* VM0 */
CONFIG_PRE_RT_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = (GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT),
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.memory = {
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.memory =
{
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.os_config =
{
.name = "PREEMPT-RT",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "RT_bzImage",
.bootargs = VM0_BOOT_ARGS,
},
.acpi_config = {
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
@@ -53,7 +57,8 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pci_devs = vm0_pci_devs,
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.mmiodevs[0] =
{
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
@@ -61,7 +66,8 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
#endif
#ifdef P2SB_BAR_ADDR
.pt_p2sb_bar = true,
.mmiodevs[0] = {
.mmiodevs[0] =
{
.base_gpa = P2SB_BAR_ADDR_GPA,
.base_hpa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
@@ -70,31 +76,35 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pt_intx_num = VM0_PT_INTX_NUM,
.pt_intx = &vm0_pt_intx[0U],
},
{ /* VM1 */
{
/* VM1 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
/* Allow Service VM to reboot the system since it is the highest priority VM. */
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
.memory = {
.memory =
{
.start_hpa = 0UL,
},
.os_config = {
.os_config =
{
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM1_BASE,
.irq = SOS_COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM2_BASE,
.irq = SOS_COM2_IRQ,
@@ -104,37 +114,42 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pci_dev_num = 0U,
.pci_devs = sos_pci_devs,
},
{ /* VM2 */
{
/* VM2 */
CONFIG_POST_STD_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM2_VCPU_CLOS,
#endif
/* The PCI device configuration is only for in-hypervisor vPCI devices. */
.pci_dev_num = VM2_CONFIG_PCI_DEV_NUM,
.pci_devs = vm2_pci_devs,
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.pci_dev_num = VM2_CONFIG_PCI_DEV_NUM,
.pci_devs = vm2_pci_devs,
},
{ /* VM3 */
{
/* VM3 */
CONFIG_POST_STD_VM(2),
#ifdef CONFIG_RDT_ENABLED
.clos = VM3_VCPU_CLOS,
#endif
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},

25
misc/config_tools/data/generic_board/generic_code/hybrid_rt/vm_configurations.h
View File

@@ -1,36 +1,29 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
* bigger than CONFIG_MAX_KATA_VM_NUM. */
#define PRE_VM_NUM 1U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 2U
#define CONFIG_MAX_KATA_VM_NUM 0U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
#define DM_OWNED_GUEST_FLAG_MASK \
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
GUEST_FLAG_IO_COMPLETION_POLLING)
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x40000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
/* SOS_VM == VM1 */
#define SOS_VM_BOOTARGS SOS_ROOTFS \
SOS_CONSOLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF
#endif /* VM_CONFIGURATIONS_H */

3
misc/config_tools/data/generic_board/generic_code/industry/ivshmem_cfg.h
View File

@@ -1,8 +1,9 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H

72
misc/config_tools/data/generic_board/generic_code/industry/misc_cfg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,25 +7,16 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS3 "
#define SOS_COM1_BASE 0x2E8U
#define SOS_ROOTFS "root=/dev/nvme0n1p3"
#define SOS_CONSOLE "console=ttyS3"
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 3U
#define SOS_COM2_BASE 0x3F8U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 4U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"swiotlb=131072 " \
"maxcpus=4"
#define SOS_BOOTARGS_DIFF \
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
"swiotlb=131072 maxcpus=4"
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
@@ -34,29 +25,11 @@
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 16U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 16U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 16U
#define MBA_MASK_0 0U
#define CLOS_MASK_0 0xfffU
#define CLOS_MASK_1 0xfffU
#define CLOS_MASK_2 0xfffU
@@ -73,19 +46,24 @@
#define CLOS_MASK_13 0xfffU
#define CLOS_MASK_14 0xfffU
#define CLOS_MASK_15 0xfffU
#define VM0_VCPU_CLOS {0U}
#define VM1_VCPU_CLOS {0U, 0U}
#define VM2_VCPU_CLOS {0U, 0U}
#define VM3_VCPU_CLOS {0U, 0U}
#define VM4_VCPU_CLOS {0U, 0U}
#define VM5_VCPU_CLOS {0U, 0U}
#define VM6_VCPU_CLOS {0U, 0U}
#define VM7_VCPU_CLOS {0U, 0U}
#define VM0_VCPU_CLOS \
{ 0U }
#define VM1_VCPU_CLOS \
{ 0U, 0U }
#define VM2_VCPU_CLOS \
{ 0U, 0U }
#define VM3_VCPU_CLOS \
{ 0U, 0U }
#define VM4_VCPU_CLOS \
{ 0U, 0U }
#define VM5_VCPU_CLOS \
{ 0U, 0U }
#define VM6_VCPU_CLOS \
{ 0U, 0U }
#define VM7_VCPU_CLOS \
{ 0U, 0U }
#endif
#define VM0_PT_INTX_NUM 0U
#endif /* MISC_CFG_H */

6
misc/config_tools/data/generic_board/generic_code/industry/pci_dev.c
View File

@@ -4,11 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>
#include <x86/mmu.h>
#include <x86/page.h>
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];

6
misc/config_tools/data/generic_board/generic_code/industry/pt_intx.c
View File

@@ -1,10 +1,8 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U];

19
misc/config_tools/data/generic_board/generic_code/industry/vbar_base.h
View File

@@ -7,8 +7,7 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
.vbar_base[2] = HI_MMIO_START + 0x0UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
@@ -34,8 +33,7 @@
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
.vbar_base[1] = 0x80000000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
@@ -51,12 +49,9 @@
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
.vbar_base[2] = 0x834e7000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
.vbar_base[1] = 0x834f6000UL, \
.vbar_base[5] = 0x834f5000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
@@ -68,11 +63,9 @@
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
.vbar_base[2] = 0x834f2000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
.vbar_base[4] = 0x83200000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL

92
misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.c
View File

@@ -1,42 +1,44 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
#include <x86/pci_dev.h>
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
extern struct pt_intx_config vm0_pt_intx[1U];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
{
/* VM0 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
/* Allow Service VM to reboot the system since it is the highest priority VM. */
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
.memory = {
.memory =
{
.start_hpa = 0UL,
},
.os_config = {
.os_config =
{
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM1_BASE,
.irq = SOS_COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM2_BASE,
.irq = SOS_COM2_IRQ,
@@ -46,34 +48,40 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pci_dev_num = 0U,
.pci_devs = sos_pci_devs,
},
{ /* VM1 */
{
/* VM1 */
CONFIG_POST_STD_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
{ /* VM2 */
{
/* VM2 */
CONFIG_POST_RT_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM2_VCPU_CLOS,
#endif
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
@@ -81,82 +89,96 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.t_vuart.vuart_id = 1U,
},
},
{ /* VM3 */
{
/* VM3 */
CONFIG_POST_STD_VM(2),
#ifdef CONFIG_RDT_ENABLED
.clos = VM3_VCPU_CLOS,
#endif
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
{ /* VM4 */
{
/* VM4 */
CONFIG_POST_STD_VM(3),
#ifdef CONFIG_RDT_ENABLED
.clos = VM4_VCPU_CLOS,
#endif
.cpu_affinity = VM4_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
{ /* VM5 */
{
/* VM5 */
CONFIG_POST_STD_VM(4),
#ifdef CONFIG_RDT_ENABLED
.clos = VM5_VCPU_CLOS,
#endif
.cpu_affinity = VM5_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
{ /* VM6 */
{
/* VM6 */
CONFIG_POST_STD_VM(5),
#ifdef CONFIG_RDT_ENABLED
.clos = VM6_VCPU_CLOS,
#endif
.cpu_affinity = VM6_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
},
{ /* VM7 */
{
/* VM7 */
CONFIG_KATA_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM7_VCPU_CLOS,
#endif
.cpu_affinity = VM7_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},

24
misc/config_tools/data/generic_board/generic_code/industry/vm_configurations.h
View File

@@ -1,31 +1,25 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
* bigger than CONFIG_MAX_KATA_VM_NUM. */
#define PRE_VM_NUM 0U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 7U
#define CONFIG_MAX_KATA_VM_NUM 1U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
#define DM_OWNED_GUEST_FLAG_MASK \
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
GUEST_FLAG_IO_COMPLETION_POLLING)
/* SOS_VM == VM0 */
#define SOS_VM_BOOTARGS SOS_ROOTFS \
SOS_CONSOLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
#define SOS_VM_BOOTARGS SOS_ROOTFS SOS_CONSOLE SOS_IDLE SOS_BOOTARGS_DIFF
#endif /* VM_CONFIGURATIONS_H */

3
misc/config_tools/data/generic_board/generic_code/logical_partition/ivshmem_cfg.h
View File

@@ -1,8 +1,9 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H

45
misc/config_tools/data/generic_board/generic_code/logical_partition/misc_cfg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,29 +9,11 @@
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define MBA_MASK_0 0U
#define CLOS_MASK_0 0xfffU
#define CLOS_MASK_1 0xfffU
#define CLOS_MASK_2 0xfffU
@@ -48,21 +30,18 @@
#define CLOS_MASK_13 0xfffU
#define CLOS_MASK_14 0xfffU
#define CLOS_MASK_15 0xfffU
#define VM0_VCPU_CLOS {0U, 0U}
#define VM1_VCPU_CLOS {0U, 0U}
#define VM0_VCPU_CLOS \
{ 0U, 0U }
#define VM1_VCPU_CLOS \
{ 0U, 0U }
#endif
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi"
#define VM1_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi"
#define VM0_BOOT_ARGS \
"rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \
"consoleblank=0 tsc=reliable reboot=acpi"
#define VM1_BOOT_ARGS \
"rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \
"consoleblank=0 tsc=reliable reboot=acpi"
#define VM0_PT_INTX_NUM 0U
#endif /* MISC_CFG_H */

6
misc/config_tools/data/generic_board/generic_code/logical_partition/pci_dev.c
View File

@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <mmu.h>
#include <page.h>
#include <x86/mmu.h>
#include <x86/page.h>

6
misc/config_tools/data/generic_board/generic_code/logical_partition/pt_intx.c
View File

@@ -1,10 +1,8 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U];

19
misc/config_tools/data/generic_board/generic_code/logical_partition/vbar_base.h
View File

@@ -7,8 +7,7 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, \
.vbar_base[2] = HI_MMIO_START + 0x0UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = 0x82000000UL, .vbar_base[2] = HI_MMIO_START + 0x0UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = 0x834e4000UL
@@ -34,8 +33,7 @@
#define SERIAL_BUS_CONTROLLER_9_VBAR .vbar_base[0] = 0x834de000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, \
.vbar_base[1] = 0x80000000UL
#define SERIAL_BUS_CONTROLLER_10_VBAR .vbar_base[0] = 0x8344c000UL, .vbar_base[1] = 0x80000000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = 0x84600000UL
@@ -51,12 +49,9 @@
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = 0x834c0000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, \
.vbar_base[2] = 0x834e7000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = 0x834d0000UL, .vbar_base[2] = 0x834e7000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, \
.vbar_base[1] = 0x834f6000UL, \
.vbar_base[5] = 0x834f5000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = 0x834e2000UL, .vbar_base[1] = 0x834f6000UL, .vbar_base[5] = 0x834f5000UL
#define SD_HOST_CONTROLLER_0_VBAR .vbar_base[0] = 0x834ee000UL
@@ -68,11 +63,9 @@
#define ETHERNET_CONTROLLER_1_VBAR .vbar_base[0] = 0x83480000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, \
.vbar_base[2] = 0x834f2000UL
#define ETHERNET_CONTROLLER_2_VBAR .vbar_base[0] = 0x83442000UL, .vbar_base[2] = 0x834f2000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, \
.vbar_base[4] = 0x83200000UL
#define MULTIMEDIA_AUDIO_CONTROLLER_0_VBAR .vbar_base[0] = 0x834d4000UL, .vbar_base[4] = 0x83200000UL
#define SMBUS_0_VBAR .vbar_base[0] = 0x834f3000UL

56
misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.c
View File

@@ -1,45 +1,49 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <vm_config.h>
#include <x86/vm_config.h>
#include <vuart.h>
#include <pci_dev.h>
#include <x86/pci_dev.h>
extern struct pt_intx_config vm0_pt_intx[1U];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
{
/* VM0 */
CONFIG_PRE_STD_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.memory = {
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.memory =
{
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.os_config =
{
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = VM0_BOOT_ARGS,
},
.acpi_config = {
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
@@ -48,7 +52,8 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
},
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.mmiodevs[0] =
{
.base_gpa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.base_hpa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
@@ -56,7 +61,8 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
#endif
#ifdef P2SB_BAR_ADDR
.pt_p2sb_bar = true,
.mmiodevs[0] = {
.mmiodevs[0] =
{
.base_gpa = P2SB_BAR_ADDR_GPA,
.base_hpa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
@@ -65,35 +71,41 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
.pt_intx_num = VM0_PT_INTX_NUM,
.pt_intx = &vm0_pt_intx[0U],
},
{ /* VM1 */
{
/* VM1 */
CONFIG_PRE_STD_VM(2),
.name = "ACRN PRE-LAUNCHED VM1",
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
.memory = {
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
.memory =
{
.start_hpa = VM1_CONFIG_MEM_START_HPA,
.size = VM1_CONFIG_MEM_SIZE,
.start_hpa2 = VM1_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.os_config =
{
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = VM1_BOOT_ARGS,
},
.acpi_config = {
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM1",
},
.vuart[0] = {
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,

13
misc/config_tools/data/generic_board/generic_code/logical_partition/vm_configurations.h
View File

@@ -1,30 +1,25 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
/* SOS_VM_NUM can only be 0U or 1U; When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too; MAX_POST_VM_NUM must be
* bigger than CONFIG_MAX_KATA_VM_NUM. */
#define PRE_VM_NUM 2U
#define SOS_VM_NUM 0U
#define MAX_POST_VM_NUM 0U
#define CONFIG_MAX_KATA_VM_NUM 0U
#define DM_OWNED_GUEST_FLAG_MASK 0UL
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
#define VM1_CONFIG_MEM_START_HPA2 0x0UL

2
misc/config_tools/data/generic_board/hybrid.xml
View File

@@ -96,7 +96,7 @@
<kern_type>KERNEL_ZEPHYR</kern_type>
<kern_mod>Zephyr_RawImage</kern_mod>
<ramdisk_mod/>
<bootargs>reboot=acpi</bootargs>
<bootargs></bootargs>
<kern_load_addr>0x8000</kern_load_addr>
<kern_entry_addr>0x8000</kern_entry_addr>
</os_config>