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HV: mmu: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
2018-06-19 18:30:40 +08:00
committed by lijinxia
parent 7b548e87db
commit f4bd0798e0
3 changed files with 105 additions and 105 deletions
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18
hypervisor/arch/x86/gdt.c
View File

@@ -11,14 +11,14 @@ static void set_tss_desc(union tss_64_descriptor *desc,
{
uint32_t u1, u2, u3;
u1 = ((uint64_t)tss << 16) & 0xFFFFFFFF;
u2 = (uint64_t)tss & 0xFF000000;
u3 = ((uint64_t)tss & 0x00FF0000) >> 16;
u1 = (uint32_t)(((uint64_t)tss << 16U) & 0xFFFFFFFFU);
u2 = (uint32_t)((uint64_t)tss & 0xFF000000U);
u3 = (uint32_t)(((uint64_t)tss & 0x00FF0000U) >> 16U);
desc->fields.low32.value = u1 | (tss_limit & 0xFFFF);
desc->fields.base_addr_63_32 = (uint32_t)((uint64_t)tss >> 32);
desc->fields.high32.value = (u2 | ((uint32_t)type << 8) | 0x8000 | u3);
desc->fields.low32.value = u1 | (tss_limit & 0xFFFFU);
desc->fields.base_addr_63_32 = (uint32_t)((uint64_t)tss >> 32U);
desc->fields.high32.value = (u2 | ((uint32_t)type << 8U) | 0x8000U | u3);
}
void load_gdtr_and_tr(void)
@@ -28,11 +28,11 @@ void load_gdtr_and_tr(void)
struct tss_64 *tss = &get_cpu_var(tss);
/* first entry is not used */
gdt->rsvd = 0xAAAAAAAAAAAAAAAA;
gdt->rsvd = 0xAAAAAAAAAAAAAAAAUL;
/* ring 0 code sel descriptor */
gdt->host_gdt_code_descriptor.value = 0x00Af9b000000ffff;
gdt->host_gdt_code_descriptor.value = 0x00Af9b000000ffffUL;
/* ring 0 data sel descriptor */
gdt->host_gdt_data_descriptor.value = 0x00cf93000000ffff;
gdt->host_gdt_data_descriptor.value = 0x00cf93000000ffffUL;
tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE;
tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE;

18
hypervisor/arch/x86/mmu.c
View File

@@ -178,12 +178,12 @@ void invept(struct vcpu *vcpu)
struct invept_desc desc = {0};
if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_SINGLE_CONTEXT)) {
desc.eptp = vcpu->vm->arch_vm.nworld_eptp | (3 << 3) | 6;
desc.eptp = vcpu->vm->arch_vm.nworld_eptp | (3UL << 3U) | 6UL;
_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
if (vcpu->vm->sworld_control.sworld_enabled &&
vcpu->vm->arch_vm.sworld_eptp) {
desc.eptp = vcpu->vm->arch_vm.sworld_eptp
| (3 << 3) | 6;
| (3UL << 3U) | 6UL;
_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
}
} else if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_GLOBAL_CONTEXT))
@@ -990,10 +990,10 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
/* Keep original attribute(here &0x3f)
* bit 0(R) bit1(W) bit2(X) bit3~5 MT
*/
attr |= (entry.entry_val & 0x3f);
attr |= (entry.entry_val & 0x3fUL);
} else {
/* Keep original attribute(here &0x7f) */
attr |= (entry.entry_val & 0x7f);
attr |= (entry.entry_val & 0x7fUL);
}
/* write all entries and keep original attr*/
for (i = 0; i < IA32E_NUM_ENTRIES; i++) {
@@ -1007,7 +1007,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
* (here &0x07)
*/
MEM_WRITE64(entry.entry_base + entry.entry_off,
(entry.entry_val & 0x07) |
(entry.entry_val & 0x07UL) |
HVA2HPA(sub_tab_addr));
} else {
/* Write the table entry to map this memory,
@@ -1016,7 +1016,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
* bit5(A) bit6(D or Ignore)
*/
MEM_WRITE64(entry.entry_base + entry.entry_off,
(entry.entry_val & 0x7f) |
(entry.entry_val & 0x7fUL) |
HVA2HPA(sub_tab_addr));
}
}
@@ -1060,9 +1060,9 @@ static int modify_paging(struct map_params *map_params, void *paddr,
* here attr & 0x7, rwx bit0:2
*/
ASSERT(!((map_params->page_table_type == PTT_EPT) &&
(((attr & 0x7) == IA32E_EPT_W_BIT) ||
((attr & 0x7) == (IA32E_EPT_W_BIT | IA32E_EPT_X_BIT)) ||
(((attr & 0x7) == IA32E_EPT_X_BIT) &&
(((attr & 0x7UL) == IA32E_EPT_W_BIT) ||
((attr & 0x7UL) == (IA32E_EPT_W_BIT | IA32E_EPT_X_BIT)) ||
(((attr & 0x7UL) == IA32E_EPT_X_BIT) &&
!cpu_has_vmx_ept_cap(VMX_EPT_EXECUTE_ONLY)))),
"incorrect memory attribute set!\n");
/* Loop until the entire block of memory is appropriately