qemu xml has no devices list. Tool will receive the empty devices
list while parsing the "platform" xml. Remove the error of resolved
nested mmio address window that the input couldn't be None. Simply
return an None list.
Tracked-On:#5454
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Allocate unused vbar for pci based vuarts when the it's enabled for SOS
and/or pre-launched VMs.
- vuart needs 2 bar, both are 4k size
- for SOS, find unused vbar in the range which is assigned to pci host
bridge. The allocated vbar cannot have confilicts with any existing pci devices
- for pre-launched VMs, find unused vbar in the range 0x80000000 to
0xfffffff. The alloacted vbar cannot have confilicts with any
passthrough devices and mmio
Tracked-On: #5425
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Multiple devices could be nested under the same range. Skip remove if
the device is removed already
Tracked-On: #5437
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Support enable ivshmem for SOS. Insert the ivshmem device information if
it is enabled.
1. get ivshmem vbar based:
- vbar[0] is size 0x100
- vbar[2] is specified MB size
2. get vbdf for ivshmem device
Tracked-On: #5426
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
Allocate unused vbar for SOS and pre-launched VMs.
- For SOS, find unused vbar in the range which is assigned to pci host
bridge. The allocated vbar cannot have confilicts with any existing pci devices
- For pre-launched VMs, find unused vbar in the range 0x80000000 to
0xfffffff. The alloacted vbar cannot have confilicts with any
passthrough devices and mmio.
Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Add functionality to get free vbar base for the vmsix devices.
- The devices size is 4k.
- The mmio range for non SOS VM is 2G to 4G
- The mmio range for SOS is depended on the range which is assigned to
PCI bus hostbridge
- The next vbar index is based on last device vbar index vbar_i
Tracked-On: #5422
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
P2SB_BAR_ADDR related macros should only be defined in misc_cfg.h only when
p2sb is enabled in scenario xml.
Tracked-On: #5340
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
The MACRO of IVSHMEM shared region name is relevant to scenario, move
the MACRO from pci_devices.h which should be consistent for different
scenarios to ivshmem_cfg.h which is the configuration for IVSHMEM and
could vary in sceanrios.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Move the function which are used to get available ttysn
from board catalogue to library catalogue
Tracked-On: #5154
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Comments will be added for the HV_SUPPORTED_MAX_CLOS/MAX_MBA_CLOS_NUM_ENTRIES/MAX_CACHE_CLOS_NUM_ENTRIES
macros in generated code
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Move struct pt_intx_config vm0_pt_intx[] defintion to pt_intx.c
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
The boilerplate code is protected by #ifdef P2SB_BAR_ADDR/#endif, so it will
not hurt if we always produce related code.
Define new macros P2SB_BAR_ADDR_GPA and P2SB_BAR_SIZE to make the code more flexible.
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
The boilerplate code is protected by #ifdef VM0_PASSTHROUGH_TPM/#endif, so it will
not hurt if we always produce related code.
Define a new macro VM0_TPM_BUFFER_BASE_ADDR_GPA to define the allocated gpa for VM0_TPM_BUFFER_BASE_ADDR
to make the code more flexible.
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Debugged and refactored the split_cmdline() function
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
For python versions prior to 3.7, dict order is not guaranteed.
Use ordered dict to ensure consistent ordering for the same input,
otherwise, the generated config files may change every time the config tool runs
Fix some error messages in code/comment
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
add 2 MACROs: DEFAULT_PCI_MMCFG_START_BUS and DEFAULT_PCI_MMCFG_END_BUS
in platform_acpi_info.h.
Tracked-On: #5233
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Always use P2SB_ as a prefix for all macro definitions related to P2SB
MMIO passthru. And introduce the new P2SB_VGPIO_DM_ENABLED macro to
indicate the presence of the pre-launched VM which requires the feature.
This macro intends to be used to enclose source files with ifdef where
macros defined by config-tool being used which are available only when
the feature is enabled. It is required to avoid causing compilation
errors when users build HV without enabling the feature.
Tracked-On: #5246
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Two PSE-GPIO controllers of EHL CRB require MSI-X emulation for
pass-thru because it uses multiple MSI vectors. Currently acrn-config
enables MSI-X emulation for only TSN devices. Enable MSI-X emulation
for PSE-GPIOs, too.
Tracked-On: #5242
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch is to expose GPIO chassis interrupts as INTx to safety VM for
EHL. User can configure this per-VM attribute in scenario xml using the
following format:
<pt_intx desc="pt intx mapping.">
(phys_gsi0, virt_gsi0), (phys_gsi1, virt_gsi1), (phys_gsiN, virt_gsiN)
</pt_intx>
The physical and virtual interrupt gsi in each pair are separated by a
comma and enclosed in parentheses. If an integer begins with 0x or 0X,
it is hexadecimal, otherwise, it is assumed to be decimal. Example:
<pt_intx desc="pt intx mapping.">
(1, 0), (0x3, 1), (0x4, 2), (5, 6), (89, 0x12)
</pt_intx>
Tracked-On: #5241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This patch is to support direct assignment of P2SB bridge to one pre-launched
VM for EHL. User can configure this per-VM attribute in scenario xml:
<mmio_resources desc="MMIO resources.">
<p2sb>y</p2sb>
</mmio_resources>
Set p2sb to y to passthru P2SB bridge to VM, and n otherwise.
Tracked-On: #5221
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.
MAX_MBA_CLOS_NUM_ENTRIES:
Max number of Cache Mask entries corresponding to each CLOS.
This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
cache mask values for Data and Code when CDP is enabled.
MAX_CACHE_CLOS_NUM_ENTRIES:
Max number of MBA delay entries corresponding to each CLOS.
2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.
Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
HV_SUPPORTED_MAX_CLOS:
This value represents the maximum CLOS that is allowed by ACRN hypervisor.
This value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
among all supported RDT resources in the platform. In other words, it is
min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
CLOS allocations between all the RDT resources.
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
We use sos kernel cmdline maxcpus to limit the pCPU number of SOS
for hybrid or hybrid_rt scenarios by vcpu numbers calculation.
v2: add SOS CPU affinity calculation by total pCPU plus pCPUs
occupied by pre-launched VMs when no pcpuid configured
in SOS.
Tracked-On: #5216
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
This patch is to support the Inter-VM communication by IVSHMEM
in config tool.
Users can configure IVSHMEM_ENABLE to enable or disable Inter-VM
communication by IVSHMEM; users can configure the name, size,
communication VM IDs of the IVSHMEM devices in the VM settings of
scenario xmls, then config tool will generate the related IVSHMEM
configurations for Inter-VM communication.
The config tool will do sanity check including when saving the xmls:
the format of shared memory region configuration is
[name],[size],[VM ID]:[VM ID](:[VM ID]...);
the max size of the name is 32 bytes;
the names should not be duplicated;
the mininum value of shared memory region size is 2M;
the value of shared memory region is a power of 2;
the size of share memory region should not extended the size of
available ram.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Fix build issue while CDP_ENABLED=y for EHL-CRB-B.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add support to generate passthru TPM information for whl-ipc-i5/i7.
Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There is some macro defined in misc_cfg.h while CAT/MBA enabled.
include the missing header to solve build issue.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Now the hypervisor configuration source code layout is changed, so acrn-config
need to change accordingly to make sure XML based configuration build success;
Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Refine sanity check for RDT CLOS and MBA Delay.
Tracked-On: #4943
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
This patch adds support to configure MBA delay values from
scenario xml files just as it is done for CAT mask. This will
improve user experience when configuring RDT resource mask
values.
Tracked-On: #4943
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
generate msix emulation information from known exist PCI devices for
board config.
Tracked-On: #4831
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently, MMIO PCI BDF of ttyS was indexed by IRQ, but it may found
the wrong BDF when the IRQ was shared and it is not expected. So, the
patch uses the MMIO base to query /proc/iomem to find BDF, the waring
will get if BDF is not present in iomem.
Tracked-On: #4862
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.Add parser and sanity check for RDT_ENABLED/CDP_ENABLED/CLOS_MASK.
2.Skip to generate RDT inforamtion when HW not support RDT or usr
select 'n' to disable RDT feature.
3.Add contiguous bit 1 check for CLOS_MASK.
Tracked-On: #4860
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch sets defaults similar to generic platform configuration
when leaf features like PM_INFO, S3_INFO, S5_INFO, DRHD_INFO, CPU_BRAND,
CX_INFO, PX_INFO, MMCFG_BASE_INFO are not generated via either target
offline tool or user supplies empty field in case of emulation.
Tracked-On: #3198
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
As VUART is not supported PCI VUART, use native PCI ttySn's IRQ for
VUART1 would cause communication failed, allocate a free IRQ for it.
Tracked-On: #4798
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add max VM count check when generating scenario XML file.
Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Currently, '--out' is relative scripts run dir if it gets relative path,
Refine '--out' to source root tree if it gets relative path.
Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Pre-Launched VMs need the vbar_base values pre-populated
for pass-thru PCI devices.
This patch moves the pci parser logic from board_cfg_gen to library
so that scenario_cfg_gen scripts can use pci parser routines while
generating pci_dev file logical partition scenario.
Tracked-On: #4666
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
To keep align hv source code changes, config tool doese below changes:
1. Remove UUID from scenario config files.
2. Remove severity from scenario config files.
3. Use vm type to instead load order type.
4. Use the mapped UUID data base for launch vm script configurations.
5. Unify the ui_entry_api for '--out'
Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
For purpose weaken 'scenario' from config tool, remove 'scenario' dependency
from config tool.
Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Board defconfig depends on hypervisor configurations and vm configurations,
add this to support to parse board defconfig from vm configuration.
Tracked-On: #4634
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Rounding HI_MMIO_START, HI_MMIO_END to the closest 1G. This avoids
round up logic in the hypervisor.
Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Board config should relay on library/common.py and board_cfg_lib, then
remove the duplicate parameters and functions.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
