For purpose to refine the library/common and xx_cfg_lib, should have
to expands parameters and functions to common.py firstly.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
This patch does the following
1) Removes the limitation on BAR size for 1 GB
2) Align the BAR address to the BAR size
Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Find the 64-bit mmio window from /proc/iomem to generate HI_MMIO_START/HI_MMIO_END.
Tracked-On: #4569
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Need more information from iomem, so dump all the iomem information
from /proc/iomem to instead of system ram information.
Tracked-On: #4569
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Currently, config tool generate board files and scenario files in
acrn-hypervisor directory, the origin souce code would be corrupted by
the config tool. Config tool add '--out' option for user to give a path
to store the generated files, without this option, tool will generate
files in origin source code.
Tracked-On: #4517
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Modify the pattern to grap the correct PCI BDF from board information
file.
Tracked-On: #4530
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. add CONFIG_scenario=y config in $(BOARD).config file so that
SCENARIO parameter will not be needed when build with xmls.
2. add CONFIG_MAX_KATA_VM_NUM;
3. add CONFIG_ENFORCE_VALIDATED_ACPI_INFO=y because all ACPI info
generated by acrn-config has been validated;
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Remove '--enable_commit' argument since acrn-config will not use git tool any
more.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. To keep align with acrn-hypervisor source code, remove a function
that generates ve820 file.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Refine HV_RAM_START to keep 2M memory align for new board config.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. If the device configure space is not fixed by ACPI and its pbar address
is above 4G or lower than 2G, then remap the vbar address to high memory.
2. Due to GPU might have huge MMIO space which would result in
HV_RAM_SIZE overflow, skip its vBAR remapping for now when the size high
than 1GB.
Tracked-On: #4458
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch adds support for,
1. Storing MBA resource and its max supported clos value
in the target xml file under clos subsection.
2. Generating board.c file with MBA RDT resource.
Tracked-On: #3725
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Devices that support SR-IOV can expose their capabilities in
lspci -vv command as below. The offline tool, instead of picking
up the bios exposed memory region(bc000000) for the devices ends
picking up the SR-IOV memory region(00000000c0000000) and generates
VBAR address (in pci_devices.h). This is incorrect. This patch
fixes the offline tool to take the right memory region as the
VBAR address.
Sample lspic -vv log:
67:00.0 Ethernet controller: Intel Corporation Ethernet Connection
X722 for 10GbE backplane (rev 09)
Subsystem: Intel Corporation Device 0000
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
Latency: 0
Interrupt: pin A routed to IRQ 61
Region 0: Memory at bc000000 (64-bit, prefetchable) [size=16M]
Region 3: Memory at c1000000 (64-bit, prefetchable) [size=32K]
Capabilities: [160 v1] Single Root I/O Virtualization (SR-IOV)
IOVCap: Migration-, Interrupt Message Number: 000
IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
IOVSta: Migration-
Initial VFs: 32, Total VFs: 32, Number of VFs: 0, Function Dependency Link: 00
VF offset: 16, stride: 1, Device ID: 37cd
Supported Page Size: 00000553, System Page Size: 00000001
Region 0: Memory at 00000000c0000000 (64-bit, prefetchable)
Region 3: Memory at 00000000c1020000 (64-bit, prefetchable)
VF Migration: offset: 00000000, BIR: 0
Tracked-On: #4443
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch checks if RDT feature is supported by platform and
updates the CONFIG_RDT_ENABLED flag in the <$BOARD$>.config
file accordingly.
Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch adds support for as generating board.c file
with multiple RDT resources.
Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
value among RDT resources.
This patch identifies the least common supported clos value
from multiple RDT resource. This is done so as to have
consistent capabilities across all resource allocations.
From SDM, "The number of CLOS supported for the MBA feature
may or may not align with other resources such as L3 CAT. In
cases where the RDT features support different numbers of
CLOS the lowest numerical CLOS support the common set of
features, while higher CLOS may support a subset. For instance,
if L3 CAT supports 8 CLOS while MBA supports 4 CLOS, all 8 CLOS
would have L3 CAT masks available for cache control, but the
upper 4 CLOS would not offer MBA support. In this case the upper
4 CLOS would not be subject to any throttling control. Software
can manage supported resources / CLOS in order to either have
1) consistent capabilities across CLOS by using the common subset
or 2) enable more flexibility by selectively applying resource
control where needed based on careful CLOS and thread mapping".
We decided to go with option #1, as it will be more consistent
and less prone to user errorw hen programming the resource mask
MSRs.
Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
KATA VM is not supported on dual-core systems override the
MAX_KATA_VM_NUM to 0.
Tracked-On: #4319
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently, config tool will maintain a whitelist for the board which
need to hide some pci devices. For the board out of whitelist, we set
MAX_HIDE_PDEVS_NUM to 0.
Tracked-On: #3475
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Hv could be failed when hv ram start address when around 16, beacause when
booting from grub mode, hv and sos ram address would be overlaped.
This patch set the HV_RAM_START address above 256M for new board.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Set the DRHDx_IGNORE to false even there is no DEV_SCOPE under this
DRHD.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add CONFIG_SERIAL_x in $(borad).config, this will help to output
console log and help new board debug.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
For currently supported hardware such as KNL NUC, the scenario xml
file is not generated and the newly added non-contiguous variables
will not be present. This can lead to build issues. This patch adds
the second non-contiguous HPA variable to all supported hardware
for both logical_partition and hybrid modes. It also adds checks
to ensure that HPA2 is valid before using it while creating the
guest VM ve820.
Tracked-On: #4242
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The macro definition is changed in hypervisor code, so modify acrn-config
side accordingly.
Tracked-On: #4230
Signed-off-by: Victor Sun <victor.sun@intel.com>
SOS vm only support legacy serial port emulation, so we need to
hide non-legacy serial ports from webUI when user want to select
serial port as SOS console.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. unify get_vuart_info_id/get_vuart_id api in board/scenario/launch
config tool.
2. if vm use 'vuart1(tty)' method to power off, make sure this vm have
select the vuart1 'SOS_COM2_BASE'.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch fixes an issue with generation of guest ve820 when the size
of the memory is >512MB. The issue is primarily with respect to converting
between hex and int.
Tracked-On: #4219
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The patch adds acrn-config tool support for adding
non-continguous HPA allocations for pre-launched VMs
in hybrid scenario.
Tracked-On: #4217
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch modifies the python scripts in scenario,
board and vm-configuration to support,
1. Generation of seperate ve820 for each VM.
2. Ability to configure each VM's HPA from
acrn-config UI tool.
3. Non-contiguous HPAs for pre-launched VMs.
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Tracked-On: #4195
Acked-by: Anthony Xu <anthony.xu@intel.com>
Current ve820 generation script assumes the size of pre-launched
VM memory is less than or equal to 512 MB (Must be the assumption
of logical partition scenario as such).
This patch extends the script to handle pre-launched VM memory
sizes greater than 512 MB.
Tracked-On: #4182
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
parse default pci mmcfg base address from target board.
Tracked-On: #4173
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Skip to generate DRHDn_IGNORE to board.c, when there is no device scope
type on target platform DRHD definition.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently MMIO BAR size not support size above 4G,
print warning to user to set the MMIO size in 4G region from BIOS.
Target-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Minor changes on git commit message of config patch:
For board config patch, specify with "config patch for board xxx";
For scenario config patch, specify with "config patch for scenario yyy".
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There may be no physical serial port in the target board, and it will
stop generating board file, the patch add support to handle such case.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
If S3/S5 are not support by BIOS in some platform, will set them to 0
as default.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Current board parse logic would be broken if acpi_idle/acpi-cpufreq
driver is not loaded by native kernel.
This patch would just leave a warning to user and continue to parse
other information in this case.
Tracked-On: #4082
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
without the msr.h file the build will be failed when CAT is enabled.
Tracked-On: #4066
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Enhance the $(board).config for new board.
Serial config should be set in $(board).config for new board.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. Parse DRHD_INFO section from board config xml, and generate dmar
structure information to board.c
2. Copy macro of DRHD_INFO from board config xml to $(board)_acpi_platform.h
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Since msr_index relys on the MSR_IA32_L2_QOS_MASKn(n:max to 3)
macro which defined in hv source code, generate array that CLOS number
more than 4 means need define more than 4 macro.
This patch solve such issue by using MSR_IA32_L2/L3_MASK_BASE with the
msr index offset.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Some BIOS does not support s3/s5, so there might be no _S3 or _S5
package in host ACPI table, previous code did not handle this, so
the build would be failed with the generated board file.
Set default s3/s5 package value to 0 for such case.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Check git environment only when '--enable_commit' option was set.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Sometimes character '-' or space need to be converted to '_' to make string format uniformed.
Add this common api to satisfy such requirment and refine the code for board name generating.
Tracked-On: #3852
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Config tool will generate files for board/scenaro/launch, some files are
part of souce code for specify board. Git add/commit these files should
be one optional of user experience. Add "--enable_commit" parameter to
enable git add/commit.
usage:
--enable_commit: flag of whether to do git commit the config file changes
to current git branch. Do commit with this flag and not do without the flag.
Tracked-On: #3834
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The value of CONFIG_MAX_PCPU_NUM is stands for Processor CPU number and
it is grabed from board information.
Tracked-On: #3798
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Current python code could handle pci sub class name contain "-" as
expected, but some space characters may still exist. This patch support
to parse similar strings which contain "-" and ' ' for pci sub class name.
Also, add the index number as suffix for the similar strings
Tracked-On: #3788
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
align the usage of acrn-config tool and their README
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Need to reserved 16M for HV debug usage like sbuf/ramoops before HV RAM START
to avoid possible conflict with HV memory.
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.the script will parse the the board information which already
generated, $(scenario).xml modified by user, generate scenario
vm configuration and apply to the acrn-hypervisor source code base.
2.parse cpu/memory/ttys/rootfs information from native os and store it to
the source code
3.implemnt scenario_config and it's usage
usage: scenario_cfg_gen.py --board <board_info_file> -scenario <scenario_info_file>
board_info_file : file name of the board info
scenario_info_file : file name of the scenario info
sample:
$ python3 scenario_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
Also improvement board config generate usage:
sample:
$ python3 board_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
V1-V2:
1). parse board_setting.xml was removed as these configuration will be
stitch into scenario configuration
2). parse console for different formats
3). parse epc sections
4). add logical partition rootfs
5). support to parse clos, while webui set to None type
6). support to parse bootargs, while webui set to nul
7). convert '-' to '_' for pci sub class name while generating source file
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
1. add misc.py to get systemd ram and root device
2. add more specify comments for arguments of functions
v1-v2:
typo: Parser -> Parse
some grammar check
v2-v3:
add the message for Cx state
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
the script will parser the the board information which already generated on
target board, and apply to the acrn-hypervisor as a patch.
usage: board_cfg_gen.py --board <board_info_file>
sample:
$ python3 board_cfg_gen.py --board ../target_board/board_info.xml
v1-v2:
1. allow to generate new board patch
v2-v3:
1. modify the description of generator tools
2. parser board_name.xml file
3. coding as PEP8 guildline
Tracked-On: #3480
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Shuang Zheng shuang.zheng@intel.com
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
