Increase CONFIG_MAX_EMULATED_MMIO_REGIONS to 32, for more pci-vuarts.
Each pci-vuart vdev need 2 mmio BARs, if there are 8 pci-vuarts, they
need emulate 16 mmio regions.
But by default CONFIG_MAX_EMULATED_MMIO_REGIONS=16, that is not enough.
Tracked-On: #5491
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
remove PSRAM_PASSTHROUGH_PRE_RTVM config which is not used in
PSRAM config and disable psram config.
Tracked-On: #5418
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Add the 'reboot=acpi' kernel boot argument for pre-launched VMs
Add the code to sanity check if 'reboot=acpi' is specified in the
scenario files
If hardware reduced ACPI is detected, by default, Linux will set the reboot type to
use EFI for rebooting. "reboot=acpi" sets the reboot type to use ACPI for rebooting.
Tracked-On: #5411
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Change ACPI version from V3 to V5 to support hardware-reduced ACPI, which
is a V5 feature
Remove/obsolete the PM1X related stuff as they are not used for hardware-reduced
ACPI
Add the _S5 method in DSDT table
Using hardware-reduced mode allows to use a much simpler form of ACPI that
does not require supporting the legacy of previous versions of the specification
such as SCI IRQ.
Hardware-reduced mode is specified by setting the Hardware Reduced (HW_REDUCED_ACPI)
flag in FADT table.
If the HW_REDUCED_ACPI flag in the FADT table is set, OSPM will ignore fields related
to the ACPI HW register interface such as the PM1x control register. Instead, sleep
control/status registers can be used for system sleep state entry on hardware-reduced
ACPI systems.
Tracked-On: #5411
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
So that guest VM can recognize and use ACPI reset register to reboot
No need to specify "Flags (decoded below)" in FADT template, iasl will
calculate and fill in this flag for us
Tracked-On: #5411
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
generic
Add console and communication vuarts to:
misc/vm_configs/xmls/config-xmls/generic/<scenario>.xml
misc/vm_configs/xmls/config-xmls/template/<scenario>.xml
Tracked-On: #5425
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Changes:
1. assign 3 CPUs for WaaG on hybrid_rt scenario;
2. Passthrough NVME@9:0.0 for VM0 on hybrid_rt scenario;
3. Change rootfs from partition2 to partition3;
Tracked-On: #5390
Signed-off-by: Liang Yi <yi.liang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add following to default output scenarios vm_configurations.c:
- pci_dev_num
- pci_devs = sos_pci_devs
Both was defineded in CONFIG_SOS_VM.
Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
fill physical PTCT table into pre-launched vACPI table when PSRAM
is configured to passthrough to pre-launched RTVM.
Tracked-On: #5418
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
add PSRAM configs in xmls, only enable PSRAM and passthrough to
pre-launched RTVM for hybrid_rt scenario on tgl-rvp board.
Tracked-On: #5418
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
changes:
1. Change SOS VM rootfs to nvme0;
2. Change hybrid_rt scenario VM0 mem size to 1GB;
Tracked-On: #5238
Signed-off-by: Victor Sun <victor.sun@intel.com>
update tgl-rvp.xml for tgl boards with IFWI of tsn version to enable
the embeded tsn device.
Tracked-On: #5427
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
update vm configurations for hybrid_rt scenario on WHL/EHL/TGL/CFL
boards, add 1 YaaG and assign 1 more pcpu for WaaG.
Tracked-On: #5390
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
assign 2 CPUs for WaaG and add 1 YaaG on hybrid_rt scenario for
WHL/EHL/TGL/CFL boards.
Tracked-On: #5390
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
P2SB_BAR_ADDR related macros should only be defined in misc_cfg.h only when
p2sb is enabled in scenario xml.
Tracked-On: #5340
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Add configurations code of industry scenario and hybrid_rt scenario for
cfl-k700-i7 board to support build acrn binary from source code directly.
Tracked-On: #5212
Signed-off-by: Victor Sun <victor.sun@intel.com>
Add cfl-k700-i7 hybrid_rt xml to support ACRN hybrid_rt scenario on
cfl-k700-i7 board.
Tracked-On: #5212
Signed-off-by: Victor Sun <victor.sun@intel.com>
There is no default xml for hybrid_rt to to generate the
script of posted launch WaaG.
Tracked-On: #5336
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
update config xmls to make ivshmem size in decimal MB at description
and values.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add the TSN device in tgl-rvp board XML and configure it to
passthrough to pre-launched VM for hybrid_rt scenario on tgl-rvp.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
move MACRO of IVSHMEM region name to ivshmem_cfg.h and bug fix that
avoids multiple declarations of mem_regions in ivshmem_cfg.h
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This is a bug fix that avoids multiple declarations of mem_regions
Tracked-On: #4853
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
increase the length of DSDT table to avoid memory overwrited by
subsequent ACPI tables.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add TSN device OTN1 config into offline ACPI table for TSN device
passthrough to pre-launched RTVM.
v2) update TSN device list from bdf list to vid:pid list.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Use vm_type to configure the load_type/uuid/severity,
Delete uuid lines in config scenario.
Tracked-On: #4641
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
generate ASL code of ACPI tables for pre-launched VMs on nuc7i7dnb,
whl-ipc-i5, whl-ipc-i7, ehl-crb-b boards
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
enable TPM2 config on ehl-crb-b board and update TPM2 configs on
legacy boards.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
For EHL hybrid_rt scenario, the requirement needs a network device
passthough to pre-launched VM0.
Tracked-On: #5286
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add 2 MACROs: DEFAULT_PCI_MMCFG_START_BUS and DEFAULT_PCI_MMCFG_END_BUS
in platform_acpi_info.h.
Tracked-On: #5233
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
use offline tool to generate one binary of ACPI tables for pre-launched
VMs, then load the ACPI binary into guest physical memory as grub module.
Users can configure the resources or devices like TPM2 for the
pre-launched VM from sceanrio XMLs or UI, and the offline tool will
generate ASL code of the ACPI tables with the configured resources or
devices, then compile the ASL code to one binary when building ACRN.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
EHL PSE TSN GbE driver is default set to use 32bit of dma addressing.
net: stmmac: configure PSE Gbe to 32bit dma addressing
https://github.com/intel/linux-intel-lts/commit/011c8f
When VM has more than 4GB physical memory, Linux kernel uses the bounce
buffers (swiotlb) to translate kernel data in 64bit memory to 32bit
range for the sake of the DMA because iommu is not available. The
default swiotlb value 32768 is insufficient to support two PSE TSN GbEs
at the same time. Increase the value to 131072 otherwise two GbEs can't
link up.
Tracked-On: #5243
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add a new scenario xml file for EHL which is derived from hybrid_rt for
validation of certain passthru devices in prelaunched RTVM. Because the
configuration requires to disable GPIO support for SOS VM, it should
not be merged into the standard hybrid_rt scenario. According to this
change, remove the SCI passthru setting from existing hybrid_rt since
from now on hybrid_rt_fusa should be used for SCI passthru test.
Tracked-On: #5278
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
minor_ver should be le 2 when major_ver == 2.
Tracked-On: #5276
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
update the size of ivshmem memory region to [2MB, 512MB].
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Yuan Liu <yuan1.liu@intel.com>
Two PSE-GPIO controllers of EHL CRB require MSI-X emulation for
pass-thru because it uses multiple MSI vectors. Currently acrn-config
enables MSI-X emulation for only TSN devices. Enable MSI-X emulation
for PSE-GPIOs, too.
Tracked-On: #5242
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
After below commit in https://github.com/zephyrproject-rtos/zephyr
commit d0126a037d23484feebba00d2c0eac27e6393fef
Author: Zide Chen <zide.chen@intel.com>
Date: Wed Feb 5 08:32:00 2020 -0800
boards/x86/acrn: build it in x86_64 mode and switch to X2APIC
The zephyr image for acrn would be built in x86_64 mode by default, then the
load/entry address for pre-launched Zephyr image should be changed from
0x100000 to 0x8000 accordingly per below definition in zephyr .ld file:
zephyrproject_src/zephyr/include/arch/x86/intel64/linker.ld
SECTIONS
{
/*
* The "locore" must be in the 64K of RAM, so that 16-bit code (with
* segment registers == 0x0000) and 32/64-bit code agree on addresses.
* ... there is no 16-bit code yet, but there will be when we add SMP.
*/
.locore 0x8000 : ALIGN(16)
{
_locore_start = .;
The commit in zephyrproject is merged before zephyr v2.2 release, so from v2.2
on, HV need this fix to boot Zephyr as pre-launched VM.
Tracked-On: #5259
Signed-off-by: Victor Sun <victor.sun@intel.com>
add shm_region config in default launch XMLs to configure Inter-
VM communication for post-launched VMs.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch is to expose GPIO chassis interrupts as INTx to safety VM for
EHL. User can configure this per-VM attribute in scenario xml using the
following format:
<pt_intx desc="pt intx mapping.">
(phys_gsi0, virt_gsi0), (phys_gsi1, virt_gsi1), (phys_gsiN, virt_gsiN)
</pt_intx>
The physical and virtual interrupt gsi in each pair are separated by a
comma and enclosed in parentheses. If an integer begins with 0x or 0X,
it is hexadecimal, otherwise, it is assumed to be decimal. Example:
<pt_intx desc="pt intx mapping.">
(1, 0), (0x3, 1), (0x4, 2), (5, 6), (89, 0x12)
</pt_intx>
Tracked-On: #5241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This patch is to support direct assignment of P2SB bridge to one pre-launched
VM for EHL. User can configure this per-VM attribute in scenario xml:
<mmio_resources desc="MMIO resources.">
<p2sb>y</p2sb>
</mmio_resources>
Set p2sb to y to passthru P2SB bridge to VM, and n otherwise.
Tracked-On: #5221
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
