Initialize the VM's time_delta to provide a consistent time offset for
guests, and properly initialize vcpu timer-related CSRs (htimedelta and
vstimecmp) to enable guest timer virtualization.
Changes:
- Add time_delta field to vm_arch structure to track VM time offset
- Initialize time_delta to -cpu_ticks() at VM creation, making
guest time start from 0
- Save/restore htimedelta CSR in vcpu load/unload paths
- Initialize vcpu's htimedelta from VM's time_delta
- Reset vstimecmp to invalid value (0xffffffffffffffff) on vcpu reset
- Add SSTC (Sstc extension) capability check
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Implement the SBI IPI (Inter-Processor Interrupt) extension to enable
guest VMs to send software interrupts between virtual CPUs.
The implementation handles the SBI_IPI_SEND_IPI function call, which
allows a guest to target one or more vCPUs using either:
- A mask (bitmap of target harts relative to a base hart ID)
- Broadcast mode (when mask_base is UINT64_MAX)
The IPI is delivered by asserting the VS-level software interrupt
(VSSIP, bit 2) on each target vCPU. Proper validation is performed
to ensure hart IDs are within valid range and all masked harts exist.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Implement the SBI TIME (Timer) extension to allow guest VMs to program
virtual timer interrupts through the SBI interface.
The implementation handles the SBI_TIME_SET_TIMER function call, which
allows guests to set the vstimecmp CSR to schedule timer interrupts.
The vstimecmp value is written directly to the CSR and saved in the
vCPU context.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Replace SBI passthrough with proper virtualization of base extension
queries. For the Service VM, forward actual machine vendor/arch/impl
IDs from the underlying SBI. For guest VMs, provide dummy ACRN-specific
IDs to maintain isolation.
Changes:
- Return vSBI spec version 2.0 for GET_SPEC_VERSION
- Return ACRN implementation ID (55) and version for GET_IMP_ID/GET_IMP_VERSION
- Forward real mvendorid/marchid/mimpid to Service VM
- Provide dummy vendor/arch/impl IDs (0/0/0) to guest VMs
- Store machine IDs in vm_arch structure during VM initialization
- Remove unnecessary SBI passthrough for base extension queries
This provides better isolation and control over the virtual SBI
interface exposed to guests.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add wrapper functions to query machine vendor ID (mvendorid),
architecture ID (marchid), and implementation ID (mimpid) through
the SBI base extension.
These IDs identify the RISC-V processor vendor, microarchitecture,
and specific implementation respectively. The hypervisor needs to
retrieve these values from the underlying SBI firmware to forward
them to the Service VM via vSBI, allowing the Service VM to see
the actual hardware characteristics.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add virtual interrupt injection infrastructure for RISC-V hypervisor.
Implement vcpu_set_intr() and vcpu_clear_intr() to manage virtual
interrupt pending state by updating irqs_pending bitmap.
Add vcpu_inject_pending_intr() to inject pending interrupts into
VS-mode by updating HVIP CSR with atomic operations.
Tracked-On: #8844
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add virtual exception handling infrastructure for RISC-V hypervisor
and enables proper virtualization of RISC-V exceptions by allowing
the hypervisor to inject exceptions into guest VS-mode.
- Implement vcpu_set_trap() to inject traps to VS-mode
- Implement vcpu_queue_exception() to queue exceptions for vCPU injection
- Process pending exception requests in riscv_process_vcpu_requests()
v1->v2:
change vcpu_redirect_trap -> vcpu_set_trap
Tracked-On: #8844
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
RISC-V vcpu capability is represented by an ISA extension string.
Add API to adjust this string for virtual FDT.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Currently dbcn outputs directly to console. Outputs to ACRN
shell vm_console when other dependencies are ready.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Initialize Service VM vFDT by reserving hypervisor and pre-launched VM
memory regions.
The vFDT is copied to Service VM to the place just before the kernel
load address, and this needs to be fixed later when MMU module is
implemented.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Original interrupt context save/restore routine saves to/restore from
per-cpu stack. This commit modifies it to support saving to/restoring
from address pointed to by sscratch register.
When sscratch is 0, the assembly is functionally equivalent to the
old version (save to/restore from per-cpu stack)
When sscratch is not 0, the assembly saves to/restores from the place
that sscratch points to.
hstatus is also added to the trap frame as this affects the virtual
mode the trap returns to.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Unlike x86 which explicitly distinguishes guest traps and host traps (VM
exits vs. IDT trap gates), risc-v unifies them to a single trap gate
with bits in multiple CSRs representing the privilege mode before the
trap. This commit follows this design.
Due to this change the arch_vcpu_thread in risc-v was basically
abandoned, and used only as a first-time entry point to guest, with the
rest of the original x86 arch_vcpu_thread being re-implemented following
above single-entry design.
Save/restore routine is also being re-implemented to account for
both hs-mode traps and v-mode traps. sscratch is used to mark the place
where the context is being saved to/restored from. When sscratch is
zero at the time of the trap, the context is saved into host stack.
When sscratch is non-zero, the context is saved to vcpu->arch.regs
(similar for restore).
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch integrates RISC-V with the common IRQ framework:
- Register software and timer interrupt handlers via request_irq().
- Refine dispatch_interrupt() to handle interrupts via do_irq().
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Move the declarations of arch-specific IRQ functions from their
arch-specific headers into the common header file.
Also rename these functions from xxx_arch() to arch_xxx() for better
naming consistency across architectures.
This change follows the style defined for multi-arch development.
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch fixes two bugs. The reason for writing them
into one commit is that they are related and the fixes
change the same places.
The first bug:
The size of struct stack_frame is 0x78, not 0x80, but
the save/restore assembly routine allocates/deallocates
the size of stack frame by 0x80.
The vcpu thread stack is initialized by allocating
sizeof(struct stack_frame) from the top of the stack
and put initial values there (arch_build_stack_frame).
The vcpu thread stack will underflow at the first
time this thread gets scheduled. So the fix is to change
the 0x80 to 0x78 in save/restore routine.
The second bug:
Save/restore routine needs to capture sstatus, as different
threads might have different interrupt enabling settings.
For example, vcpu threads always get scheduled out when the
interrupts are disabled, but idle thread needs to have the
interrupts enabled. So sstatus needs to be saved/restored.
The fix is to add a new member sstatus in struct stack_frame.
Adding a new member in struct stack_frame boost the size
of struct stack_frame to 0x80, which in this case the fix
of the first bug is no longer needed.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
There are two reasons to use inline functions and numbered-CSR
instead of simply string concat.
1, With old style, CSR names have to be written in lower cases
and cannot prefix anything. This sometimes causes confusion with
variables. For example, csr_write(sstatus, sstatus). Changing to
inline function with MACROs can reduce confusion:
csr_write(CSR_SSTATUS, sstatus)
2, Using number macros allows us to manage CSRs in a more organized
way. We can now put CSR names in variables or arrays and access them
using variables instead of just string names.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Bare boot protocol is a protocol to be used when there are no protocols
(such as multiboot1/2) are available: ACRN have no way to know where its
modules are being loaded, how large they are, and what are their command
line arguments.
Bare boot protocol allows you to pre-configure (hard-code) modules' address and
sizes. ACRN will find modules based on the pre-configured information
without the need of a bootloader passing information to it.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Besides implementing copy_from/to_gpa, this commit also wraps a dummy
commit in mmu.c that exposes API of adding hv mmu mapping.
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add stack protector implementation for RISC-V architecture using a
global __stack_chk_guard variable. This differs from x86 which uses
per-CPU stack canaries.
Tracked-On: #8834
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add RISC-V specific implementation of arch_get_random_value() that
combines entropy from rdcycle and rdtime counters. This provides a
portable solution since the Zkr entropy extension is optional in RVA23
profile.
Tracked-On: #8834
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The ACRN hypervisor binary can be loaded at a physical address different
from its configured link address (CONFIG_HV_RAM_START) due to bootloader
constraints or memory layout requirements. However, the current MMU
initialization code always maps the hypervisor using the compile-time
link address, which causes page faults when the hypervisor is actually
loaded elsewhere. Since ACRN uses identity mapping (VA == PA) for the
hypervisor address space, both the virtual and physical base addresses
in the page table mapping must reflect the actual runtime load address,
not the link-time address.
Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The following flags are assigned to CFLAGS/LDFLAGS when trying to build
a relocatable acrn.out (ELF):
- CFLAGS += -fpie & ASFLAGS += -fpie:
- Produces position-independent code suitable for executables (not shared libraries).
- Uses PC-relative addressing for global variables and function calls
- Generates code that can be loaded at any memory address
- Together with -mcmodel=medany is used to support "Medium Position
Independent Code Model"
- CFLAGS += -fvisibility=hidden:
- Enabled with --gc-sections, the -fvisibility=hidden compiler flag
increases the number of symbols the linker can identify and remove
as unused. This reduces the final binary size and can improve
performance
- LDFLAGS += -shared:
- Create a shared object (ELF::e_type == 3) instead of an executable
- This is required to support a relocatable acrn.out
- LDFLAGS += -Wl,-z,notext
- Allow relocations in read-only segments (text relocations)
- Resolves linking errors when absolute addresses exist in read-only
sections
- LDFLAGS += -Wl,-Bsymbolic
- Prioritizes local symbol definitions over external ones
- Improves performance by avoiding PLT (Procedure Linkage Table) calls
for local symbols
- LDFLAGS += -Wl,-z,defs
- Forces the linker to resolve all symbol references at link time
- Report undefined symbol errors during linking
In summary:
- -fpie + -shared: Creates a position-independent shared object that can
be loaded as an executables
- -z,notext + -Bsymbolic: Allows internal relocations while keeping
symbols local
- -z,defs: Ensures all symbols are properly defined, preventing runtime
errors
We are using --start-group/--end-group to link all the modules. When
using -shared, the linker discards unused symbols by default, even if
they are marked with KEEP() in the linker script. This is because shared
libraries typically allow undefined symbols to be resolved at runtime.
To ensure the entry point is included, we need to add EXTERN(_start) to
the linker script, which forces the linker to treat _start as a required
symbol that must be resolved during the linking process.
Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements relocation support for ACRN RISC-V to enable
position-independent execution. The hypervisor can now be loaded at any
physical address and will automatically relocate itself at runtime. Key
changes:
- Add relocate() function to process R_RISCV_RELATIVE relocations in
.rela sections during early boot
- Implement arch_get_hv_image_delta() to calculate the load address offset
from the configured base address
- Add relocation processing in cpu_entry.S before jumping to C code
- Update linker script to include .rela sections for relocation data
- Define R_RISCV_RELATIVE relocation type and linker symbol definitions
Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
add BSP and AP initialization function.
and call uart16550_init to update uart_base_address
after init paging.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
riscv only need to map mmio and hv owned memory, donot
need to map guest memory. And need detection for svpbmt extension
to support page table defined memory attribute programming.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add functions get_board_hv_device_start/get_board_hv_device_size
to get mmio device start address and size. These are needed to be
generated by config tool or runtime parsing DTS, wrap the method
here.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
this patch calculate riscv static pages number for page pool.
riscv donot need to map guest memory. use link script address
label to map code size.
For risc-v:
1) if the platform doesn't support PCIe devices
The address space layout for risc-v is like
| |
| MMIO |
| |
| ... |
| |
| RAM |
| |
For all its address space, one 1GB page table is enough which cover 512G
For MMIO or RAM, if its start address and end address is 1G aligned, there's no 2M
or 4K page table is needed. if their address are not 1G aligned, two 2M page table
is enough for MMIO or RAM. The issue here is that if we neetid 4K page entries for
different page attributes. So we need to reserve enough 4K page tables for that requirement.
2) if the platform support PCI devices, for the low MMIO range, another two 2MB page
table may needed. for the high MMIO range, its depends on the max physical address bits of
the platform and the high MMIO range reserved by the BIOS.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add hypervisor pagetable manipulate interface to riscv arch directory,
which is needed by the common interface, and add riscv ppt pgtable
structure implementation.
Tracked-On: #8831
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: hangliu1 <hang1.liu@intel.com>
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move some funcitons like hpa2hva to common file.
change some files to include file from asm/pgtable.h to common/pgtable.h
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
For now, BOARD should use the qemu-riscv for risc-v.
For RISC-V:
make hypervisor BOARD=qemu-riscv SCENARIO=shared ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-
For x86:
make hypervisor BOARD=qemu SCENARIO=shared [ARCH=x86]
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Now doesn't want introduce the PCI module since PCI CFG access should be arch
special.
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
get_vm_from_vmid,is_paused_vm and is_poweroff_vm should be common APIs.
But now doesn't implement them as common for not introduce more VM related
data structure and APIs.
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
