hangliu1 a436f72493 hv: riscv: add access usr memory interface ...

Add pre_user_access() and post_user_access() interfaces
to protect mmio from hypervisor accidental access,
SMAP extensiton need to be detected

Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-10-21 14:14:55 +08:00

..

boot

hv: risc-v: add assembly code for BSP and AP boot

2025-09-15 13:12:21 +08:00

guest

uart16550: add a CONFIG to enable PCI uart16550

2025-10-14 14:45:12 +08:00

cpu.c

hv: multiarch: move some function to common

2025-10-21 14:14:55 +08:00

dummy_entry.S

…

dummy.c

…

init.c

hv:riscv: add memory initizalization

2025-10-21 14:14:55 +08:00

intr.S

hv: riscv: irq: add interrupt initialization and handlers

2025-09-29 14:01:00 +08:00

irq.c

hv: abstract IRQ related macros

2025-09-29 14:01:00 +08:00

link_ram.ld.in

hv: risc-v: update link script

2025-09-15 13:12:21 +08:00

Makefile

hv: riscv: add riscv memory interface

2025-10-21 14:14:55 +08:00

mmu.c

hv: riscv: add access usr memory interface

2025-10-21 14:14:55 +08:00

notify.c

hv: add arch_send_reschedule_request implementation for riscv support

2025-09-30 12:31:07 +08:00

pgtable.c

hv: riscv: add riscv memory interface

2025-10-21 14:14:55 +08:00

sbi.c

hv: riscv: fix the implementation of send_ipi

2025-10-10 11:15:17 +08:00

sched.S

hv: add arch_switch_to support for riscv

2025-09-30 12:31:07 +08:00

timer.c

risc-v: initial timer codes

2025-09-17 08:55:12 +08:00

trap.c

dump: add exception dump for risc-v

2025-10-16 09:45:08 +08:00