Commit Graph

117 Commits

Author SHA1 Message Date
Qi Yadong
4c8c7cc8d1 trusty: initialize tsc_offset to zero
Per trusty design, trusty requires a monotonic increasing
secure tick(TSC) at run time. This secure tick will used
to mitigate password/pin force attack, control key expiration,
etc.

Currently, the TSC_OFFSET is enabled. And guest will got
(host_tsc + tsc_offset) when execute rdtsc/rdtscp/rdmsr to
aquire tsc value. The host_tsc is always keeping increasing
during the runtime.

So initialize tsc_offset of trusty to 0 will ensure the
secure tick feature.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-09 12:37:02 +08:00
Jason Chen CJ
d937dd09df ept: change eptp to PA
eptp should be record as PA.

this patch changed nworld_eptp, sworld_eptp and m2p eptp to PA type,
necessary HPA2HVA/HVA2HPA transition is used for them after the change.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-09 12:36:09 +08:00
Jason Chen CJ
50630c2e4b mmu: identify VA and PA in mmu.c
- read/write page table entries should use VA which defined as "void *"
- the address data in page table entries should us PA which defined as
  "uint64_t"

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-09 12:36:09 +08:00
Victor Sun
8e8aa4a6dc HV: add px data of bxt j3455 SOC
The cpu model name of "Intel(R) Celeron(R) CPU J3455 @ 1.50GHz" is used for
APL NUC which is in Acrn official suport list.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-04-08 16:54:42 +08:00
Victor Sun
d0b7c172d4 HV: trap and validate px request
Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-04-08 16:54:42 +08:00
Victor Sun
0cca1feab2 HV: add hypercall interface of get vcpu state data
We can use this interface for VHM to pass per-cpu power state data
to guest per its request.

For now the vcpu power state is per-vm, this could be changed if
per-cpu power state support is required in the future.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-04-08 16:54:42 +08:00
Victor Sun
c47aa3648d HV: setup px info when create vm
The vm px info would be used for guest Pstate control.
Currently it is copied from host boot cpu.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-04-08 16:54:42 +08:00
Victor Sun
1ab5010910 HV: load cpu px data in boot
The patch takes Intel ATOM A3960 as example that hard code all Px info
which is needed for Px control into Acrn HV and load it in boot process.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-04-08 16:54:42 +08:00
Victor Sun
5f406fb335 HV: add cpu model name
The cpu model name would be used to distinguish which hard coded data
need to be loaded to boot_cpu_data;

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-04-08 16:54:42 +08:00
Jason Chen CJ
860d9e6bd7 mmu: refine functions for invept
- rename mmu_invept to invept
- panic if HW doesn't support invept

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-04-08 16:50:02 +08:00
Jason Chen CJ
0b48ac96a9 mmu: replace ASSERT with panic in fetch_page_table_offset
all callers for fetch_page_table_offset should already make sure
it will not come to an unknown table_leve, so just panic here.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-04-08 16:50:02 +08:00
Jason Chen CJ
f5b3f2862c mmu: refine functions walk_paging_struct & update_page_table_entry
- walk_paging_struct should return sub_table_addr, if something wrong,
  it return NULL
- update_page_table_entry should return adjusted_size, if something wrong
  it return 0

the change is valid under release version, as at that time, ASSERT in
walk_paging_struct is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-08 16:50:02 +08:00
Jason Chen CJ
7611251339 mmu: refine functions get_table_entry & obtain_last_page_table_entry
- remove unused map_params in get_table_entry
- add error return for both, which is valid under release version,
  as at that time, ASSERT in get_table_entry is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-08 16:50:02 +08:00
Jason Chen CJ
e863b4135c mmu: refine function break_page_table
function break_page_table should return next_level_page_size, if
something wrong, it return 0.

the change is valid for release version, as at that time ASSERT()
in break_page_table is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-08 16:50:02 +08:00
Jason Chen CJ
22948c2af0 mmu: refine function map_mem_region
function map_mem_region should return mapped_size, if something wrong,
it return 0.

the change is valid for release version, as at that time ASSERT()
in map_mem_region is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-08 16:50:02 +08:00
Jason Chen CJ
59dea38ee8 mmu: refine functions modify_paging & map/unmap/modify mem
add error return for all, which is valid under release version,
as at that time, ASSERT in modify_paging is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-08 16:50:02 +08:00
Jack Ren
0c0d882084 UEFI: get the guest entry address explicitly
Previously with the help from gcc, __builtin_return_address(0) is
used as the guest entry address, but it can't work well with gcc 7.3
and leads to the guest unable to return to UEFI correctly.
Let's get it explicitly.

Signed-off-by: Jack Ren <jack.ren@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-08 11:14:59 +08:00
Geoffroy Van Cutsem
465ce972a2 Travis CI: enable Ubuntu 16.04 and Fedora 26 testing
Enable compilation test for Fedora 26 and Ubuntu 16.04. The tests
will run for all combinations of RELEASE={0|1} and PLATFORM={sbl|uefi}

Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2018-04-06 22:28:46 +08:00
Geoffroy Van Cutsem
b8b2d037c3 Enable Travis CI for all combinations
Enable the Travis CI testing for all combinations of variables
that can be set at compile-time. I.e. RELEASE={0|1} and
PLATFORM={0|1}

Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2018-04-06 22:28:46 +08:00
David B. Kinder
45d8190f3c doc: fix hypercall API doxygen errors
Documentation for parameters must match exactly in spelling and case.
Parameter named "vcpu" was incorrectly documented as "VCPU", and
parameter named "param" was documented as "param's".

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-04-06 12:35:06 +08:00
yechunliang
85b29e1c28 replace malloc and memset with calloc
malloc: allocate a block of memory, the contents of the block are undefined.
calloc: allocate a block of memory for an array of num elements and initializes all its bits to zero.

Signed-off-by: yechunliang <yechunliangcn@163.com>
2018-04-06 12:34:26 +08:00
Mingqiang Chi
78355029ff hv:check continuous hpa when create secure world
Add check_continuous_hpa API:
when create secure world,if the physical
address is not continuous, will assert.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-06 12:32:44 +08:00
Mingqiang Chi
42a7147cec hv:add destroy Secure world API
This patch added API destroy_secure_world, which will do:
-- clear trusty memory space
-- restore memory to SOS ept mapping
It will be called when VM is destroyed, furthermore, ept of
Secure world will be destroyed as well.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-06 12:32:44 +08:00
Li, Fei1
445a30849c hv: shell: add cpuid command
Add cpuid shell command for test

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-04-06 12:32:13 +08:00
Qi Yadong
877558ea23 trusty: fix typo of comments
Remove TODO comments since it has been done below the comments.
Typo fix: startup_info --> startup_param.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-06 12:31:35 +08:00
Geoffroy Van Cutsem
3b90a66a1d Add initial .travis.yml and Dockerfile (Clearlinux)
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Signed-off-by: T <shrmrf@users.noreply.github.com>
2018-04-06 09:27:18 +08:00
Minggui Cao
9dbd30303b add vmx msr ops protection from guest OS
1.it doesn't support VMX for guest OS
2.for MSR out of control, inject GP to guest OS.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 15:38:27 +08:00
Mingqiang Chi
7660187f9e hv: free ept memory enhancement
--add free_paging_struct api, used for free page tables
  it will clear memory before free.
--add HPA2HVA translation when free ept memory

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 11:54:52 +08:00
Mingqiang Chi
c31c3d7f84 hv:bugfix for the API of creating secure world
Before this patch, HV accesses PML4E of secure world when the PML4
doesn't exist,will access null pointer.
Fix as follow:
Before the copy of PDPTE,will allocate memory and write PML4E,
then copy the PDPTE.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 11:54:52 +08:00
Junjie Mao
ac61ae0ae5 hv: cpu: use the physical address limit from CPUID when available
Per SDM Vol. 2:

    If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
    number supported should come from this field.

This patch gets the maximum physical address number from CPUID leaf
0x80000008 and calculates the physical address mask when the leaf is
available.

Currently ACRN does not support platforms w/o this leaf and will panic
on such platforms.

Also call get_cpu_capabilities() earlier since the physical address mask
is required for initializing paging.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 10:52:12 +08:00
Junjie Mao
802080e348 cpu: cache the maximum input value for CPUID extended function
Per SDM:

    When CPUID executes with EAX set to 80000000H, the processor returns
    the highest value the processor recognizes for returning extended
    processor information. The value is returned in the EAX register and is
    processor specific.

This patch caches this value in the global cpuinfo_x86.cpuid_leaves. This
value will be used to check the availability of any CPUID extended
function.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 10:52:12 +08:00
Junjie Mao
d0ce6a9fc6 hypercall: Fix compile error caused by missing memcpy function
Assignment of structures are implemented using memcpy which is not
available in the hypervisor. This patch convert such assignment to an
explicit memcpy_s() call.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 10:52:12 +08:00
Minggui Cao
e17455fa86 enable TSC-offset & add TSC MSR emulation
enable TSC offset in VMX, so if TSC MSR is changed by guest OS,
write a caculated value into TSC-offset, then host TSC will not be changed.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: He, Min <min.he@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-04 10:23:03 +08:00
Yonghua Huang
a2bffc7630 hv: pass-through xsave feature to guests
enable Xsave feature and pass-through it to guests
 update based on v2:
  - enable host xsave before expose it to guests.
  - add validation for the value to be set to 'xcr0' before call xsetbv
    when handling xsetbv vmexit.
  - tested in SOS guest, created two threads to do different
    FP calculations,test code runs in user land of sos.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-03 17:50:27 +08:00
Junjie Mao
677cb6f24a treewide: fix declarations of functions with empty parameter lists
According to C99:

    The empty list in a function declarator that is not part of a definition of
    that function specifies that no information about the number or types of the
    parameters is supplied.

This means gcc is happy with the following code, which is undesirable.

    void foo();    /* declaration with an empty parameter list */

    void bar() {
        foo();     /* OK */
        foo(1);    /* OK */
        foo(1, 2); /* OK */
    }

This patch fixes declarations of functions with empty parameter lists by adding
an unnamed parameter of type void, which is the standard way to specify that a
function has no parameters. The following coccinelle script is used.

    @@
    type T;
    identifier f;
    @@

    -T f();
    +T f(void);

New compilation errors are fixed accordingly.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-04-02 13:57:43 +08:00
Jack Ren
ec6b6aa4ff version: v0.1-rc3
Signed-off-by: Jack Ren <jack.ren@intel.com>
2018-04-02 10:25:45 +08:00
Jack Ren
d0ab58cc81 update home page information
Signed-off-by: Jack Ren <jack.ren@intel.com>
2018-04-02 10:18:59 +08:00
Mingqiang Chi
c652e36afb hv: Save secure world memory info into vm instead of vm0
A bugfix for saving secure world memory info.
Maybe there are multiple UOS, each VM has its own secure
world and normal world, should save memory info into individual VM.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-03-30 19:49:29 +08:00
Rusty Lynch
e4c243cc97 Fix compile error caused by missing memcpy function
On some toolchain configurations direct struct assignments will
default to a memcpy operation which is not present in this
environment, so explicitly use the internal memcpy_s function.

Signed-of-by: Rusty Lynch <rusty.lynch@intel.com>
2018-03-30 19:49:03 +08:00
Zheng, Gen
794de35426 UEFI: update documentation
Add a new document named ACRN_UEFI.txt to direct user how
to use the acrn.efi.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
9f79dddb12 UEFI: add FIXME comments to function emalloc() & __emalloc()
Add a FIXME comment that the emalloc() & __emalloc cannot
guarantee to return address under 4G, and the hypervisor
cannot handle params, which address is above 4G, delivered
from efi stub.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
14c92640f0 UEFI: create new func named construct_mbi
Cleanup the mass code for constructing multiboot info

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
0762798543 UEFI: cleanup functions in boot.c file
Remove the useless function named get_path().
Remove the useless function named print_ch().
Remove the useless function named isspace().
Move the function memory_map() from boot.c to malloc.c

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
edde39b368 UEFI: header file cleanup
Move the header content from boot.c to boot.h

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
835af7ef6a UEFI: change the efi_ctx passing method
Save the pointer of efi_ctx in mi_drivers_addr field of
multiboot structure and pass to hypervisor, not by
saving in register RDX(the third default parameter in
64bit call function).

With this method, we can be compatible with the original
32bit boot parameters passing method and no need to
large the array size of boot_regs in hypervisor.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
f216b57415 UEFI: change the acrn boot flow on uefi platform
With current code, the acrn.efi is inserted between
cl bootloader.efi and bzImage.efi that destroyed the chain
relationship of cl bootloader and cl bzImage.efi.
And the following is current boot flow:
UEFI -> cl bootloader.efi -> acrn.efi -> bzImage.efi

The purpose of this patch is resume above chain relationship,
and make uefi vm return to efi stub context once launched,
then continue to call the UEFI API(LoadImage/StartImage) to launch
cl bootloader or other bootloaders. So the boot flow will
change to be as below:
UEFI -> acrn.efi -> cl bootloader.efi -> bzImage.efi

After applying this patch, the code related to loading
bzImage.efi and getting pe_entry is unnecessary due to
the bzImage.efi will not be launched by acrn.efi directly,
so it is removed.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Zheng, Gen
33fb5f5cac UEFI: bug fix on delivering RSDP
With current code, memcpy rsdp to 0x500 maybe overwrite uefi
code/data region.

So remove the legacy BIOS deliver method of RSDP, which need copy
the RSDP to EBDA space which is addressed by the 16bit pointer
at 0x40E or upper memory BIOS space 0xe0000-0xfffff. And just
deliver the pointer of RSDP, which is already saved in UEFI system
table, to hypervisor.

Create a function named efi_init() to separate efi initialize code.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-03-30 19:48:46 +08:00
Qi Yadong
1eece0d5e6 Rename TIME_MS_DELTA to CYCLES_PER_MS
TIME_MS_DELTA is not clear enough, rename it to CYCLES_PER_MS.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-03-29 14:54:23 +08:00
Qi Yadong
abcd765f2d io: remove pio emulation restriction
Currently, the serial log is printed through IO(0x3f8).
Secure World will print serial log by port 0x3f8. So
remove the ASSERT for Secure World booting.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-03-29 14:54:23 +08:00
Qi Yadong
4af2f04bd2 trusty: add key_info for trusty bring-up
For trusty bring-up, key_info is needed.
Currently, bootloader did not transfer key_info to hypervisor.
So in this patch, use dummy key_info temporarily.

Derive vSeed from dSeed before trusty startup, the vSeed will
bind with UUID of each VM.

Remove key_info from sworld_control structure.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-03-29 14:54:23 +08:00