Commit Graph

43 Commits

Author SHA1 Message Date
Junjie Mao
5cf9ac714c board_inspector: extend DSDT parser to allow parsing arbitrary trees
With AML templates for devices in the board XML, the parser now needs to be able
to parse a stream as an arbitrary object. This patch adds the `parse_tree`
method to the acpiparser.aml.parser module for this purpose.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
94d517b514 board_inspector: extract Compatible IDs of devices
In addition to the mandatory _HID (Hardware ID), the ACPI spec also defines
an optional _CID (Compatible ID) object for device identification.

This patch enhances the ACPI extractor by parsing the _CID objects of devices as
well.

Tracked-On: #6320
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
879c6c11ca board_inspector: more verbose messages
It is quite common to meet permissions errors when opening a specific
region of /dev/mem due to kernel configurations. This patch adds a bit more
logs on this for eaiser debugging.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
26021bd467 board_inspector: add interrupt pin routing and usage
This patch adds interrupt pin related information into the board XML,
including:

  * The PCI routing table in ACPI DSDT/SSDT are parsed and generated into
    the board XML as "interrupt_pin_routing" nodes.

  * IRQs encoded in _CRS directly are represented as resources of type
    "irq".

  * Interrupt lines (i.e. INTx#) of PCI devices are represented as
    resources of type "interrupt_pin". When the PCI routing table is
    available, the corresponding interrupt line is identified and
    represented as the "source" attribute of the resource node.

Due to the existence of vIOAPIC in ACRN VMs, the board inspector interprets
the \_PIC method with parameter 1 to inform the ACPI namespace that the
interrupt model should be in APIC mode.

v1 -> v2:
  * Remove the msi_enable variable which is defined but never used.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
a3aa0797b1 board_inspector: add builders of AML AST nodes
This patch adds the acpiparser.aml.builder module which provides methods to
construct AML trees from scratch in Python. Similar to how parsers and
binary generators are implemented, this module constructs most builder
methods from the AML grammar defined in the acpiparser.aml.grammar
module. AML objects whose grammar are not present in the grammar module
require special treatment and their builders are implemented
explicitly. The methods have the same name as the AML tree labels defined
in the grammar.

In addition, this module also provides the method `build_value` which
converts plain integers, strings or interpreter values (which are defined
in the datatypes module) to AML trees.

With the builders, the `interpret_method_call` method in the
ConcreteInterpreter is refined to build the (fake) MethodInvocation node
using the builders and handle the actual parameters as well.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
e91ace7341 board_inspector: refactor tree visitors and transformers
Tree visitors usually have a fixed direction (either top-down or bottom-up)
and invoking a visitor with a wrong direction typically leads to unintended
behavior. However, the current implementation exposes both `visit_topdown`
and `visit_bottomup` methods to users, allowing callers to invoke the
visitors in an undesigned way. The same issue exists in the implementation
of transformers.

This patch refactors the base classes of visitors and transformers so that
they require an explicit direction from their sub-classes to
initialize. Callers of the visitors and transformers are now expected to
invoke the `visit` or `transform` methods without assuming the correct
direction of the visitor or transformer. The original `visit_topdown` or
`visit_bottomup` methods (or their transformer counterparts) are now
used to initialize the `visit` method and can be used by the subclasses in
case those subclasses visits the tree in a customized manner.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
55554e7d56 board_inspector: add a visitor to generate AML binary from trees
This patch introduces a visitor that converts an arbitrary AML tree to an
AML binary. Most nodes can be converted in a straightforward way by
following the defined grammar, but the following nodes require some
additional effort:

  - NameStrings can be formatted as either a NameSeg (i.e. four upper case
    characters), a DualNamePath, a MultiNamePath or a NullName.

  - PkgLengths are recalculated according to the actual length of the
    following object (in case they are changed dynamically after being
    generated by the parser) and generated following the AML encoding of
    such lengths.

The visitor works in a bottom-up manner, i.e. the children are visited and
converted to binary before the parent.

The whole trees parsed from DSDT/SSDTs are now also stored in the Context
for further reference.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
b119a0b824 board_inspector: collect descriptions of ACPI devices
_STR is another device identification object defined in ACPI spec that
describes a device. This patch collects this string (when available) into
board XML as well.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
127e12a56a board_inspector: add a property to reflect the encoded IRQs in RDT
This patch adds the property `irqs` to the class SmallResourceitemIRQ so
that the list of IRQs encoded in this resource item can be retrieved
easily.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
0991f7f03b board_inspector: add a parser of PCI routing tables
This patch adds a parser to the PCI routing tables returned by _PRT objects
of platform devices. The parsed result is a list of PRTMappingPackage
instances, each of which is a named tuple with the following fields:

  * address: a dword with higher 16 bits being the function number and
    lower 16 bits all 1's.
  * pin: a byte representing the mapped pin.
  * source: either a DeviceDecl of the device that allocates the interrupt
    line, or the byte 0.
  * source_index:
    - If `source` is a DeviceDecl, this is the index of the interrupt
      source within that device.
    - If `source` is 0, this is the interrupt line connected to the pin.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
503b1ee317 board_inspector: fix returning nested local variables
Local variables can be assigned with formal arguments in AML. As a result
when interpreting a DefReturn node, the interpreter shall unwrap multiple
layers of argument/local variable wrappings until a concrete value is
found. This patch implements this logic.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
0b46440b32 board_inspector: strip an end tag when concat resource templates
Resource template buffers always end with an end tag. Concatenation of two
resource buffers thus requires that the end tag of the first buffer is
stripped. This patch adds this logic to the interpretation of DefConcatRes
AML nodes.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
774b60ac2d board_inspector: adjust logging levels
The warning, info and debug logging levels are intended to be used in the
following way.

  * Warnings are used when users are expected to be aware of a certain
    failure.
  * Info messages are used to track parsing process and major internal
    errors for development.
  * Debug messages are used to collect verbose debug logs.

To align the current usage of logs to the above guidelines, this patch
adjusts the logging level of the following messages:

  * DSDT/SSDT interpretation failures are now warnings, not information
  * Failures of parsing deferred AML blocks are now information, not debug
    messages

The default log level when running `cli.py` is adjusted to WARNING as well,
as INFO is primarily used for development. A new command line option
`loglevel` is added to adjust the log level per user needs.

v2 -> v3:
  * Make address collisions in ACPI namespace as an info rather than a
    warning.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
523ce8ad31 board_inspector: Remove dead code in parser.py
A DualNamePath clause is a NamePath that only follows rootchar or
prefixpath. Thus, it is never necessary to check if a dot is necessary for
separating segments before a DualNamePath. This patch removes the code that
conduct that check.

Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
a39f2995ad board_inspector: check if BAR base is 0
It is seen occasionally that a memory/port BAR of a PCI device is
programmed with the address 0 which is clearly invalid. This patch
gracefully handles this case by printing an error to warn the users that
this device cannot be passed through to any VM.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
1ad836e9a8 board_inspector: fix scope opening in the AML parser
According to section 19 of ACPI spec 6.4, the following clauses open name
scopes (in addition to the Scope clauses).

  - Function
  - Device
  - Method
  - Power Resource
  - Thermal Zone

The current AML parser only opens a scope when parsing DefMethod and
DefDevice, however. This patch fixes the AML parsing by opening a scope on
visiting a DefPowerRes or DefThermalZone clause.

Note: Functions in ASL are equivalent to Methods at AML level.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
a5f5ed0865 board_inspector: fix unregisteration of conditionally disabled objects
The current ConditionallyUnregisterSymbolVisitor has the following two
issues.

  1. The visitor will crash when a DefIfElse node is not fully parsed due
     to failed deferred expansion.

  2. Nested DefIfElse of disabled blocks are still checked and one of its
     branch may still take effect.

This patch fixes those issues by checking the predicates of a DefIfElse
block only when conditionally_hidden is False and check existence of
TermList and DefElse clauses.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
35edd7804a board_inspector: fix an opcode peek issue
When parsing a sequence of clauses, it is not necessary to peek an opcode
from the current stream unless that sequence starts with one. Peeking an
opcode is even an error when the actual clause is empty (e.g. as a
TermList).

This patch makes the SequenceFactory only peeking at the next opcode when
the grammar expects one.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
3bcb3146ad board_inspector: improve readability and performance of AML parser
This patch refines the AML parser to improve its readability and
performance in the following ways.

  1. A Tree object now has the parts of the corresponding object being
     member fields. As an example, a Tree with label `DefMethod` now has
     members `NameString`, `MethodFlags` and `TermList`.

  2. It is now possible to assign names each part of an object. The grammar
     is updated to assign different names to the parts with the same type
     in the same object.

  3. Invocation to intermediate factories is now skipped. As an example,
     when parsing a ByteConst that acts as a ByteIndex, the original
     implementation invokes the following factories in sequence:

         ByteIndex -> TermArg -> DataObject -> ComputationalData -> ByteConst

     The factories TermArg, DataObject and ComputationalData does nothing
     but forward the parsing to the next-level factory according to the
     opcode of the next object. With this patch, the invocation sequence
     becomes:

         ByteIndex -> ByteConst

     i.e. ByteIndex directly passes to ByteConst which can parse the next
     opcode.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
d325966612 board_inspector: always defer parsing of method bodies
The current ACPI AML parser can generate incorrect AST if a DSDT/SSDT
satisfies the following:

  1. The body of a method invokes a NameString that is defined later.

  2. Before that method the same NameString is also defined but in an outer
     scope and with a different number of parameter.

Since method bodies hardly define any further symbol that is referenced
outside the method itself, this patch forces the parsing of method bodies
to be deferred to the second pass when all symbols have been declared.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
60920bb905 board_inspector: Access I/O registers on-demand and properly
The current implementation of I/O buffers have the following issues.

  1. I/O buffers are filled with values on creation. This may be fine for
     memory-mapped I/O regions, but could be a problem to port I/O regions
     and indexed I/O regions.

  2. While not commonly seen, it IS witnessed that some devices only allow
     its MMIO registers to be accessed with certain width. Accessing such
     registers with a larger width will not be handled by the device,
     causing SW to get all 1's rather than the actual values in these
     registers.

This patch resolves the issues above as follows:

  1. I/O buffers now do not access any register on creation. Instead, the
     register is accessed only upon requests.

  2. The access width of these registers are followed to ensure that the
     registers are accessed properly.

The classes that represents buffers when interpreting AML is also
refactored to abstract the common code that manages fields within
buffers. The class hierarchy now looks like this:

  BufferBase: Implement methods that registers, reads or writes fields
    Buffer(BufferBase): Implement memory buffer
    StreamIOBuffer(BufferBase): Implement I/Os available via /dev files
    IndexedIOBuffer(BufferBase): Implement I/Os via index/data registers

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
8c63550eb7 board_inspector: interpret DefDivide in DSDT/SSDT
DefDevide is now enountered when interpreting host DSDT/SSDT. This patch
implements the interpretation of the integer division operation.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Junjie Mao
e56eb6238d board_inspector: return from method call invocation on DefReturn
The current implementation of the AML interpreter continues interpreting a
method after meeting a DefReturn object, which is incorrect. This patch
fixes this issue by raising a dedicated exception on return and catching
that exception on the caller side.

Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-08-09 09:05:01 +08:00
Yang,Yu-chu
fec1f87adc config-tools: do not exit when the board inspector runs in hypervisor
While running in a nested environment, such as qemu, parse the board
information should be allowed even it is not in a native environment.

Replace the error with warning message and does not exit the program.

Tracked-On: #6208
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-07-19 10:13:28 +08:00
Yang,Yu-chu
987216fef0 config-tools: add MSI-X capability
Add the MSI-X capability structure nodes under <capability
id="MSI-X"> in board.xml.
Example:
  <capability id="MSI-X">
    <table_size>16</table_size>
    <table_bir>1</table_bir>
    <table_offset>0x1000000</table_offset>
    <pba_bir>1</pba_bir>
    <pba_offset>0x0</pba_offset>
  </capability>

Fix the MSI <count> nodes when there is only one vector.

Tracked-On: #6235
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
2021-07-19 10:00:40 +08:00
Kunhui-Li
e6d447e462 config_tools: update board_inspector to copy RTCT file
1. Remove acpi_template/ehl-crb-b/PTCT and acpi_template/tgl-rvp/PTCT files.
2. Update board_inspector/legacy/acpi.py script to copy RTCT file.

Tracked-On: #6238
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
2021-07-02 13:42:06 +08:00
Kunhui Li
2ce0b38486 doc: update the content about generating board xml
Update the content about getting board xml from native
enviroment in acrn_configuration_tool.rst and README.

Tracked-On: #6134
Signed-off-by: Kunhui Li <kunhuix.li@intel.com>
2021-06-09 17:17:09 -04:00
Kunhui Li
ff2102a5c1 config_tools: replace illegal character with escaped character
For illegal characters, replace original characters with escaped characters in board.xml.

Tracked-On: #6113
Signed-off-by: Kunhui Li <kunhuix.li@intel.com>
2021-06-01 11:28:52 +08:00
Junjie Mao
99f15a27c2 board_inspector/acpiparser: enable parsing RTCT v2
This patch adds support to parse RTCT v2 using the refined board XML
schema. The major changes include:

 - Add the RTCT v2 parser in the acpiparser module. The version of an RTCT
   is detected automatically to choose the right parser.
 - Extract software SRAM capabilities of caches into the board XML.
 - Move the logic that determines the software SRAM base address for the
   pre-launched VM to the static allocator of GPAs.
 - Generate software SRAM related macros into misc_cfg.h when necessary.

Tracked-On: #6020
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-19 08:53:38 +08:00
Yonghua Huang
9facbb43b3 config-tool: rename PSRARM to SSRAM
'psram' and 'PSRAM' are legacy names and replaced
  with 'ssram' and 'SSRAM' respectively.

Tracked-On: #6012
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Shuang Zheng <shuang.zheng@intel.com>
2021-05-17 14:31:42 +08:00
Junjie Mao
0aa899271d board_inspector/extractors: extract device information
This patch extracts information on devices and put them under the
`/acrn-config/devices` node in the board XML.

The generated XML looks like the following:

  <devices>
    <bus type="system">
      <acpi_object>\_SB_</acpi_object>
      <bus id="PNP0A08" type="pci" address="0x0" description="...">
        <vendor>0x8086</vendor>
        <identifier>0x591f</identifier>
        <subsystem_vendor>0x1028</subsystem_vendor>
        <subsystem_identifier>0x07a1</subsystem_identifier>
        <class>0x060000</class>
        <acpi_object>\_SB_.PCI0</acpi_object>
        <resource type="bus_number" min="0x0" max="0x3e" len="0x3f"/>
        <resource type="io_port" min="0x0" max="0xcf7" len="0xcf8"/>
        <resource type="io_port" min="0xcf8" max="0xcf8" len="0x8"/>
        <resource type="io_port" min="0xd00" max="0xffff" len="0xf300"/>
        <resource type="memory" min="0x10000" max="0x1ffff" len="0x0"/>
        <resource type="memory" min="0xa0000" max="0xbffff" len="0x20000"/>
        <resource type="memory" min="0xc0000" max="0xc3fff" len="0x4000"/>
        <resource type="memory" min="0xc4000" max="0xc7fff" len="0x4000"/>
        ...
        <capability id="vendor_specific"/>
        <device address="0x1"> ... </device>
        ...
      <bus>
    <bus>
    <device> ... <device>
  <devices>

The hierarchy of devices are based on the hierarchy of device objects in
the ACPI namespace (which is established by interpreting the ACPI DSDT and
SSDT tables). Typically most device objects are under the predefined
`_SB_` (i.e. System Bus) object under which an object representing the PCI
root complex (`\_SB_.PCI0` in the example above) can be found. The PCI
devices attached to bus 0 are listed as children of the PCI root complex
node.

For each bus or device, the board inspector tries best to parse the
information from both ACPI device objects and PCI configuration space to
extract the following:

- the model (via `_HID` object and PCI vendor ID, device ID and class code),
- assigned resources (via `_CRS` object and PCI BARs),
- capabilities (via the PCI capability list)

v1 -> v2:
 - Fix references to undeclared modules or variables.
 - Make the ACPI extractor advanced and not enabled by default.
 - Extract the secondary I/O and memory-mapped I/O addresses of bridges.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
52ee5827e1 board_inspector/extractors: extract memory layout
This patch extracts information on mapping of available RAM and put them
under the `/acrn-config/memory` node in the board XML. Each range of
available RAM is represented by its start (host physical) address, end
address and size (in byte).

The following is an example of the generated XML.

  <memory>
    <range start="0x0000000000000000" end="0x0000000000057fff" size="360448"/>
    <range start="0x0000000000059000" end="0x000000000009dfff" size="282624"/>
    <range start="0x0000000000100000" end="0x00000000c9ff9fff"
    size="3387924480"/>
    <range start="0x00000000c9ffc000" end="0x00000000d984afff"
    size="260370432"/>
    <range start="0x00000000dbdff000" end="0x00000000dbdfffff" size="4096"/>
    <range start="0x0000000100000000" end="0x000000041dffffff"
    size="13388218368"/>
  </memory>

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
ffe213359c board_inspector/extractors: extract cache topology and capabilities
This patch extracts information on cache topology and capabilities and put
them under the `/acrn-config/caches` node in the board XML in the following
manner.

  <caches>
    <cache level="1" id="0x0" type="1">
      <cache_size>32768</cache_size>
      <line_size>64</line_size>
      <ways>8</ways>
      <sets>64</sets>
      <partitions>1</partitions>
      <self_initializing>1</self_initializing>
      <fully_associative>0</fully_associative>
      <write_back_invalidate>0</write_back_invalidate>
      <cache_inclusiveness>0</cache_inclusiveness>
      <complex_cache_indexing>0</complex_cache_indexing>
      <processors>
        <processor>0x0</processor>
        <processor>0x1</processor>
      </processors>
    </cache>
    <cache level="1" id="0x0" type="2"> ... </cache>
    <cache level="1" id="0x1" type="1"> ... </cache>
    <cache level="1" id="0x1" type="2"> ... </cache>
    ...
    <cache level="2" id="0x0" type="3"> ... </cache>
    <cache level="2" id="0x1" type="3"> ... </cache>
    ...
    <cache level="3" id="0x0" type="3"> ... </cache>
  </caches>

Each cache block is represented by a separate `cache` node identified by
its level, cache ID and type (as reported by CPUID). More information, such
as the size, characteristics and capabilities, are attached as children of
the node.

The current implementation fetches cache information solely from the CPUID
leaf 4H. In the future more cache-related information, such as those in the
ACPI RTCT tables, will be appended here.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
3e3120d342 board_inspector/extractors: extract CPU topology and models
This patch extracts information on CPU topology and capability and put them
under the `/acrn-config/processors` node in the board XML.

The added information can be divided into two categories.

1. The topology of CPUs like the following. Each thread (which is a leaf
   node in the topology) contains its addresses (i.e. CPU ID, APIC ID,
   x2APIC ID) and model identifiers (i.e. family, model, stepping IDs, core
   types and native model ID).

    <die id="0">
      <core id="0x0">
        <thread id="0x0">
          <cpu_id>0</cpu_id>
          <apic_id>0x0</apic_id>
          <x2apic_id>0x0</x2apic_id>
          <family_id>0x6</family_id>
          <model_id>0x9e</model_id>
          <stepping_id>0x9</stepping_id>
          <core_type></core_type>
          <native_model_id></native_model_id>
	</thread>
        <thread id="0x1"> ... </thread>
      </core>
      <core id="0x1">
        <thread id="0x2"> ... </thread>
        <thread id="0x3"> ... </thread>
      </core>
      <core id="0x2">
        <thread id="0x4"> ... </thread>
        <thread id="0x5"> ... </thread>
      </core>
      <core id="0x3">
        <thread id="0x6"> ... </thread>
        <thread id="0x7"> ... </thread>
      </core>
    </die>

2. The CPU models identified by the quadruple (family_id, model_id,
   core_type, native_model_id). Each model is described by its brandstring
   and capabilities, both of which are fetched from CPUID leaves.

    <model description="Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz">
      <family_id>0x6</family_id>
      <model_id>0x9e</model_id>
      <core_type></core_type>
      <native_model_id></native_model_id>
      <capability id="sse3"/>
      <capability id="pclmulqdq"/>
      <capability id="dtes64"/>
      <capability id="monitor"/>
      ...
    </model>

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
4d3a765708 board_inspector/extractors: framework to support extractors
This patch makes the `run.py` enumerate and invoke all extractors (whose
name should be `##-<name>.py` where `##` is a decimal number for ordering)
under the extractors/ directory. Only some helper subroutines are added in
this patch; the actual extractors will be added in the subsequent patches
in this series.

v1 -> v2:
 - Allow an extractor to be classified as advanced by defining the variable
   `advanced` to True. Advanced extractors are not enabled by default and
   can be invoked by passing `--advanced` to the board inspector.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
b3921137c2 board_inspector/smbiosparser: add SMBIOS table parsers
This patch adds a parser of SMBIOS tables. The tables are fetched from
/sys/firmware/dmi/tables on target board. The parser comes from
BITS (https://biosbits.org/) without modifications, except how the raw
SMBIOS tables are read.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
3a395bb342 board_inspector/pcieparser: add PCIe config space parser
This patch adds a parser of PCI-compatible configuration space read from
sysfs. The headers and capability lists are fully parsed, but only a couple
of capabilities are parsed completely. Parsing of additional capabilities
will be added on an on-demand basis.

v1 -> v2:
 - Fix a typo that causes incorrect parsing of BAR types
 - Parse capability structures using from_buffer_copy instead of
   from_address

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
0215603812 board_inspector/acpiparser: add DSDT/SSDT parser
This patch adds a parser and interpreter of ACPI DSDT/SSDT tables in
AML (ACPI Machine Language) in order to understand the complete device
layout and resource allocation.

Kindly note that the interpreter is still experimental and not yet
complete.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
6276e5759a board_inspector/memmapparser: add parser of e820 memory maps
This patch adds a parser of the physical E820 memory maps fetched from
/sys/firmware/memmap.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
598be99dc2 board_inspector/cpuparser: add CPUID parsers
This patch adds a parser of CPU identification information reported by the
CPUID instruction.

The framework is based on the CPUID parsing facilities in
BITS (https://biosbits.org/), but with the following changes.

1. The CPUID data is fetched by executing the `cpuid` utility, rather than
   executing the `cpuid` instruction. This avoids introducing any
   additional library or Python/C extension and gets a CPUID leaf on all
   physical cores in one shot.

2. Parsers of CPUID leaves 0x10, 0x1A and 0x1F are added. New fields in
   existing leaves are also added.

3. A wrapper function, named `parse_cpuid`, is added as the single API that
   allows other modules to get an arbitrary CPUID leaf or subleaf.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
05c738a480 board_inspector/lib: fix compatibility issues in unpack.py
Starting from Python 3.0 the following changes to the language are
effective:

1. The integer types `int` and `long` have been unified as `int`. See
   `https://www.python.org/dev/peps/pep-0237/` for details.
2. The `.iterkeys` method is removed from the `dict` class. See
   `https://www.python.org/dev/peps/pep-3106/` for details.

This patch updates `unpack.py`, originally from BITS, so that it can be
used in Python 3.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
e6e61a4979 board_inspector/legacy: fix a copy destination error
Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00
Junjie Mao
bd4ddbd31d board-inspector: reorganize the scripts
This patch reorganize the files of the board inspector as follows.

1. Rename the directory name from `target` to `board_inspector`, in order to
   align with the name used in ACRN documentation.
2. Move the scripts that generate the current board XML into the `legacy`
   sub-directory. The legacy nodes will be removed after transitioning to the
   new board XML schema completely,
3. Add the main script `cli.py` which is the command line interface of the board
   inspector.

v1 -> v2:
 - Rename `run.py` to `cli.py`.

Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2021-05-16 19:02:00 +08:00