Some ACRN docs (in particular the HLD) has content nested more than the
4 levels shown in the sidebar navigation. So when looking at those
documents, it's hard to get to next chapter. Bring back the
previous/next links to fix this situation.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Add two Kconfig pSRAM config:
one for whether to enable the pSRAM on the platfrom or not;
another for if the pSRAM is enabled on the platform whether to enable
the pSRAM in the pre-launched RTVM.
If we enable the pSRAM on the platform, we should remove the pSRAM EPT
mapping from the SOS to prevent it could flush the pSRAM cache.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
1.Modified the virtual e820 table for pre-launched VM. We added a
segment for pSRAM, and thus lowmem RAM is split into two parts.
Logics are added to deal with the split.
2.Added EPT mapping of pSRAM segment for pre-launched RTVM if it
uses pSRAM.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
dm: pSRAM: added a command line parameter "--psram" to enable pSRAM
support for post-launched RTVM
Added "--psram" in DM command line to enable pSRAM support for
post-launched RTVM
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
pSRAM memory should be cachable. However, it's not a RAM or a normal MMIO,
so we can't use the an exist API to do the EPT mapping and set the EPT cache
attribute to WB for it. Now we assume that SOS must assign the PSRAM area as
a whole and as a separate memory region whose base address is PSRAM_BASE_HPA.
If the hpa of the EPT mapping region is equal to PSRAM_BASE_HPA, we think this
EPT mapping is for pSRAM, we change the EPT mapping cache attribute to WB.
And fix a minor bug when SOS trap out to emulate wbinvd when pSRAM is enabled.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
dm: modify vE820 to adapt to pSRAM for post-launched RTVM
When pSRAM is enabled for post-launched RTVM, we add a segment in vE820 for
pSRAM, and therefore the lowmem RAM will be split into part1 and part2.
Also, code of post vE820 initialization is refined
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
dm: vptct: add vPTCT for post-launched RTVM
We added vPTCT support for post-launched RTVM:
1. Added a function create_and_inject_vptct. Currently, we
pass-through the whole pSRAM to one RTVM, so we will also pass-
through the PTCT to the very same RTVM. This function will
read the native PTCT from SOS and inject it into post-
launched VM's vACPI.
2. Added some definitions for vPTCT.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Use ept_flush_leaf_page to emulate guest WBINVD when PTCM is enabled and skip
the pSRAM in ept_flush_leaf_page.
TODO: do we need to emulate WBINVD in HV side.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Rename hv_access_memory_region_update to ppt_clear_user_bit to
verb + object style.
Tracked-On: #5330
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Temporarily remove NX bit of PTCM binary in pagetable during pSRAM
initialization:
1.added a function ppt_set_nx_bit to temporarily remove/restore the NX bit of
a given area in pagetable.
2.Temporarily remove NX bit of PTCM binary during pSRAM initialization to make
PTCM codes executable.
3. TODO: We may use SMP call to flush TLB and do pSRAM initilization on APs.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
The added parse_ptct function will parse native ACPI PTCT table to
acquire information like pSRAM location/size/level and PTCM location,
and save them.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
1.We added a function init_psram to initialize pSRAM as well as some definitions.
Both AP and BSP shall call init_psram to make sure pSRAM is initialized, which is
required by PTCM.
BSP:
To parse PTCT and find the entry of PTCM command function, then call PTCM ABI.
AP:
Wait until BSP has done the parsing work, then call the PTCM ABI.
Synchronization of AP and BSP is ensured, both inside and outside PTCM.
2. Added calls of init_psram in init_pcpu_post to initialize pSRAM in HV booting phase
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
According 11.5.1 Cache Control Registers and Bits, Intel SDM Vol 3,
change CR0.CD will not flush cache to insure memory coherency. So
it's not needed to call wbinvd to flush cache in ACRN Hypervisor.
That's what the guest should do.
Tracked-On: #5330
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Improve the legacy vuart code. The legacy vuart insert the declaration
without checking if it's enabled. Refined the logic that if the legacy
is disabled, simply do not declare.
Tracked-On: #5425
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
generic
Add console and communication vuarts to:
misc/vm_configs/xmls/config-xmls/generic/<scenario>.xml
misc/vm_configs/xmls/config-xmls/template/<scenario>.xml
Tracked-On: #5425
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Check if the scenario xmls configure pci vuarts properly
Sanity check of scenario xml:
1. check the format of console and communication vuarts
2. legacy vuart0 and console vuart0 cannot be eabled at the same time
3. legacy vuart1 and communication vuart1 cannot be enabled at the
same time
4. Any vuart should not connect to any type of vuart0
5. Every vuart can only connect to enabled vuart<idx> (idx > 0)
Tracked-On: #5425
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
Add pci vuart to launch script if the pci vuart is enabled.
Add pci vuart sanity check for launch script:
- vuart0 and console vuart cannot be enabled at the same time
- vuart1 cannot be eabled if the legacy vuart 1 is enabled
Tracked-On: #5425
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
- Find unused bdf for SOS and pre-launched VM's pci vuart if it's
enabled
- The vuart cannot detect the function difference, find the unused vbdf
based on "dev" increment
Tracked-On: #5425
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Allocate unused vbar for pci based vuarts when the it's enabled for SOS
and/or pre-launched VMs.
- vuart needs 2 bar, both are 4k size
- for SOS, find unused vbar in the range which is assigned to pci host
bridge. The allocated vbar cannot have confilicts with any existing pci devices
- for pre-launched VMs, find unused vbar in the range 0x80000000 to
0xfffffff. The alloacted vbar cannot have confilicts with any
passthrough devices and mmio
Tracked-On: #5425
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Preparing for upgrading to newer versions of doc building tools
including sphing, doxygen, breathe, docutils, etc. This PR's changes
still work find with the older tool versions, but should eliminate
issues found while moving to newer tool versions (later).
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
when fix the issue of _PM_SystemS5 with life_mngr fail,
the vuart1(tty) item was devided into two parts, the last
part "/dev/tty*" which need to get will be added to the
end, so it should be handled singly, but it will be added
to other item too, such as vuart1(pty).
Tracked-On:#5366
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
cleanup vpci structure when shutdown_vm to avoid use uninitialized data
after reboot.
Tracked-On: #4958
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Add cteate method for vmcs9900 vdev in hypercalls.
The destroy method of ivshmem is also suitable for other emulated vdev,
move it into hcall_destroy_vdev() for all emulated vdevs
Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
If acrn-dm create pci vuart with
'-s,<slot>,uart,vuart_idx:<value>', then acrn-dm will not
create pci uart at DM land, but create an vuart-pci virtual device
at HV land.
When create a HV land vuart-pci vdev, user must specify its vuart id.
Which is defined in vm_config, is the acrn_vm_pci_dev_config.vuart_idx
Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
if vuart type is pci-vuart, then use MSI interrupt
split vuart_toggle_intr() control flow into vuart_trigger_level_intr() &
trigger_vmcs9900_msix(), because MSI is edge triggered, no deassertion
operation. Only trigger MSI for pci-vuart when assert interrupt.
Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
support pci-vuart type, and refine:
1.Rename init_vuart() to init_legacy_vuarts(), only init PIO type.
2.Rename deinit_vuart() to deinit_legacy_vuarts(), only deinit PIO type.
3.Move io handler code out of setup_vuart(), into init_legacy_vuarts()
4.add init_pci_vuart(), deinit_pci_vuart, for one pci vuart vdev.
and some change from requirement:
1.Increase MAX_VUART_NUM_PER_VM to 8.
Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
The vuart_read()/vuart_write() are coupled with PIO vuart type. Move
the non-type related code into vuart_read_reg()/vuart_write_reg(), so
that we can re-use them to handle MMIO request of pci-vuart type.
Tracked-On: #5394
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Multiple devices could be nested under the same range. Skip remove if
the device is removed already
Tracked-On: #5437
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Changes:
1. assign 3 CPUs for WaaG on hybrid_rt scenario;
2. Passthrough NVME@9:0.0 for VM0 on hybrid_rt scenario;
3. Change rootfs from partition2 to partition3;
Tracked-On: #5390
Signed-off-by: Liang Yi <yi.liang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Support enable ivshmem for SOS. Insert the ivshmem device information if
it is enabled.
1. get ivshmem vbar based:
- vbar[0] is size 0x100
- vbar[2] is specified MB size
2. get vbdf for ivshmem device
Tracked-On: #5426
Signed-off-by: Yang,Yu-chu <yu-chu,yang>
Add following to default output scenarios vm_configurations.c:
- pci_dev_num
- pci_devs = sos_pci_devs
Both was defineded in CONFIG_SOS_VM.
Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
- Refactor pci_dev_c.py to insert devices information per VMs
- Add function to get unused vbdf form bus:dev.func 00:00.0 to 00:1F.7
Add pci devices variables to vm_configurations.c
- To pass the pci vuart information form tool, add pci_dev_num and
pci_devs initialization by tool
- Change CONFIG_SOS_VM in hypervisor/include/arch/x86/vm_config.h to
compromise vm_configurations.c
Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Allocate unused vbar for SOS and pre-launched VMs.
- For SOS, find unused vbar in the range which is assigned to pci host
bridge. The allocated vbar cannot have confilicts with any existing pci devices
- For pre-launched VMs, find unused vbar in the range 0x80000000 to
0xfffffff. The alloacted vbar cannot have confilicts with any
passthrough devices and mmio.
Tracked-On: #5426
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
automatically get PTCT table from native environment for the usage
of pre-launched VMs.
Tracked-On: #5418
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
