Commit Graph

  • 445eb573a6 hv: riscv: add uart init after paging hangliu1 2025-10-17 16:46:17 +08:00
  • cbab9cbab8 hv: multiarch: add hva2hpa_early/hpa2hva_early to common hangliu1 2025-10-16 14:21:29 +08:00
  • 8615271e45 hv: multiarch: move shell_dump_host_mem to common hangliu1 2025-10-15 16:52:45 +08:00
  • a436f72493 hv: riscv: add access usr memory interface hangliu1 2025-09-26 15:03:10 +08:00
  • 3041b2fd33 hv:riscv: add memory initizalization hangliu1 2025-10-15 16:01:46 +08:00
  • 47ed22bef8 hv: riscv: add check for other memory mode hangliu1 2025-10-15 15:55:05 +08:00
  • a6e0cba89b hv: riscv: add hypervisor memory mapping hangliu1 2025-10-15 15:38:28 +08:00
  • b50f1eb199 hv: riscv: get device mmio parameter hangliu1 2025-10-17 14:27:55 +08:00
  • 3d57581eb0 hv: riscv: page number calculate hangliu1 2025-10-15 15:11:34 +08:00
  • 52e7919d9f hv: riscv: add riscv memory interface hangliu1 2025-10-15 14:46:35 +08:00
  • cf73187528 hv: multiarch: add arch specific set_pgentry hangliu1 2025-10-14 10:45:01 +08:00
  • 1ec40cd62f hv: multiarch: replace memset with sanitize_pte hangliu1 2025-10-13 17:02:11 +08:00
  • 8ba4890677 hv: x86: modify Makefile to enable compile hangliu1 2025-09-30 15:00:32 +08:00
  • 5dcf336ab3 hv: x86: move two functions back to x86 hangliu1 2025-09-30 10:56:29 +08:00
  • 9bedd785e3 hv:multiarch: move round_pde_down/round_pde_up to common hangliu1 2025-09-30 10:39:48 +08:00
  • 5cc6694eab hv: multiarch: move page table entry function hangliu1 2025-10-13 15:17:19 +08:00
  • 8be20c690b hv: multiarch: change to common page level hangliu1 2025-10-13 13:56:11 +08:00
  • 6748f72d1b hv:multiarch: change main macro name hangliu1 2025-09-29 18:33:06 +08:00
  • c421a9557b hv:multiarch: move main memory interface to common hangliu1 2025-09-29 17:20:23 +08:00
  • c911c3d38e hv: multiarch: move sanitize interface to common hangliu1 2025-10-13 11:59:57 +08:00
  • bab6e4010c hv: multiarch: move set_pgentry/get_pgentry hangliu1 2025-10-13 11:48:08 +08:00
  • 2e4f5e79b7 hv:multiarch: move main memory structure to common hangliu1 2025-10-13 10:29:59 +08:00
  • 2ab068400b hv: multiarch: move some function to common hangliu1 2025-09-28 08:00:58 +08:00
  • 2470e7f064 dump: add exception dump for risc-v Fei Li 2025-10-16 00:38:56 +08:00
  • 274eec4ec2 debug: enable console and shell for risc-v Fei Li 2025-09-26 21:51:03 +08:00
  • 712568f949 shell: split arch special code Fei Li 2025-09-25 22:12:35 +08:00
  • b26ef37519 log: move print_hv_banner as common Fei Li 2025-09-25 22:31:29 +08:00
  • f687574a58 vuart: add dummy vuart for risc-v Fei Li 2025-09-23 23:57:45 +08:00
  • df5a5f2657 vuart_config: separate vuart config from vm config file Fei Li 2025-09-23 19:29:14 +08:00
  • f3ab8291f4 intx: abstruct intx inject for VM Fei Li 2025-09-23 21:16:56 +08:00
  • ab32f6c033 config: add VMCS9900 CONFIG Fei Li 2025-09-23 22:26:12 +08:00
  • eea9a21796 vuart: move x86 special code into x86 Fei Li 2025-09-23 19:19:42 +08:00
  • b82a6fea8b smap: risc-v should implement enable and disable APIs Fei Li 2025-09-23 23:21:04 +08:00
  • 0774a517a0 mmu: add dummy APIs for risc-v Fei Li 2025-09-23 22:07:48 +08:00
  • 0a13d0c7a4 uart16550: add a CONFIG to enable PCI uart16550 Fei Li 2025-09-23 22:17:22 +08:00
  • 83d56e0edb vm: add necessary dummy APIs Fei Li 2025-09-23 21:06:57 +08:00
  • ac1c79641e cmdline: move cmdline to x86 Fei Li 2025-09-23 22:49:56 +08:00
  • 9d95a6adb6 hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore Shiqing Gao 2025-10-13 11:04:04 +08:00
  • 23b9cacbd2 misc: Add scenario file and change board file for QEMU virt platform Xue Bosheng 2025-10-10 08:42:07 +08:00
  • 3449b62dfb hv: risc-v: use tp register directly for arch_get_pcpu_id Jian Jun Chen 2025-10-10 13:31:05 +08:00
  • 0a8eb09454 hv: riscv: fix the implementation of send_ipi Jian Jun Chen 2025-09-25 09:02:59 +08:00
  • bd0e83fa5f io: add risc-v mmio read and write APIs with memory order Haicheng Li 2025-09-09 15:18:47 +08:00
  • b6854ac4bd io: move common IO operation out of arch Fei Li 2025-09-09 15:00:36 +08:00
  • 763c6684e3 misc: Remove AVAILABLE_IRQ_INFO values from RISC-V board XML Wei6 Zhang 2025-10-09 14:03:43 +08:00
  • a4a1c573e5 misc: Add RISC-V board configuration for QEMU virt platform Wei6 Zhang 2025-10-09 09:59:39 +08:00
  • 5f59c02a81 hv: init sched and run idle thread in risicv AP initialization Xue Bosheng 2025-09-19 20:51:52 +08:00
  • 82ca737400 hv: move schedule source code out of x86 macro Xue Bosheng 2025-09-08 10:01:37 +08:00
  • 69f7c14191 hv: move trace.c out of x86 Xue Bosheng 2025-09-25 16:23:06 +08:00
  • 034cccb7a4 hv: fix build issue in schedule module Xue Bosheng 2025-09-24 10:14:12 +08:00
  • 6de0e4b681 hv: add dummy function for riscv support Xue Bosheng 2025-09-24 03:19:24 +08:00
  • fb82f3b931 hv: implement cpu dead and cpu idle for riscv Haicheng Li 2025-09-02 10:35:25 +08:00
  • 4875a4a919 hv: refine cpu dead and cpu idle implementation Xue Bosheng 2025-08-26 16:00:48 +08:00
  • ca63f62af3 hv: move run_idle_thread to schedule file Xue Bosheng 2025-08-26 15:36:50 +08:00
  • 65927b4f03 hv: add arch_switch_to support for riscv Haicheng Li 2025-08-22 14:40:57 +08:00
  • d8970404e3 hv: move stack_frame out of vcpu Xue Bosheng 2025-09-02 16:11:05 +08:00
  • e278b38ec4 hv: move percpu delivery mode and idle mode from common to x86 Xue Bosheng 2025-08-25 20:05:23 +08:00
  • b03dc25119 hv: add arch_send_reschedule_request implementation for riscv support Haicheng Li 2025-08-25 14:23:24 +08:00
  • 974e8c63ea hv: refine make_reschedule_request in schedule module Xue Bosheng 2025-09-28 19:45:59 +08:00
  • 6abe2e950c hv: riscv: build timer and softirq Yi Y Sun 2025-09-25 15:23:39 +08:00
  • 64055b49be hv: riscv: initialize timer Yi Y Sun 2025-09-25 15:21:25 +08:00
  • ca778139e6 hv: abstract IRQ related macros Shiqing Gao 2025-09-22 16:39:59 +08:00
  • 86b25ea9ac hv: riscv: fix strict-aliasing error in local_irq_save Shiqing Gao 2025-09-25 14:34:01 +08:00
  • 395a7c44bc hv: riscv: fix local_irq_save to only clear SIE bit Shiqing Gao 2025-09-22 16:39:12 +08:00
  • fc495b946a hv: riscv: irq: add interrupt initialization and handlers Haicheng Li 2025-09-12 11:27:57 +08:00
  • 0fc843de84 hv: riscv: irq: add misc IRQ-dependent helpers Haicheng Li 2025-09-12 11:24:53 +08:00
  • 6276763cd5 hv: riscv: implement cpu_ctx_save and cpu_ctx_restore Haicheng Li 2025-09-11 16:59:10 +08:00
  • 5803232d83 hv: enable acrnlog in release builds Jiaqing Zhao 2024-12-06 05:40:37 +00:00
  • 015a97bfa8 hv: move sbuf_share_setup() and sbuf_reset() to common Jiaqing Zhao 2024-12-11 06:57:45 +00:00
  • 2312472b1c hv: make acrntrace a common feature Jiaqing Zhao 2024-12-02 06:31:37 +00:00
  • c103ef655d hv: riscv: specifiy -fpie / -fno-pie explicitly Jian Jun Chen 2025-09-11 14:08:42 +08:00
  • 17c9a4d7be hv: riscv: implement basic logic to bring up APs Jian Jun Chen 2025-09-10 15:21:36 +08:00
  • 43d6036694 hv: multi-arch: move SP_BOTTOM_MAGIC to common/cpu.h Jian Jun Chen 2025-09-17 09:05:06 +08:00
  • 0e6e6ca502 hv: riscv: add arch_asm_pause implementation Jian Jun Chen 2025-09-10 15:42:47 +08:00
  • 8d218c0b37 hv: multi-arch: move asm_pause to common Jian Jun Chen 2025-09-12 09:41:57 +08:00
  • 1949c0b52f hv: riscv: add get/set_pcpu_id and start_pcpus implementation Jian Jun Chen 2025-09-09 15:35:48 +08:00
  • 9d6ec75628 [FIXME] hv: riscv: add a stub do_logmsg for build Jian Jun Chen 2025-09-10 15:56:42 +08:00
  • 033bb2e347 [FIXME] hv: riscv: add build dependencies temporarily Jian Jun Chen 2025-09-10 14:19:32 +08:00
  • e5831fec1e hv: multi-arch: abstract some pcpu related interfaces and macros Jian Jun Chen 2025-09-09 15:09:38 +08:00
  • b4092965a4 hv: riscv: add SBI HSM HART_START interface Haicheng Li 2025-09-09 15:07:06 +08:00
  • 95a13b334f hv: enable build of common/{delay.c,ticks.c} Jian Jun Chen 2025-09-19 15:10:04 +08:00
  • bc90c7bc41 dm: correct wrong input parameter when printing get edid error message Xue Bosheng 2025-09-15 09:24:39 +08:00
  • 8a521fe47e hv: add common library to risc-v build Haoyu Tang 2025-09-16 17:10:23 +08:00
  • 5c1726a78f hv: fix the bug in common library sprintf.c Haoyu Tang 2025-09-19 15:06:27 +08:00
  • bb9817b866 hv: multi-arch add RISC-V bits library implementation Haicheng Li 2025-09-07 10:50:00 +08:00
  • a226b5f0ec hv: multi-arch reconstruct bits library Haoyu Tang 2025-09-05 11:34:02 +08:00
  • 090aaf4c34 hv: multi-arch add RISC-V barrier library implementation Haicheng Li 2025-09-07 11:27:56 +08:00
  • f67a437e5a hv: multi-arch construct barrier library Haoyu Tang 2025-09-06 20:46:00 +08:00
  • 47944d975d hv: multi-arch add RISC-V atomic library implementation Haicheng Li 2025-09-07 11:06:21 +08:00
  • 286a7557bc hv: multi-arch reconstruct atomic library Haoyu Tang 2025-09-05 14:16:09 +08:00
  • d22e21f484 hv: multi-arch add RISC-V spinlock library implementation Haicheng Li 2025-09-09 11:00:26 +08:00
  • a7239d1268 [FIXME] hv: risc-v add denpended implementation in cpu.h Haicheng Li 2025-09-15 15:12:42 +08:00
  • 3a74e62ec4 hv: multi-arch reconstruct spinlock library Haoyu Tang 2025-09-09 10:51:02 +08:00
  • 052a58d87d hv: multiarch: riscv: add two cpu interfaces Haicheng Li 2025-09-09 14:43:50 -04:00
  • a72bd5e076 hv: multiarch: abstract pcpu related data from x86 hangliu1 2025-09-09 14:39:50 -04:00
  • 0cd5567140 hv:multiarch:riscv: add dummy function hangliu1 2025-09-10 14:31:38 +08:00
  • 41f04b4e7a HV: abstract percpu structure from x86 arch hangliu1 2025-09-08 20:25:25 -04:00
  • 286c383b53 hv: multiarch: riscv: add dummy header for riscv hangliu1 2025-09-10 13:26:13 +08:00
  • b5306f2a74 enable common code compile hangliu1 2025-09-10 10:52:44 +08:00
  • 037c479221 hv: ipi: drop arch_ prefix from IPI functions Shiqing Gao 2025-09-19 10:01:45 +08:00
  • cf5860f369 risc-v: handle timer interrupt Haicheng Li 2025-09-03 12:27:54 +08:00