mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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49adb858e7
This patch integrates RISC-V with the common IRQ framework: - Register software and timer interrupt handlers via request_irq(). - Refine dispatch_interrupt() to handle interrupts via do_irq(). Tracked-On: #8845 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Wang Yu1 <yu1.wang@intel.com>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
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* Copyright (C) 2023-2024 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <softirq.h>
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#include <timer.h>
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#include <irq.h>
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#include <asm/sbi.h>
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#include <asm/qemu.h>
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#include <asm/cpu.h>
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#include <asm/csr.h>
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#include <asm/trap.h>
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#define HOST_CPUFREQ 10000000
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#define STOP_TIMER 0xFFFFFFFFFFFFFFFF
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static void timer_irq_handler(__unused uint32_t irq, __unused void *data)
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{
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arch_set_timer_count(STOP_TIMER);
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fire_softirq(SOFTIRQ_TIMER);
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}
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void arch_init_timer(void)
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{
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uint32_t acrn_irq;
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if (get_pcpu_id() == BSP_CPU_ID) {
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acrn_irq = riscv_domain_get_acrn_irq(RISCV_IRQD_CPU, TRAP_CAUSE_IRQ_S_TIMER);
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if ((acrn_irq == IRQ_INVALID) || ((request_irq(acrn_irq, timer_irq_handler, NULL, IRQF_NONE) < 0))) {
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pr_err("Timer IRQ setup failed \n");
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}
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}
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}
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/* FIXME:
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* Such short arch_xxx function need be moved into header file with
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* static inline prefix.
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*/
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uint64_t arch_cpu_ticks(void)
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{
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uint64_t tick;
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asm volatile (
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"rdtime %0":"=r"(tick):: "memory");
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return tick;
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}
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uint32_t arch_cpu_tickrate(void)
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{
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return HOST_CPUFREQ / 1000;
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}
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void arch_set_timer_count(uint64_t timeout)
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{
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#ifdef CONFIG_SSTC
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cpu_csr_write(CSR_STIMECMP, timeout);
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#else
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sbi_set_timer(timeout);
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#endif
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}
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