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acrn-hypervisor/hypervisor/arch/x86
Shuo A Liu 025df6d44c hv: use SELF IPI Register for self IPI in X2APIC mode
According to SDM 10.12.11, we can know this register is dedicated to the
purpose of sending self-IPIs with the intent of enabling a highly
optimized path for sending self-IPIs. Also sending the IPI via the Self
Interrupt Register ensures that interrupt is delivered to the processor
core. Specifically completion of the WRMSR instruction to the SELF IPI
register implies that the interrupt has been logged into the IRR.

Tracked-On: #4937
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-06-28 10:33:22 +08:00
..
2020-06-08 13:30:04 +08:00
2020-06-19 16:13:20 +08:00
2020-05-08 08:50:13 +08:00
2020-06-19 16:13:20 +08:00