acrn-hypervisor/hypervisor/arch/x86
Xiangyang Wu 13d354e7a6 HV:treewide:Update return type for bit operations fls and clz
Change the return type of function fls and clz as uint16_t;
When the input is zero, INVALID_BIT_INDEX is returned;
Update temporary variable type and return value check of caller
when it call fls or clz;
When input value is zero, clz returns 32 directly.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER;
        Add type conversion as needed;
        Add "U/UL" for constant value as needed;
        Codeing style fixing.
V2-->V3:
       Use type conversion to remove side effect of
       the variable which stores fls/clz return value;
       fls return INVALID_BIT_INDEX directly when the
       input value is zero.
V3-->v4:
       Clean up comments for fls.

Note: For instruction "bsrl", destination register value
      is undefined when source register value is zero.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 15:11:22 +08:00
..
configs HV: config: add Kconfig and defconfigs for sbl & uefi 2018-06-08 17:21:13 +08:00
debug HV: further cleanup of header inclusions 2018-05-25 10:45:56 +08:00
guest HV:treewide:Update return type for bit operations fls and clz 2018-07-02 15:11:22 +08:00
assign.c HV: treewide: drop debug-only helpers in release build 2018-07-02 14:35:39 +08:00
cpu_primary.S init: separate init function based on different stack 2018-06-25 17:29:11 +08:00
cpu_state_tbl.c HV:x86:fix "expression is not Boolean" 2018-06-20 14:19:47 +08:00
cpu.c HV:change the cpu state to enum type 2018-07-02 11:22:48 +08:00
cpuid.c HV: cpu: convert hexadecimals used in bitops to unsigned 2018-06-21 13:12:39 +08:00
ept.c HV: Make all trace event prefix consist with TRACE 2018-07-02 10:46:41 +08:00
gdt.c HV: mmu: convert hexadecimals used in bitops to unsigned 2018-06-21 13:12:39 +08:00
idt.S license: Replace license text with SPDX tag 2018-06-01 10:43:06 +08:00
io.c HV: Make all trace event prefix consist with TRACE 2018-07-02 10:46:41 +08:00
ioapic.c HV: treewide: drop debug-only helpers in release build 2018-07-02 14:35:39 +08:00
irq.c HV: treewide: drop debug-only helpers in release build 2018-07-02 14:35:39 +08:00
Kconfig HV: correct loglevel definitions and default values 2018-06-20 13:23:46 +08:00
lapic.c hv:merge struct lapic and lapic_regs to lapic_regs 2018-07-02 10:49:14 +08:00
mmu.c HV:transfer page_table_type type 2018-07-02 10:47:01 +08:00
mtrr.c HV: add MTRR capability check when CPU boot 2018-06-29 00:50:01 +08:00
notify.c HV: treewide: enforce unsignedness of pcpu_id 2018-06-21 16:59:21 +08:00
pm.c hv: trap vm0 write/read pm1a/pm1b registers 2018-06-29 00:50:01 +08:00
retpoline-thunk.S license: Replace license text with SPDX tag 2018-06-01 10:43:06 +08:00
softirq.c Rename phy_cpu_num as phys_cpu_num 2018-06-22 16:12:52 +08:00
timer.c Rename phy_cpu_num as phys_cpu_num 2018-06-22 16:12:52 +08:00
trampoline.S init: separate init function based on different stack 2018-06-25 17:29:11 +08:00
trusty.c hv: add context->vmx_ia32_pat to save and restore VMCS 2018-07-02 12:33:06 +08:00
virq.c HV: Make all trace event prefix consist with TRACE 2018-07-02 10:46:41 +08:00
vmexit.c HV: Make all trace event prefix consist with TRACE 2018-07-02 10:46:41 +08:00
vmx_asm.S hv: cpu_context is not only used by guest. 2018-06-25 17:29:45 +08:00
vmx.c hv: emulate CR0.CD and CR0.NW 2018-07-02 12:33:06 +08:00
vtd.c modified the lapic_id type to uint8_t 2018-06-29 13:16:02 +08:00
wakeup.S hv: add enter_s3 2018-06-29 00:50:01 +08:00