mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-01 11:55:25 +00:00
2abd8b34ef
VT-d shares the EPT tables as the second level translation tables. For the IOMMUs that don't support page-walk coherecy, cpu cache should be flushed for the IOMMU EPT entries that are modified. For the current implementation, EPT tables for translating from GPA to HPA for EPT/IOMMU are not modified after VM is created, so cpu cache invlidation is done once per VM before starting execution of VM. However, this may be changed, runtime EPT modification is possible. When cpu cache of EPT entries is invalidated when modification, there is no need invalidate cpu cache globally per VM. This patch exports iommu_flush_cache for EPT entry cache invlidation operations. - IOMMUs share the same copy of EPT table, cpu cache should be flushed if any of the IOMMU active doesn't support page-walk coherency. - In the context of ACRN, GPA to HPA mapping relationship is not changed after VM created, skip flushing iotlb to avoid potential performance penalty. Tracked-On: #3607 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Anthony Xu <anthony.xu@intel.com> |
||
|---|---|---|
| .. | ||
| boot | ||
| guest | ||
| lib | ||
| apicreg.h | ||
| board.h | ||
| cat.h | ||
| cpu_caps.h | ||
| cpu.h | ||
| cpufeatures.h | ||
| cpuid.h | ||
| default_acpi_info.h | ||
| e820.h | ||
| gdt.h | ||
| host_pm.h | ||
| idt.h | ||
| init.h | ||
| io.h | ||
| ioapic.h | ||
| irq.h | ||
| lapic.h | ||
| mmu.h | ||
| msr.h | ||
| multiboot.h | ||
| page.h | ||
| pci_dev.h | ||
| per_cpu.h | ||
| pgtable.h | ||
| security.h | ||
| seed.h | ||
| sgx.h | ||
| timer.h | ||
| trampoline.h | ||
| vm_config.h | ||
| vmx.h | ||
| vtd.h | ||
| zeropage.h | ||