Vijay Dhanraj b8a021d658 HV: split L2 and L3 cache resource MSR ... Upcoming intel platforms can support both L2 and L3 but our current code only supports either L2 or L3 CAT. So split the MSRs so that we can support allocation for both L2 and L3. This patch does the following, 1. splits programming of L2 and L3 cache resource based on the resource ID. 2. Replace generic platform_clos_array struct with resource specific struct in all the existing board.c files. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2020-02-27 10:44:07 +08:00
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board.c	HV: split L2 and L3 cache resource MSR	2020-02-27 10:44:07 +08:00
misc_cfg.h	hv: pci: add hide pci devices configuration for apl-up2	2020-01-07 16:05:30 +08:00
pci_devices.h	HV: add generic board config	2019-04-29 15:25:25 +08:00
ve820.c	HV: add generic board config	2019-04-29 15:25:25 +08:00