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b8a021d658
Upcoming intel platforms can support both L2 and L3 but our current code only supports either L2 or L3 CAT. So split the MSRs so that we can support allocation for both L2 and L3. This patch does the following, 1. splits programming of L2 and L3 cache resource based on the resource ID. 2. Replace generic platform_clos_array struct with resource specific struct in all the existing board.c files. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
48 lines
1012 B
C
48 lines
1012 B
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <board.h>
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#include <msr.h>
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#include <vtd.h>
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#include <pci.h>
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#ifndef CONFIG_ACPI_PARSE_ENABLED
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#error "DMAR info is not available, please set ACPI_PARSE_ENABLED to y in Kconfig. \
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Or use acrn-config tool to generate platform DMAR info."
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#endif
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struct dmar_info plat_dmar_info;
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struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
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struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM] = {
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_BASE,
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},
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_BASE + 1U,
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},
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_BASE + 2U,
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},
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{
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.clos_mask = 0xff,
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.msr_index = MSR_IA32_L2_MASK_BASE + 3U,
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},
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};
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const struct cpu_state_table board_cpu_state_tbl;
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const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {
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{
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.bits.b = 0x0,
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.bits.d = 0xd,
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.bits.f = 0x0,
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},
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};
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