Zide Chen bb47184f3c hv: fix enable_msr_interception() function ...

Fixed three MISRA-C violations:
11S: No brackets to loop body
7C: Procedure has more than one exit point.
8D: DD data flow anomalies found.
  initialize read_map and write_map in the declaration statements.

Fixed one bug:
Use "msr <= 0x1FFFU" instead of "msr < 0x1FFFU" because 0x1FFF is a valid MSR
bitmap address.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>

2018-12-20 18:46:19 +08:00

..

guest.c

hv: enable SMAP in hypervisor

2018-12-14 15:24:26 +08:00

instr_emul.c

hv: enable SMAP in hypervisor

2018-12-14 15:24:26 +08:00

instr_emul.h

hv: use int32_t replace int

2018-12-12 13:08:10 +08:00

pm.c

HV: modularization to refine pm related code.

2018-12-19 13:02:09 +08:00

ucode.c

hv: refine coding style for ucode.c

2018-12-19 09:44:42 +08:00

vcpu.c

Make ibrs_type as internal variable

2018-12-19 09:07:14 +08:00

vcpuid.c

modulization: move virtual cpuid stuff into guest dir

2018-12-13 09:08:02 +08:00

vlapic_priv.h

hv: self-IPI APIC register in x2APIC mode of guest vLAPIC

2018-11-02 13:48:43 +08:00

vlapic.c

hv: use int32_t replace int

2018-12-12 13:08:10 +08:00

vm.c

hv:refine prepare_vm0 api

2018-12-19 09:16:37 +08:00

vmcall.c

hv: use int32_t replace int

2018-12-12 13:08:10 +08:00

vmsr.c

hv: fix enable_msr_interception() function

2018-12-20 18:46:19 +08:00

vmtrr.c

hv: refine a few functions to only one exit point

2018-12-19 09:17:30 +08:00