Commit Graph

4969 Commits

Author SHA1 Message Date
Mingqiang Chi
2b648476cc life_mngr:fix resend shutdown cmd fail
1) fix a bug,resend shutdown cmd only send one character
2) move out accept routine from while loop, let this thread
   can read data from acrn-dm continuously.

Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Yuhong Tao <yuhong.tao@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
2020-04-16 22:04:53 +08:00
Mingqiang Chi
90b8d844d0 dm:refine pm_vuart code
1) remove state machine
2) remove retry mechanism
3) pm thread only use to transmit data,not parse detailed message.

v1-->v2:
   remove delay in pm_monitor_loop
Tracked-On: #4446
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Yuhong Tao <yuhong.tao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-04-16 22:01:54 +08:00
Mingqiang Chi
f90100e382 hv: add pre-condition for vcpu APIs
remove unnecessary state check and
add pre-condition for vcpu APIs.

Tracked-On: #4320
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-16 21:59:03 +08:00
Jason Chen CJ
0584981c03 hv:add pre-condition for vm APIs
check the vm state in hypercall api,
add pre-condition for vm api.

Tracked-On: #4320
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-16 21:59:03 +08:00
Mingqiang Chi
fe929d0a10 hv: move out pause_vm from shutdown_vm
now it will call pause_vm in shutdown_vm,
move it out from shutdown_vm to reduce coupling.
Tracked-On: #4320
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-16 21:59:03 +08:00
Naveen Saini
fc5292e354 acrnprobe: avoid race condition
main.c is compiled while version.h being generated. This will
result following error:

| main.c: In function 'main':
| main.c:95:5: error: 'AP_MAJOR_VERSION' undeclared (first use in this function)
|    95 |     AP_MAJOR_VERSION, AP_MINOR_VERSION,
|       |     ^~~~~~~~~~~~~~~~
| main.c:95:5: note: each undeclared identifier is reported only once for each function it appears in
| main.c:95:23: error: 'AP_MINOR_VERSION' undeclared (first use in this function)
|    95 |     AP_MAJOR_VERSION, AP_MINOR_VERSION,
|       |                       ^~~~~~~~~~~~~~~~
| main.c:96:5: error: 'AP_BUILD_VERSION' undeclared (first use in this function)
|    96 |     AP_BUILD_VERSION, AP_BUILD_USER,
|       |     ^~~~~~~~~~~~~~~~
| main.c:96:23: error: 'AP_BUILD_USER' undeclared (first use in this function)
|    96 |     AP_BUILD_VERSION, AP_BUILD_USER,
|       |                       ^~~~~~~~~~~~~
| main.c:97:5: error: 'AP_BUILD_TIME' undeclared (first use in this function)
|    97 |     AP_BUILD_TIME);
|       |     ^~~~~~~~~~~~~

Similar issues observed with usercrash too.

To fix this, add version.h header as dependency, to make sure
it is generated successfully.

Tracked-On: #4590

Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
2020-04-16 21:49:18 +08:00
Yonghua Huang
84eaf94ae6 hv: wrap a function to initialize pCPU for second phase
This patch wrapps a common function to initialize physical
 CPU for the second phase to reduce redundant code.

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2020-04-16 14:02:29 +08:00
Zide Chen
5420b34a26 hv: provide vm_config information in get_platform_info hypercall
Hypervisor reports VM configuration information to SOS which can be used to
dynamically allocate VCPU affinity.

Servise OS can get the vm_configs in this order:

1. call platform_info HC (set vm_configs_addr with 0) to get max_vms and
   vm_config_entry_size.
2. allocate memory for acrn_vm_config array based on the number of VMs
   and entry size that just got in step 1.
3. call platform_info HC again to collect VM configurations.

Tracked-On: #4616
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-16 13:46:27 +08:00
Shuang Zheng
b9583f42e9 acrn-config: enable hv config for scenarion setting UI
config app supports hv config in scenario setting UI.

Tracked-On: #4634
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Acked by: Terry Zou <terry.zou@intel.com>
2020-04-16 08:50:31 +08:00
Wei Liu
b4a61abe45 acrn-config: add hv configurations to scenario config xmls
Update the board defconfig to scenario config xmls, and user can configure
it from webUI.

Tracked-On: #4634
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-16 08:50:31 +08:00
Wei Liu
b30d304d69 acrn-config: add support to parse board defconfig from configurations
Board defconfig depends on hypervisor configurations and vm configurations,
add this to support to parse board defconfig from vm configuration.

Tracked-On: #4634
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-16 08:50:31 +08:00
Xiaoguang Wu
d4f789f47e hv: iommu: remove snoop related code
ACRN disables Snoop Control in VT-d DMAR engines for simplifing the
implementation. Also, since the snoop behavior of PCIE transactions
can be controlled by guest drivers, some devices may take the advantage
of the NO_SNOOP_ATTRIBUTE of PCIE transactions for better performance
when snoop is not needed. No matter ACRN enables or disables Snoop
Control, the DMA operations of passthrough devices behave correctly
from guests' point of view.

This patch is used to clean all the snoop related code.

Tracked-On: #4509
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-16 08:40:17 +08:00
Xiaoguang Wu
b4f1e5aa85 hv: iommu: disable snoop bit in EPT-PTE/SL-PTE
Due to the fact that i915 iommu doesn't support snoop, hence it can't
access memory when the SNOOP bit of Secondary Level page PTE (SL-PTE)
is set, this will cause many undefined issues such as invisible cursor
in WaaG etc.

Current hv design uses EPT as Scondary Leval Page for iommu, and this
patch removes the codes of setting SNOOP bit in both EPT-PTE and SL-PTE
to avoid errors.

And according to SDM 28.2.2, the SNOOP bit (11th bit) will be ignored
by EPT, so it will not affect the CPU address translation.

Tracked-On: #4509
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-16 08:40:17 +08:00
David B. Kinder
4b1dfe9632 doc: remove trailing spaces
Remove trailing spaces on lines to avoid potential issues with git

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-15 11:46:06 -07:00
Sainath Grandhi
f290f22344 doc: Known Limitation regarding PCI devices and resources assignment
ACRN assumes certain state for the PCI devices w.r.t. resources assigned to them
before the platform BIOS hands control over to itself.
When the same BIOS is used with native OS boot, there should not be a need for
native kernel to re-program device BARs or bridge windows for bridge devices.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2020-04-15 10:49:10 -07:00
David B. Kinder
237997f3f9 doc: change UOS/SOS to User VM/Service VM
First pass at updating obsolete usage of "UOS" and "SOS"

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-15 10:48:25 -07:00
David B. Kinder
f5f16f4e64 doc: clean up utf8 characters
Stray non-ASCII characters can creep in when pasting from Word or Google
Docs, particularly for "smart" single and double quotes and non-breaking
spaces.  Change these to their ASCII equivalents.  Also fixed some very
long lines of text to wrap at 80-ish characters.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-15 10:17:54 -07:00
Wei Liu
138c3aeadd acrn-config: support passthroug GVT for WaaG by default
Modify launch config tool to support passthroug GVT for WaaG by default.

Tracked-On: #4625
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-15 15:28:14 +08:00
Conghui Chen
84ad340898 hv: fix for waag 2 core reboot issue
Waag will send NMIs to all its cores during reboot. But currently,
NMI cannot be injected to vcpu which is in HLT state.
To fix the problem, need to wakeup target vcpu, and inject NMI through
interrupt-window.

Tracked-On: #4620
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-15 14:42:00 +08:00
Binbin Wu
597f7658fc hv: guest: fix bug in get_vcpu_paging_mode
Align the implementation to SDM Vol.3 4.1.1.
Also this patch fixed a bug that doesn't check paging status first
in some cpu mode.

Tracked-On: #4628
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-15 14:40:02 +08:00
Mingqiang Chi
3df6d71e08 hv:print relocation delta
now the actual address does not match with the MAP file
if enable CONFIG_RELO when there are some exceptions,
this patch print the delta between the actual load addess
and CONFIG_HV_RAM_START.

Tracked-On: #4144
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2020-04-15 14:34:30 +08:00
Zide Chen
6040d8f6a2 hv: fix SOS vapic_id assignment issue
Currently vlapic_build_id() uses vcpu_id to retrieve the lapic_id
per_cpu variable:

  vlapic_id = per_cpu(lapic_id, vcpu->vcpu_id);

SOS vcpu_id may not equal to pcpu_id, and in that case it runs into
problems. For example, if any pre-launched VMs are launched on PCPUs
whose IDs are smaller than any PCPU IDs that are used by SOS.

This patch fixes the issue and simplify the code to create or get
vapic_id by:

- assign vapic_id in create_vlapic(), which now takes pcpu_id as input
  argument, and save it in the new field: vlapic->vapic_id, which will
  never be changed.
- simplify vlapic_get_apicid() by returning te saved vapid_id directly.
- remove vlapic_build_id().
- vlapic_init() is only called once, merge it into vlapic_create().

Tracked-On: #4268
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-15 14:34:15 +08:00
dongshen
00ad3863a1 hv: maintain a per-pCPU array of vCPUs and handle posted interrupt IRQs
Maintain a per-pCPU array of vCPUs (struct acrn_vcpu *vcpu_array[CONFIG_MAX_VM_NUM]),
one VM cannot have multiple vCPUs share one pcpu, so we can utilize this property
and use the containing VM's vm_id as the index to the vCPU array:

 In create_vcpu(), we simply do:
   per_cpu(vcpu_array, pcpu_id)[vm->vm_id] = vcpu;

 In offline_vcpu():
   per_cpu(vcpu_array, pcpuid_from_vcpu(vcpu))[vcpu->vm->vm_id] = NULL;

so basically we use the containing VM's vm_id as the index to the vCPU array,
as well as the index of posted interrupt IRQ/vector pair that are assigned
to this vCPU:
  0: first vCPU and first posted interrupt IRQs/vector pair
  (POSTED_INTR_IRQ/POSTED_INTR_VECTOR)
  ...
  CONFIG_MAX_VM_NUM-1: last vCPU and last posted interrupt IRQs/vector pair
  ((POSTED_INTR_IRQ + CONFIG_MAX_VM_NUM - 1U)/(POSTED_INTR_VECTOR + CONFIG_MAX_VM_NUM - 1U)

In the posted interrupt handler, it will do the following:
 Translate the IRQ into a zero based index of where the vCPU
 is located in the vCPU list for current pCPU. Once the
 vCPU is found, we wake up the waiting thread and record
 this request as ACRN_REQUEST_EVENT

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2020-04-15 13:47:22 +08:00
dongshen
14fa9c563c hv: define posted interrupt IRQs/vectors
This is a preparation patch for adding support for VT-d PI
related vCPU scheduling.

ACRN does not support vCPU migration, one vCPU always runs on
the same pCPU, so PI's ndst is never changed after startup.

VCPUs of a VM won’t share same pCPU. So the maximum possible number
of VCPUs that can run on a pCPU is CONFIG_MAX_VM_NUM.

Allocate unique Activation Notification Vectors (ANV) for each vCPU
that belongs to the same pCPU, the ANVs need only be unique within each
pCPU, not across all vCPUs. This reduces # of pre-allocated ANVs for
posted interrupts to CONFIG_MAX_VM_NUM, and enables ACRN to avoid
switching between active and wake-up vector values in the posted
interrupt descriptor on vCPU scheduling state changes.

A total of CONFIG_MAX_VM_NUM consecutive IRQs/vectors are reserved
for posted interrupts use.

The code first initializes vcpu->arch.pid.control.bits.nv dynamically
(will be added in subsequent patch), the other code shall use
vcpu->arch.pid.control.bits.nv instead of the hard-coded notification vectors.

Rename some functions:
  apicv_post_intr --> apicv_trigger_pi_anv
  posted_intr_notification --> handle_pi_notification
  setup_posted_intr_notification --> setup_pi_notification

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-15 13:47:22 +08:00
dongshen
c2d350c5cc hv: enable VT-d PI for ptdev if intr_src->pid_addr is non-zero
Fill in posted interrupt fields (vector, pda, etc) and set mode to 1 to
enable VT-d PI (posted mode) for this ptdev.

If intr_src->pi_vcpu is 0, fall back to use the remapped mode.

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-15 13:47:22 +08:00
dongshen
f7be985a23 hv: check if the IRQ is intended for a single destination vCPU
Given the vcpumask, check if the IRQ is single destination
and return the destination vCPU if so, the address of associated PI
descriptor for this vCPU can then be passed to dmar_assign_irte() to
set up the posted interrupt IRTE for this device.

For fixed mode interrupt delivery, all vCPUs listed in vcpumask should
service the interrupt requested. But VT-d PI cannot support multicast/broadcast
IRQs, it only supports single CPU destination. So the number of vCPUs
shall be 1 in order to handle IRQ in posted mode for this device.

Add pid_paddr to struct intr_source. If platform_caps.pi is true and
the IRQ is single-destination, pass the physical address of the destination
vCPU's PID to ptirq_build_physical_msi and dmar_assign_irte

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-15 13:47:22 +08:00
dongshen
6496da7c56 hv: add function to check if using posted interrupt is possible for vm
Add platform_caps.c to maintain platform related information

Set platform_caps.pi to true if all iommus are posted interrupt capable, false
otherwise

If lapic passthru is not configured and platform_caps.pi is true, the vm
may be able to use posted interrupt for a ptdev, if the ptdev's IRQ is
single-destination

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-04-15 13:47:22 +08:00
Sainath Grandhi
47f883db30 hv: Hypervisor access to PCI devices with 64-bit MMIO BARs
PCI devices with 64-bit MMIO BARs and requiring large MMIO space
can be assigned with physical address range at the very high end of
platform supported physical address space.

This patch uses the board info for 64-bit MMIO window as programmed
by BIOS and constructs 1G page tables for the same.

As ACRN uses identity mapping from Linear to Physical address space
physical addresses upto 48 bit or 256TB can be supported.

Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-13 16:52:18 +08:00
Sainath Grandhi
1c21f747be hv: Add HI_MMIO_START and HI_MMIO_END macros to board files
Add 64-bit MMIO window related MACROs to the supported board files
in the hypervisor source code.

Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2020-04-13 16:52:18 +08:00
Sainath Grandhi
e14cafe412 acrn-config: round HI_MMIO_START/HI_MMIO_END to the closest 1G
Rounding HI_MMIO_START, HI_MMIO_END to the closest 1G. This avoids
round up logic in the hypervisor.

Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2020-04-13 16:52:18 +08:00
Jian Jun Chen
159c9ec759 hv: add lock for ept add/modify/del
EPT table can be changed concurrently by more than one vcpus.
This patch add a lock to protect the add/modify/delete operations
from different vcpus concurrently.

Tracked-On: #4253
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2020-04-13 11:38:55 +08:00
David B. Kinder
1e8269b5f7 doc: fix misspellings
Fix misspellings missed during regular reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-10 08:58:54 -07:00
David B. Kinder
a29ef9178e doc: remove /404.html redirect
Using a root-level /404.html as a redirect to the /latest/404.html
causes the URL shown in the browser to change so you can't see what the
error-causing URL was.  Instead of a redirect, copy the /latest/404.html
generated by Sphinx to /404.html and edited with a <base> tag that
specifies a base URL for all relative URLs on a page.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-09 14:21:46 -07:00
Li Fei1
74edf2e54b hv: vmcs: remove vmcs field check for a vcpu
The VMCS field is an embedded array for a vCPU. So there's no need to check for
NULL before use.

Tracked-On: #3813
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-04-09 09:40:26 +08:00
Li Fei1
366214e567 hv: virq: refine pending event inject sequence
Inject pending exception prior pending interrupt to complete the previous instruction.

Tracked-On: #1842
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-09 09:40:00 +08:00
David B. Kinder
88a5212396 doc: update robots.txt exclusion list
Developers using google search can accidentally find older versions of
documents and lead to confusion.  While we do maintain previous release
documentation on the site, we should have a preference for the latest
documentation when using external search engines.  (Note the on-site
search always returns version-specific results.)

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 18:22:48 -07:00
David B. Kinder
296b666f5f doc: tweak 404 page for phone display
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 18:22:14 -07:00
David B. Kinder
1b5a49770e doc: fix 404 display on mobile devices
Fix display of 404 errors on mobile phones.  Also added some additional
wording for reporting errors.  (Last change, I hope :)

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 17:11:55 -07:00
David B. Kinder
e91eee2ab6 doc: update custom CSS with additional styles
Add styles for multi-column display, and for auto-numbered instruction
steps used in some other projects.

Also updating the used page width to 1100px following experience
improvements noted on other sites.  Pages are hard to read when
displayed full-screen on really wide monitors.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 16:59:22 -07:00
David B. Kinder
5c35fa84ab doc: fix image size on 404 page
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 16:04:05 -07:00
David B. Kinder
b67d88cab3 doc: fix 404 processing
Some additional tweaks to the publish script, image, and root-level
redirect to fix a redirect recursion problem.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 14:37:04 -07:00
David B. Kinder
dffa75e50f doc: add a custom 404 page
Add a site-wide custom error page for broken references within the site.
Besides giving a better user experience, it's also easier to track
broken links to the site using google analytics (looking for hits to the
404.html page and noticing the referrer.

Note we only "publish" the custom 404.html when publishing the latest
documents (not for released versions) so we always get the latest
left-navigation menu when a 404 error occurs.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2020-04-08 12:53:37 -07:00
lirui34
f981ddbd1b doc: gsg quick setup script issue fix.
- Fix swupd mirror issue
- Fix bootloader config file not detect correctly issue

Signed-off-by: lirui34 <ruix.li@intel.com>
2020-04-08 11:49:49 +08:00
Tw
e51d12d8cb sample: add sample script for launching xenomai RTVM
Add a launch script for xenomai RTVM.

Tracked-On: #4514
Signed-off-by: Tw <wei.tan@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
2020-04-08 11:49:27 +08:00
Wei Liu
793e22a87a acrn-config: remove the same parameters and functions from launch_cfg_lib
Launch config should relay on library/common.py and launch_cfg_lib,
then remove the duplicate parameters and functions.

Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-08 10:19:17 +08:00
Wei Liu
ba3c531e50 acrn-config: remove the same parameters and functions from scenario_cfg_lib
Scenario config should relay on library/common.py and scenario_cfg_lib,
then remove the duplicate parameters and functions.

Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-08 10:19:17 +08:00
Wei Liu
ed8ac484ad acrn-config: remove the same parameters and functions from board_cfg_lib
Board config should relay on library/common.py and board_cfg_lib, then
remove the duplicate parameters and functions.

Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-08 10:19:17 +08:00
Wei Liu
78ce220eb9 acrn-config: expends parameters and functions to common lib
For purpose to refine the library/common and xx_cfg_lib, should have
to expands parameters and functions to common.py firstly.

Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
2020-04-08 10:19:17 +08:00
Li Fei1
2d66d39529 hv: vpci: refine comment for pci_vdev_update_vbar_base
Refine why we set the base_gpa to zero for a vBAR.

Tracked-On: #3475
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-04-08 10:15:34 +08:00
Li Fei1
572f755037 hv: vm: refine the devices unregistration sequence of vm shutdown
Conceptually, the devices unregistration sequence of the shutdown process should be
opposite to create.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-04-08 10:13:37 +08:00