Commit Graph

21 Commits

Author SHA1 Message Date
Junjun Shan
4fd5102edc hv:treewide:fix multiple MISRAC violations
MISRAC has requirements about literal value requires a U suffix and
signed/unsigned conversion with cast. This patch is used to solve
these violations.

v1->v2
 *Drop the cast of sz from uint32_t to int32_t, the signed/unsigned
  violation of nchars will be solved by other patch together with
  printf/sprintf/console/vuart/uart code.

 *Delete the unnecessary L suffix of shifting operand.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Reviewed by: Junjie Mao <junjie.mao@intel.com>
2018-09-13 11:12:29 +08:00
Li, Fei1
709cd5749e hv: lib: add ffz64_ex
Add ffz64_ex to find the first zero bit in a uint64_t array.
Note: the API is lockless.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-17 14:27:12 +08:00
Junjun Shan
ca83c09b9f hv: treewide: fix multiple MISRAC violations
MISARC has requirements about  Marco redefinition, usage of ++ or -- and
assignment operator in boolean expression. This patch is used to solve
these violations.

The modifications are summarized as following:
1.The HC_VM_SET_MEMORY_REGION, HC_VM_GPA2HPA, HC_VM_SET_MEMORY_REGIONS are
redefined twice in acrn_hv_des.h, so delete them to solve the macro
redefinition violations.

2.The macro BUS_LOCK are redefined in bits.h and atomic.h, then delete
the declaration in both two files, add a new declaration in cpu.h and
include the header file.

3.modify the code to solve the improper usage of -- operators in string.c.

4.modify the while loop to for loop to avoid assignment operator in
boolean expression in vlapic.c.

v1 -> v2:
 *Modify the format of commit logs and signed-off name.

 *Modify the code format from 'd = d-1;' to 'd--;' to be better.

Signed-off-by: Junjun Shan <junjun.shan@intel.com>
2018-08-15 11:21:09 +08:00
Arindam Roy
a2fe964de8 HV: Rename functions beginning with "_"
V1:
In order to remove MISRA C violations for rule
219S, rename functions, macros whose name
starts with "_".
Also removed some __mmio functions because they are
duplicates and are not used anywhere.
Renamed functions like __assert, to asm_assert,
because they were only wrappers around asm calls.

V2:
Over and above the changes on V1, modified bitmap
functions names to lock (corresponding to unlock)
introduced in V1

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-30 10:11:54 +08:00
Huihuang Shi
496e40072e HV:treewide:fix rest of violations related parameter changed
Misra c required parameter should not changed in the scope
of function,use local variable to replace it.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-27 16:42:19 +08:00
Yang, Yu-chu
91337da5a1 HV: logical and high level precedence expression needs brackets
Added brackets for expression to make it easy to understand and
reduce the mistake of precedence. The rule is applied to the
mixed same level of prevedence opeartors, high level presedence
operators and logical expression.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 10:10:39 +08:00
Arindam Roy
af806a93bd HV: Fix missing brackets for MISRA C Violations
Patch 6 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-13 09:09:12 +08:00
Yin Fengwei
fdd785d669 hv: Add 32bit bitmap bit ops API
We need bitmap bit ops API for 32bit operators like vlapic irr
registers.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-05 10:01:15 +08:00
Xiangyang Wu
50f06cad55 HV:treewide: Rename bit operation function fls as fls32
Rename bit operation function fls as fls32, keep name
style with other bit operation function.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-03 17:12:54 +08:00
Xiangyang Wu
a97593e7db HV:treewide:Update return type of function ffs64 and ffz64
To reduce type conversion in HV:
Update return type of function ffs64 and ffz64 as uint16;
For ffs64, when the input is zero, INVALID_BIT_INDEX is returned;
Update temporary variable type and return value check of caller
when it call ffs64 or ffz64;

Note: In the allocate_mem, there is no return value checking for
calling ffz64, this will be updated latter.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER
        Coding style fixing;
        INVALID_CPU_ID instead of INVALID_PCPU_ID or INVALID_VCPU_ID;
        "%hu" is used to print vcpu id (uint16_t);
        Add "U/UL" for constant value as needed.
V2-->V3:
        ffs64 return INVALID_BIT_INDEX directly when
        the input value is zero;
        Remove excess "%hu" updates.
V3-->V4:
        Clean up the comments of ffs64;
        Add "U" for constant value as needed.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 15:11:22 +08:00
Xiangyang Wu
db01efa047 HV:treewide:Update return type for function fls64 and clz64
Change the return type of function fls64 and clz64 as uint16_t;
When the input is zero, INVALID_ID_INDEX is returned;
Update temporary variable type and return value check of caller
when it call fls64 or clz64;
When input value is zero, clz64 returns 64 directly.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER;
        Partly revert apicv_pending_intr udpates;
        Add type conversion as needed;
        Coding style fixing.
V2-->V3:
        Correct type conversion;
        fls64 return INVALID_BIT_INDEX directly when
        the input value is zero.
V3-->V4:
        No updates for this part in PATCH V4.

Note: For instruction "bsrq", destination register value
      is undefined when source register value is zero.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 15:11:22 +08:00
Xiangyang Wu
13d354e7a6 HV:treewide:Update return type for bit operations fls and clz
Change the return type of function fls and clz as uint16_t;
When the input is zero, INVALID_BIT_INDEX is returned;
Update temporary variable type and return value check of caller
when it call fls or clz;
When input value is zero, clz returns 32 directly.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER;
        Add type conversion as needed;
        Add "U/UL" for constant value as needed;
        Codeing style fixing.
V2-->V3:
       Use type conversion to remove side effect of
       the variable which stores fls/clz return value;
       fls return INVALID_BIT_INDEX directly when the
       input value is zero.
V3-->v4:
       Clean up comments for fls.

Note: For instruction "bsrl", destination register value
      is undefined when source register value is zero.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 15:11:22 +08:00
Xiangyang Wu
cc50165018 HV:treewide:Cleanup the type for parameters of bitmap
operations

For reducing sign conversion in hypervisor:
Update parameters of bitmap operations as unsigned type;
Update the input of related caller as unsigned type when the
caller's input parameter is const variable or the variable is
only used by bitmap operations.

V1-->V2:
        (1) Explicit casting for the first parameter
            of all bitmap operations;
        (2) Remove mask operation for explicit casting
            of all bitmap operations, since masking is
            useless. Otherwise, this trucation is dangerous.
V2-->V3:
        (1) Explicit casting for all bitmap operations parameter;
        (2) Masking bit offset with 6-bit;
        (3) Add few comments about bit offset.
V3-->V4:
        add '\' for some statement of bitmap macro

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 10:46:11 +08:00
Huihuang Shi
9600dfa07d fix "function return type inconsistent"
MISRA C required function return type should be consistented.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00
Zheng, Gen
8f3b36b224 HV: add volatile declaration to pointer parameter
Add a volatile declaration to pointer parameter to avoid compiler
to optimize it by using old value saved in register instead of
accessing system memory.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 13:41:12 +08:00
Li, Fei1
34445008c2 hv: add non-lock bitmap operation
Add __bitmap_set/clear,
__bitmap_test_and_set/clear.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-25 09:42:03 +08:00
Li, Fei1
efb60e2726 hv: refine bit scan API
Rename
bsrl to bsr
bsrq to bsr64
bitmap_ffs to fls64
get_first_zero_bit to ffz64

Remove
ffsl

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-25 09:42:03 +08:00
Li, Fei1
57d0bf3b7c hv: refine bitops
Rename bitmap_clr to bitmap_clear
Rename bitmap_isset to bitmap_test
Remove bitmap_setof

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-25 09:42:03 +08:00
Li, Fei1
5e427f340e hv: lib: split atomic operation to atomic.h
split atomic related operation to file atomic.h

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Zhao Yakui
ec13f4e1f2 HV:Remove the "immediate" constraint for inline assembly in bits operation
The input operand for inline assembly is passed from the caller. And they
are not the immediate type. Instead the register should be used.
This also helps to reduce the compile error if the optimizatin is enabled.

Signed-off-by: Zhao Yakui<yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Eddie Dong
7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00