Fix the folder name where the 'acrn-manager' source code is located.
Replace instances of 'UOS' by 'User VM'
Other minor text updates to improve readability
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
generate ASL code of ACPI tables for pre-launched VMs on nuc7i7dnb,
whl-ipc-i5, whl-ipc-i7, ehl-crb-b boards
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
enable TPM2 config on ehl-crb-b board and update TPM2 configs on
legacy boards.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
For EHL hybrid_rt scenario, the requirement needs a network device
passthough to pre-launched VM0.
Tracked-On: #5286
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add 2 MACROs: DEFAULT_PCI_MMCFG_START_BUS and DEFAULT_PCI_MMCFG_END_BUS
in platform_acpi_info.h.
Tracked-On: #5233
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add 2 MACROs: DEFAULT_PCI_MMCFG_START_BUS and DEFAULT_PCI_MMCFG_END_BUS
in platform_acpi_info.h.
Tracked-On: #5233
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
use offline tool to generate one binary of ACPI tables for pre-launched
VMs, then load the ACPI binary into guest physical memory as grub module.
Users can configure the resources or devices like TPM2 for the
pre-launched VM from sceanrio XMLs or UI, and the offline tool will
generate ASL code of the ACPI tables with the configured resources or
devices, then compile the ASL code to one binary when building ACRN.
Tracked-On: #5266
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
EHL PSE TSN GbE driver is default set to use 32bit of dma addressing.
net: stmmac: configure PSE Gbe to 32bit dma addressing
https://github.com/intel/linux-intel-lts/commit/011c8f
When VM has more than 4GB physical memory, Linux kernel uses the bounce
buffers (swiotlb) to translate kernel data in 64bit memory to 32bit
range for the sake of the DMA because iommu is not available. The
default swiotlb value 32768 is insufficient to support two PSE TSN GbEs
at the same time. Increase the value to 131072 otherwise two GbEs can't
link up.
Tracked-On: #5243
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
When creating a new launch setting, config app can't fine the
scenario config which caused the app failed to load the new
launch setting.
Tracked-On: #5282
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Build and install 'acrnctl' for regardless of the RELEASE value. Kata Containers
depends on 'acrnctl' in order to work correctly and we therefore need to make
sure that it is built and installed correctly regardless of whether this is a
debug or a release build.
Tracked-On: #4940
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Add a new scenario xml file for EHL which is derived from hybrid_rt for
validation of certain passthru devices in prelaunched RTVM. Because the
configuration requires to disable GPIO support for SOS VM, it should
not be merged into the standard hybrid_rt scenario. According to this
change, remove the SCI passthru setting from existing hybrid_rt since
from now on hybrid_rt_fusa should be used for SCI passthru test.
Tracked-On: #5278
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
minor_ver should be le 2 when major_ver == 2.
Tracked-On: #5276
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
update the size of ivshmem memory region to [2MB, 512MB].
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Yuan Liu <yuan1.liu@intel.com>
Always use P2SB_ as a prefix for all macro definitions related to P2SB
MMIO passthru. And introduce the new P2SB_VGPIO_DM_ENABLED macro to
indicate the presence of the pre-launched VM which requires the feature.
This macro intends to be used to enclose source files with ifdef where
macros defined by config-tool being used which are available only when
the feature is enabled. It is required to avoid causing compilation
errors when users build HV without enabling the feature.
Tracked-On: #5246
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Two PSE-GPIO controllers of EHL CRB require MSI-X emulation for
pass-thru because it uses multiple MSI vectors. Currently acrn-config
enables MSI-X emulation for only TSN devices. Enable MSI-X emulation
for PSE-GPIOs, too.
Tracked-On: #5242
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
After below commit in https://github.com/zephyrproject-rtos/zephyr
commit d0126a037d23484feebba00d2c0eac27e6393fef
Author: Zide Chen <zide.chen@intel.com>
Date: Wed Feb 5 08:32:00 2020 -0800
boards/x86/acrn: build it in x86_64 mode and switch to X2APIC
The zephyr image for acrn would be built in x86_64 mode by default, then the
load/entry address for pre-launched Zephyr image should be changed from
0x100000 to 0x8000 accordingly per below definition in zephyr .ld file:
zephyrproject_src/zephyr/include/arch/x86/intel64/linker.ld
SECTIONS
{
/*
* The "locore" must be in the 64K of RAM, so that 16-bit code (with
* segment registers == 0x0000) and 32/64-bit code agree on addresses.
* ... there is no 16-bit code yet, but there will be when we add SMP.
*/
.locore 0x8000 : ALIGN(16)
{
_locore_start = .;
The commit in zephyrproject is merged before zephyr v2.2 release, so from v2.2
on, HV need this fix to boot Zephyr as pre-launched VM.
Tracked-On: #5259
Signed-off-by: Victor Sun <victor.sun@intel.com>
ACRN 2.1 supports two virtual boot modes, deprivilege boot mode and
direct boot mode. The deprivilege boot mode’s main purpose is to support
booting Clear Linux Service VM with UEFI service support, but this
brings scalability problems when porting ACRN to new Intel platforms.
For the 2.2 release, deprivilege mode is removed, and only direct boot
is supported, and with this we've removed support for Clear Linux as the
service VM, which impacts over 50 ACRN documents. This PR removes
documents we don't intend to update, and fixes broken links that would
occur from references to these deleted docs.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Convert SERIAL_PCI_BDF string value to hex value.
Tracked-On: #4937
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Tested-by: Shuo A Liu <shuo.a.liu@intel.com>
Users can add one or more ivshmem shm regions for uos when the shm
regions are configured from scenario setting.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add shm_region config in default launch XMLs to configure Inter-
VM communication for post-launched VMs.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch is to expose GPIO chassis interrupts as INTx to safety VM for
EHL. User can configure this per-VM attribute in scenario xml using the
following format:
<pt_intx desc="pt intx mapping.">
(phys_gsi0, virt_gsi0), (phys_gsi1, virt_gsi1), (phys_gsiN, virt_gsiN)
</pt_intx>
The physical and virtual interrupt gsi in each pair are separated by a
comma and enclosed in parentheses. If an integer begins with 0x or 0X,
it is hexadecimal, otherwise, it is assumed to be decimal. Example:
<pt_intx desc="pt intx mapping.">
(1, 0), (0x3, 1), (0x4, 2), (5, 6), (89, 0x12)
</pt_intx>
Tracked-On: #5241
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This patch is to support direct assignment of P2SB bridge to one pre-launched
VM for EHL. User can configure this per-VM attribute in scenario xml:
<mmio_resources desc="MMIO resources.">
<p2sb>y</p2sb>
</mmio_resources>
Set p2sb to y to passthru P2SB bridge to VM, and n otherwise.
Tracked-On: #5221
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Add missing IVSHMEM tag in mrb board xml file to fix build issue
Correct misspelled function name
Use better error messages
Tracked-On: #5221
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Because ivshmem memory uses hv memory, if the ivshmem feature is
enabled, HV_RAM_SIZE will include IVSHMEM_SHM_SIZE.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add hybrid_rt scenario for the ElkhartLake CRB board so that user can
launch Yocto Linux as pre-launched VM.
Tracked-On: #5238
Signed-off-by: "Nishioka, Toshiki" <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.Modify clos_mask and mba_delay as a member of the union type.
2.Move HV_SUPPORTED_MAX_CLOS ,MAX_CACHE_CLOS_NUM_ENTRIES and
MAX_MBA_CLOS_NUM_ENTRIES to misc_cfg.h file.
Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.
MAX_MBA_CLOS_NUM_ENTRIES:
Max number of Cache Mask entries corresponding to each CLOS.
This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
cache mask values for Data and Code when CDP is enabled.
MAX_CACHE_CLOS_NUM_ENTRIES:
Max number of MBA delay entries corresponding to each CLOS.
2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.
Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
HV_SUPPORTED_MAX_CLOS:
This value represents the maximum CLOS that is allowed by ACRN hypervisor.
This value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
among all supported RDT resources in the platform. In other words, it is
min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
CLOS allocations between all the RDT resources.
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
add IVSHMEM config in hybrid_rt scenario on tgl-rvp board.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
We use sos kernel cmdline maxcpus to limit the pCPU number of SOS
for hybrid or hybrid_rt scenarios by vcpu numbers calculation.
v2: add SOS CPU affinity calculation by total pCPU plus pCPUs
occupied by pre-launched VMs when no pcpuid configured
in SOS.
Tracked-On: #5216
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Add cfl-k700-i7 board xml and its industry xml to support ACRN industry
scenario on cfl-k700-i7 board.
Tracked-On: #5212
Signed-off-by: Victor Sun <victor.sun@intel.com>
CPU sharing between pre-launch VMs and SOS, post-launch VMs were
forbidden.
Remove the limitation.
Tracked-On: #5153
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
This patch is to support the Inter-VM communication by IVSHMEM
in config tool.
Users can configure IVSHMEM_ENABLE to enable or disable Inter-VM
communication by IVSHMEM; users can configure the name, size,
communication VM IDs of the IVSHMEM devices in the VM settings of
scenario xmls, then config tool will generate the related IVSHMEM
configurations for Inter-VM communication.
The config tool will do sanity check including when saving the xmls:
the format of shared memory region configuration is
[name],[size],[VM ID]:[VM ID](:[VM ID]...);
the max size of the name is 32 bytes;
the names should not be duplicated;
the mininum value of shared memory region size is 2M;
the value of shared memory region is a power of 2;
the size of share memory region should not extended the size of
available ram.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Shared memory regoins can be added or deleted or updated from
scenario settings in config app with sanity check.
v2: move IVSHMEM config to hv->FEATURES->IVSHMEM
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
add IVSHMEM_ENABLED and IVSHMEM_REGION in scenario xmls to support
Inter-VM communications configuration for VMs.
v2: move IVSHMEM config into <FEATURES> section
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Enable TPM passthrough configuration for pre-launched VM feature, on
TGL, by adding 'tgl-rvp' to TPM_PASSTHRU_BOARD.
Tracked-On: #5205
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Get the max number with integer list to instead string 'number'.
Tracked-On: #5199
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The default memory is 16G on TGL; the value of PLATFORM_RAM_SIZE and
SOS_RAM_SIZE is a little small in default xml.
Tracked-On: #5184
Reviewed-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: fuzhongl <fuzhong.liu@intel.com>
add an IVSHMEM regoin and the related configuration parameters in
hybrid_rt scenario on whl-ipc-i5. The size of the shared memory is
2M, and it is used for the communication between VM0 and VM2.
v6: rename shm name; remove unnecessary MACROs.
v7: rename MACRO for shm name; add unassigned vbdf for post-launched
VMs.
Tracked-On: #4853
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Fix build issue while CDP_ENABLED=y for EHL-CRB-B.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The default memory is 16G on TGL; the value of HV and sos
ramsize is a little small in default xml.
Tracked-On: # 5184
Signed-off-by: fuzhongl <fuzhong.liu@intel.com>
Add a comment for SOS_VM to indicate its VM ID for better understanding;
Tracked-On: #5077
Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
