Commit Graph

119 Commits

Author SHA1 Message Date
Mingqiang Chi
ae8836d960 hv:fix return value violation for vioapic_get_rte
Change this API to void type
Add pre-condition, state the input parameters are not NULL.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 14:47:43 +08:00
Yin Fengwei
f576f97ea8 hv: add vm restart API
And export the API to DM. DM will do system reboot/S3 resume based
on this API.

Also add the pre-assumption description for some vm APIs.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Shiqing Gao
51c75e9e3c hv: treewide: fix 'Function prototype/defn param type mismatch'
Fix the parameter type mismatch between API declaration and definition.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-01 15:53:29 +08:00
Xiangyang Wu
6e77a8d5f1 HV:treewide:rename enum vpic_wire_mode, stack_canary, segment_override, pde_index
For data structure types "enum vpic_wire_mode, struct stack_canary",
its name is identical with variable name in the same scope.
This MISRA C  violation is detected by static analysis tool.
For variables "segment_override, pde_index", its name is identical
with function name. This MISRA C  violation is detected.
Naming convention rule:Variable name can be shortened from
its data structure type name.

The following udpates are made:
enum vpic_wire_mode vpic_wire_mode-->enum vpic_wire_mode wire_mode
struct stack_canary stack_canary-->struct stack_canary stk_canary
uint8_t segment_override:1 --> uint8_t seg_override:1
uint32_t pde_index--> uint32_t pde_idx

V1-->V2:
	Remove update "enum cpu_state cpu_state-->enum cpu_state state"
	and "enum irqstate irqstate-->enum irq_ops_mode ops_mode", other
	patch will cover it.
V2-->V3:
	Update "uint32_t pde_index--> uint32_t pde_idx".

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2018-07-31 11:20:21 +08:00
Xiangyang Wu
2c95a8c4aa HV:treewide:rename struct pic and iommu_domain
For data structure types "struct pic and struct iommu_domain",
its name is identical with variable name in the same scope.
This MISRA C  violation is detected.

Naming convention rule:If the data structure type is used by only one
module and its name meaning is simplistic, its name needs prefix
shorten module name.
Naming convention rule:Variable name can be shortened from its
data structure type name.

The following udpates are made:
struct pic pic-->struct i8259_reg_state i8259
struct iommu_domain iommu_domain-->struct iommu_domain iommu

V1-->V2:
	Update "struct iommu_domain iommu_domain-->struct iommu_domain iommu"

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-31 10:33:22 +08:00
Junjie Mao
17771c0ac2 HV: io: refine state transitions of VHM requests
Instead of using two members for maintaining the state of a VHM request, this
patch replaces the transitions with a single state. Basically the lifecycle of a
VHM request shall be:

    FREE -> PENDING -> PROCESSING -> COMPLETE -> FREE -> ...

The structure header of vhm_request has more details of the transitions access
limitations under different states.

Also drop the set but unused member vcpu.ioreq_pending.

For backward-compatibility, the obsolete 'valid' member is still kept and
maintained before SOS and DM adapts to the new state transitions.

v2 -> v3:

    * Use complete_ioreq to mark an I/O request finished in
      dm_emulate_(pio|mmio)_post.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-31 10:22:03 +08:00
Xiangyang Wu
159d57b703 HV:treewide:rename union lapic_id and struct segment
For data structure types "union lapic_id and struct segment",
its name is identical with variable name in the same scope. This MISRA C
violation is detected by static analysis tool.

Naming convention rule:If the data structure is corresponding
to hardware resource (such as register, segment selector),
its name need resource shorten name suffix (such as _reg, _sel).

The following udpates are made:
union lapic_id-->union lapic_id_reg
struct segment-->struct segment_sel

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-30 10:18:39 +08:00
Huihuang Shi
59771ff461 HV:treewide:fix "Reference parameter to procedure is reassigned"
Parameter's type which is pointer should not be changed in the
scope of function,assign it's value to local variable to fixed
it out.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 12:17:12 +08:00
Xiangyang Wu
58b42baa74 HV:treewide:rename struct vpic as struct acrn_vpic
There are many naming violations detected by static analysis
tool. Data structure type name is the same as variable name.
According to naming convention rules, If the data structure
type is used by multi modules and its name meaning is
simplistic (such as vcpu, vm), its name needs prefix "acrn_".

Rename struct vpic as struct acrn_vpic.
Replace regular expression:s/struct vpic\([ ),;\t\*]\+\)/struct acrn_vpic\1

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 11:27:12 +08:00
Xiangyang Wu
33fdfd05f1 HV:treewide:rename struct vlapic as struct acrn_vlapic
There are many naming violations detected by static analysis
tool. Data structure type name is the same as variable name.
According to naming convention rules, If the data structure
type is used by multi modules and its name meaning is
simplistic (such as vcpu, vm), its name needs prefix "acrn_".

Rename struct vlapic as struct acrn_vlapic
Replace regular expression:s/struct vlapic\([ ),;\t\*]\+\)/struct acrn_vlapic\1

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 11:27:12 +08:00
Junjie Mao
88f74b5dbb HV: io: unify vhm_request req and mem_io in vcpu
The current struct vcpu has two members, namely 'struct vhm_request req' and
'struct mem_io mmio', that hold similar info, including the address, direction, size,
value and status of mmio reqeusts.

As a step towards a unified framework for both MMIO/PIO, this patch unifies
these two members by a tailored version of vhm_reqeust, mostly with the reserved
fields dropped. The definitions to request types, directions and process status
are reused.

Handling errors during emulations will be revisited after the I/O emulation
paths are unified. Thus for this patch the mmio.mmio_status in inherited by
io_req.processed which is not yet properly processed.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 10:50:19 +08:00
Junjie Mao
1915eec632 HV: io: separate I/O emulation interface declarations
Currently the I/O emulation structures and interfaces are scattered among mmu.h,
io.h and guest.h, and tangled with other interfaces there. This patch moves the
former to a separate header ioreq.h.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 10:50:19 +08:00
Huihuang Shi
5189bcd272 HV:treewide:fix "Attempt to change parameter passed by value"
In the function scope,the parameter should not be
changed as Misra required.
V1->V2 recover some violations because of ldra's false positive.
V2->V3 sync local variable' type to parameter's type with the prefix of const.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 09:35:52 +08:00
Jason Chen CJ
589c72382a add CONFIG_VM0_DESC support
if defined CONFIG_VM0_DESC, HV will use predefined vm0_desc to config
VM0, otherwise, HV will run VM0 with all physical cpus.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-25 17:18:14 +08:00
Jason Chen CJ
22833787ce refine definition for foreach_vcpu
foreach_vcpu will go through all vcpu_array and only call the following
code when vcpu != NULL

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-25 17:18:14 +08:00
Binbin Wu
b2802f3d1d hv: cpu: align general-purpose register layout with vmx
In current code, general-purpose register layout in run_context is not align with the
general-purpose register index when vmexit. So hv needs to map the index used during
vmexit to the index of the general-purpose register in run_context.
This patch align the layout, so that no mapping needed.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-25 13:05:38 +08:00
Li, Fei1
1815a1bb01 hv: ept: store virtual address of EPT PML4 table
Most of the time, we use the virtual address of EPT PMl4 table,
not physical address.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-20 10:40:32 +08:00
Shiqing Gao
0252ae9e11 hv: treewide: fix 'No definition in system for prototyped procedure'
- Remove those APIs without definition

- Minor changes to make sure the line length is less than 80

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-20 10:38:32 +08:00
Xiangyang Wu
d28fff2b06 HV:treewide:Update the type of return value and parameters of atomic operations
There are many type conversions in the atomic
operations invoking reported by static analysis tool. These
type conversions voilate MISRA C.

To keep uniform naming convention, rename atomic operation
function names:
atomic_set_int/long --> atomic_set32/64;
atomic_clear_int/long --> atomic_clear32/64;
atomic_load --> atomic_load32;
atomic_store --> atomic_store32;
atomic_swap --> atomic_swap32;
atomic_readandclear --> atomic_readandclear32;
atomic_inc --> atomic_inc32;
atomic_dec --> atomic_dec32;
atomic_cmpxchg --> atomic_cmpxchg32;
atomic_xadd --> atomic_xadd32.
Update the type of atomic_load32/64, atomic_store32/64,
atomic_swap32/64, atomic_cmpxchg32/6.
Update related variables and callers.

Note: the type of return value and parameters of atomic_xadd32/64
still keep signed int/long since caller pass
negative variable to atomic_xadd32/64;

V1-->V2:
	Add comments for atomic_set/clear to differ from
	bitmap_set/clear.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie.Mao <junjie.mao@intel.com>
2018-07-19 14:39:47 +08:00
Zheng, Gen
20c80ea72a HV: bug fix on emulating msi message from guest
Current code has a mistake associating destination with
redirectionhint. So just use the destination mode to work out
destination mode.

When injecting the msi interrupt to vcpu in hypervisor layer,
current code ingnores the redirection hint(RH) bit of msi address
message from guest, and just use the destination mode and
destination ID. So correctly before injecting, check the RH bit,
if set, choose the vcpu that has lowest priority to inject msi.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com>
Reviewed-by: Yin, Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-19 11:09:09 +08:00
Xiangyang Wu
612cdceaca HV:treewide:Add exec_vmread32 and exec_vmwrite32 functions
In the hypervisor, VMCS fields include 16-bit fields,
32-bit fields, 64-bit fields and natural-width fields.
In the current implement, no exec_vmread32/exec_vmwrite32
is for accessing 32-bit fields. So there are many type
casting for the return value and parameters vmread/vmwrite
operations.

Create exec_vmread32 and exec_vmwrite32 functions to
access 32-bit fields in VMCS;
Update related variables type for vmread/vmwrite operations;
Update related caller according to VMCS fields size.

V1--V2:
        This is new part of this patch serial to only
        update 32 bit vmread/vmread opertions and related
        caller.
V2-->V3:
	Update related variables type in data structure
	 for exec_vmread32/exec_vmwrite32.
	Rename temp variable 'low' into 'value' for
	exec_vmread32;
V3-->V4:
	Remove useless type conversion.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-18 12:31:42 +08:00
Huihuang Shi
f2774e496b HV:common:fix "integer type violations"
fix integer type violations,keep some violations which
related to hypcall and msix_entry_index.

V1->V2:1.modified API_MAJOR_VERSION from Makefile
       2.sync acrn_common.h changed to device model

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-18 12:31:14 +08:00
Junjie Mao
69ebf4c6e6 HV: vioapic: cleaning up integral-type-related violations
This patch cleans up the integral-type-related violations after the access
pattern to RTEs is unified. Major changes include:

    1. vioapic_mmio_read(), vioapic_mmio_write() and vioapic_mmio_rw() assumes
       the size of the register to be accessed is always 4, which is checked in
       vioapic_mmio_access_handler(). Thus they no longer takes the unused
       ''size'' parameter.

    2. Typical integral-type-related violation fixes including 'U' suffixes,
       type of local variables, conversion specification in format strings, etc.

v1 -> v2:

    * Drop duplicated definitions to IOAPIC register offsets.
    * Drop the ''size'' parameter of vioapic_mmio_[read|write] and
      vioapic_mmio_rw since vioapic_mmio_access_handler() ensures that size is
      always 4.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-17 15:37:45 +08:00
Junjie Mao
a1069a5117 HV: ioapic: unify the access pattern to RTEs
There are two different ways the current implementation adopts to access ioapic
RTEs:

    1. As two 32-bit registers (typically named ''low'' and ''high''), or

    2. As one 64-bit register (typically named ''rte'').

Two issues arise due to the mixed use of these two patterns.

    1. Additional conversions are introduced. As an example, ioapic_get_rte()
       merges two RTE fragments into a uint64_t, while some callers break it
       back to ''low'' and ''high'' again.

    2. It is tricky to choose the proper width of IOAPIC_RTE_xxx constants. SOS
       boot failure is seen when they are 32-bit due to the following code:

           /* reg is uint64_t */
           vioapic->rtbl[pin].reg &= ~IOAPIC_RTE_REM_IRR;

       while making them 64-bit leads to implicit narrowing when the RTEs are accessed
       in the low & high pattern.

This patch defines a union ''ioapic_rte'' and unifies the access pattern
to IOAPIC and vIOAPIC RTEs.

v1 -> v2:

    * Instead of two 32-bit ''low'' and ''high'', define a union that allows
      either 32-bit or 64-bit accesses to RTEs.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-17 15:37:45 +08:00
Minggui Cao
2f2d108b1e HV: handle integral issue report by MISRA-C
The main focus on: constant suffix U/UL; parameters cast like
uint32 to a uint16 variable; unify some APIs interface,
consist with the callers.

also modify some places to unify code style

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
2018-07-16 16:24:29 +08:00
Huihuang Shi
aa5027a30c HV:misc:fix "signed/unsigned conversion with cast"
Signed/unsigned conversion should add cast explicitily
or change the type of them to the same.

V1->V2:Fixed the 0U to 0UL because of the mistakes.
V2->V3:remove unsed macro

Signed-off-by: HuiHuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-16 15:45:40 +08:00
Huihuang Shi
680c64de13 HV:transfer vmid's type to uint16_t
vmid's type prefered to be uint16_t.

V1->V2:vmid from uint32_t transfer to uint16_t
V2->V3:add range check to hcall's vmid parameter
V3->V4:seperate the declaration and actual code.
V4->V5:remove range check from hcall's vmid parameter

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 14:13:38 +08:00
Huihuang Shi
e3302e87e8 HV:transfer vm_hw_logical_core_ids's type and rename it
rename vm_hw_logical_core_ids to vm_pcpu_ids
and changed the type to uint16_t.

V1->V2:rename the vm_hw_logical_core_ids

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 13:05:29 +08:00
Junjie Mao
e3452cf804 HV: vlapic: minimize explicit casts by adjusting types
To minimize explicit casts, this patch adjusts the types of function parameters
and structure fields related to vlapic and update the types in the internal
implementation accordingly.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 10:02:44 +08:00
Minggui Cao
4cab8b9cc5 HV: code cleanup as MISRA-C report for guest/vmsr
like: constant of unsigned int need add U/UL as surfix.
enum value can't use to give or compare with int directlly.
unsigned and signed mis-matched

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-12 17:27:53 +08:00
Xiangyang Wu
4dc39fdb8e HV:treewide:Add 16-bit atomic operations and update vpid type
There are some integer type conversions reported by static
analysis tool for vcpu id, number of created vcpus, and
vpid, to reduce these type conversions, redesign vcpu id,
number of created vcpus, and vpid type as uint16_t as per
their usage, related 16-bit atomic operations shall be
added in HV.
MISRA C requires that all unsigned constants should have the suffix 'U'
(e.g. 0xffU), but the assembler may not accept such C-style constants.

Add 16-bit atomic add/dec/store operations;
Update temporary variables type and parameters type of
related caller;
Update vpid type as uint16_t;
Replace Macro with constant value for CPU_PAGE_SIZE.

Note: According to SDM A.10, there are some bits defined
in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID
instruction, these bits don't mean actual VPID, so
the vpid field in the data struct vmx_capability doesn't
be updated.

V1--V2:
	update comments for assembly code as per coding style;

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 21:27:08 +08:00
Huihuang Shi
0ccd74b947 HV:modified vm_description and vm_hw_info memebers' type
transfer num_vcpus,exp_num_vcpus to uint16_t.
transfer vm_hw_num_cores to uint16_t.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 12:42:22 +08:00
Yang, Yu-chu
0419816574 HV: Avoiding assignment opperation inside macro
To follow the Misra-c standard, the assignment operation inside
function-like macro should be avoided. Replaced the violations
macro using inline function instead.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2018-07-10 11:47:45 +08:00
Xiangyang Wu
474e9af216 HV:CPU: Add 'U/UL' for unsigned const value
According to MISRA C:2012, suffix 'U/UL' shall be for
unsigned const value, the member of enum variable should
not be used to compare with integer variable.

Add 'U/UL' for unsigned const value in the CPU module;
Use Macro insteading of enum feature_word since the member
of feature_word is used to compare with integer variable;
Use hex number insteading of Macro in the assembly code.

V1-->V2:

        Update the suffix of some constant value as 'UL'
        according to its'storage variable;
        Split MACRO updates used in the assembly code
	in other patch.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-09 10:27:21 +08:00
Xiangyang Wu
0f6ff87835 HV:CPU:Constant values replace with CPU MACRO
MISRA C requires that all unsigned constants should have
the suffix 'U/UL'(e.g. 0xffU), but the assembler may not
accept such C-style constants.

To work this around, all  unsigned constants must be
explicitly spells out in assembly with a comment tracking
the original expression from which the magic number is
calculated.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-09 09:24:56 +08:00
Junjie Mao
db62c23d81 HV: vioapic: use uint8_t for pins
IOAPIC pins always fit in 8-bit and we already use uint8_t for virt_pins. This
patch converts pins in vioapic to uint8_t.

This is based on Arindam's previous patch ("was: hv: Cleanup and optimise
vioapic.c"), with SOS boot failure resolved, format string updated, complex
arithmetic expression with implicit type conversion decoupled. Also make some
local variables representing interrupt vectors uint32_t.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-05 15:54:52 +08:00
Mingqiang Chi
9d8893e499 hv:rename several APIs in vlapic.c
rename 4 APIs:
  x2apic_msr -> is_ x2apic_msr
  vlapic_msr -> is_vlapic_msr
  vlapic_mmio_write -> vlapic_write_mmio_reg
  vlapic_mmio_read -> vlapic_read_mmio_reg

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-07-05 10:00:43 +08:00
Xiangyang Wu
b76c92bf3e HV:treewide:Update cpu_id type as uint_16
There are extra type conversion in the HV since cpu_id
type is uint32_t and the return value type of get_cpu_id
is uint16_t. BTW, the name of cpu_id is not clear enough
to express its usage.

So the following updates are made in this patch:
Update cpu_id type as unit_16 to reduce type casting;
Update related temporary variables type;
Update related print argument;
Change the input parameter name of interrupt_init as
cpu_id to keep align with function implement;
Rename cpu_id as pcpu_id as needed.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 16:39:26 +08:00
Xiangyang Wu
188210ab03 HV:Treewide:Update the type of vcpu id as uint16_t
In the hypervisor, virtual cpu id is defined as "int" or "uint32_t"
type in the hypervisor. So there are some sign conversion issues
about virtual cpu id (vcpu_id) reported by static analysis tool.
Sign conversion violates the rules of MISRA C:2012.

BTW, virtual cpu id has different names (vcpu_id, cpu_id, logical_id)
 for different modules of HV, its type is defined as "int" or "uint32_t"
in the HV. cpu_id type and logical_id type clean up will be done in
other patchs.

V1-->V2:
         More clean up the type of vcpu id;
         "%hu" is for vcpu id in the print function.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-04 14:28:52 +08:00
Huihuang Shi
8b94957774 HV:guest:fix "signed/unsigned conversion without cast"
Misra C required signed/unsigned conversion with cast.

V1->V2:
  a.split patch to patch series

V2->V3:
  a.change the uint64_t type numeric constant's suffix from U to UL

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 12:18:38 +08:00
Yin Fengwei
2a819366ae hv: add ioapic reset function
ioapic reset function will be called when doing guest reset.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 16:12:54 +08:00
Xiangyang Wu
a97593e7db HV:treewide:Update return type of function ffs64 and ffz64
To reduce type conversion in HV:
Update return type of function ffs64 and ffz64 as uint16;
For ffs64, when the input is zero, INVALID_BIT_INDEX is returned;
Update temporary variable type and return value check of caller
when it call ffs64 or ffz64;

Note: In the allocate_mem, there is no return value checking for
calling ffz64, this will be updated latter.

V1-->V2:
        INVALID_BIT_INDEX instead of INVALID_NUMBER
        Coding style fixing;
        INVALID_CPU_ID instead of INVALID_PCPU_ID or INVALID_VCPU_ID;
        "%hu" is used to print vcpu id (uint16_t);
        Add "U/UL" for constant value as needed.
V2-->V3:
        ffs64 return INVALID_BIT_INDEX directly when
        the input value is zero;
        Remove excess "%hu" updates.
V3-->V4:
        Clean up the comments of ffs64;
        Add "U" for constant value as needed.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 15:11:22 +08:00
Junjie Mao
cfc3811a0a HV: treewide: drop debug-only helpers in release build
There are multiple helpers for collecting info to be printed on the ACRN uart
console. They are unreachable code in release builds in which the uart console
is removed.

To define a precise boundary for safety-related activities, this patch wraps the
declarations and definitions to these helpers with "#ifdef HV_DEBUG" so that
these unreachable APIs will be dropped in release builds.

v1 -> v2:

    * Fix coding style: no empty lines between #ifdef and the wrapped code.
    * Also drop get_rte_info() in ioapic.c, which is solely used by
      get_ioapic_info().

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 14:35:39 +08:00
Zide Chen
9f4404d0e6 hv: add context->vmx_ia32_pat to save and restore VMCS
Similar to cr0/4:
- use context->vmx_ia32_pat to save/restore VMX_GUEST_IA32_PAT field
- use context->ia32_pat to keep track the guest' view of IA32_PAT MSR

Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 12:33:06 +08:00
Zide Chen
6801d826e2 hv: intercept IA32_PAT MSR
Preparing for emulating guest's CR0.CD and CR0.NW bits:
 - Intercept both rdmsr and wrmsr for IA32_PAT
 - Track guest's IA32_PAT MSR with vcpu.arch_vcpu.contexts.ia32_pat

Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 12:33:06 +08:00
Kaige Fu
7a66c317b5 HV: Remove vm->attr.name
We define attr.name in struct vm and named as ("vm_%d", attr.id). attr.name only
be used in debug tool vm_list. It does't deserve to do so in OS created flow
(aka function create_vm). It's better to handle this in vm_list tool.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@inte.com>
2018-07-02 10:48:36 +08:00
Xiangyang Wu
cc50165018 HV:treewide:Cleanup the type for parameters of bitmap
operations

For reducing sign conversion in hypervisor:
Update parameters of bitmap operations as unsigned type;
Update the input of related caller as unsigned type when the
caller's input parameter is const variable or the variable is
only used by bitmap operations.

V1-->V2:
        (1) Explicit casting for the first parameter
            of all bitmap operations;
        (2) Remove mask operation for explicit casting
            of all bitmap operations, since masking is
            useless. Otherwise, this trucation is dangerous.
V2-->V3:
        (1) Explicit casting for all bitmap operations parameter;
        (2) Masking bit offset with 6-bit;
        (3) Add few comments about bit offset.
V3-->V4:
        add '\' for some statement of bitmap macro

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-02 10:46:11 +08:00
Huihuang Shi
4de869665e HV:treewide:transfer the struct member types to non-basic types
The struct member types should be transfer to non-basic types,
chaned it to length-prefix(uint32_t,int32_t ...) type.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 15:48:19 +08:00
Huihuang Shi
b8384ea0dd HV:common:transfer local variable type
The local variable type should be transfer to non-basic type,
chaned it to length-prefix(uint32_t,int32_t ...) type.

Char *type or char array type which used to pointer a string
will be keeped.

V1->V2 add extra comments.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 09:49:29 +08:00
Yin Fengwei
5b43521461 hv: trap vm0 write/read pm1a/pm1b registers
ACRN needs to trap the pm1a/pm1b written/read from VM0. So we
could know when should we put the system to S3.

We will have two path back to VM0:
 - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec
   with real mode
 - S3 enter/exit failed. Will return to the next instruction of
   pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt
   register to check whether it's waked up or not.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00