Commit Graph

461 Commits

Author SHA1 Message Date
Huihuang Shi
aa5027a30c HV:misc:fix "signed/unsigned conversion with cast"
Signed/unsigned conversion should add cast explicitily
or change the type of them to the same.

V1->V2:Fixed the 0U to 0UL because of the mistakes.
V2->V3:remove unsed macro

Signed-off-by: HuiHuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-16 15:45:40 +08:00
Yin Fengwei
619c600021 hv: cpu state update should be moved just before halt.
The cpu offline requester monitor the target cpu state
to detect whether target cpu is put to offline already.

So we should only update the cpu state to offline after
all other operations are finished.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Eddie Dong <Eddie.dong@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-16 13:06:08 +08:00
Arindam Roy
944776f238 HV: Fix new MISRAC violations for brackets
Fix remaining 11S and 12S violations. These
are after the 7 patches submitted earlier.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-16 11:02:38 +08:00
Yang, Yu-chu
90b342bd53 HV: prototyping non-static function
Includes header file of non-static function, and declare the
in-file use function static.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-16 10:35:54 +08:00
Zide Chen
8925eb5647 hv: set guest segment base to zero if VCPU does not start in real mode
In non real mode, for segment registers other than CS, the guest segment
base should be zero, otherwise the guest's segmentation results in wrong
effective addresses.

Linux boots with the wrong segment registers (base address in hidden part),
because it happens that it assigns the segment registers before using any
of them, which effectively reloads the segment base addresses from GDT.
2018-07-16 10:35:25 +08:00
Yonghua Huang
b831120165 HV: coding style cleanup for TRACE_2L & TRACE_4I usage
to align the data type of parameters

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-07-16 10:32:14 +08:00
Huihuang Shi
680c64de13 HV:transfer vmid's type to uint16_t
vmid's type prefered to be uint16_t.

V1->V2:vmid from uint32_t transfer to uint16_t
V2->V3:add range check to hcall's vmid parameter
V3->V4:seperate the declaration and actual code.
V4->V5:remove range check from hcall's vmid parameter

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 14:13:38 +08:00
Shiqing Gao
cb0009f4d2 hv: cpu: fix 'Pointer arithmetic is not on array'
Use the array for lapic_id directly to avoid the unnecessary pointer
arithmetic.

With current implementation,
  lapic_id_base is always a byte array with CPU_PAGE_SIZE elements

What this patch does:
 - replace 'uint8_t *lapic_id_base' with 'uint8_t
   lapic_id_array[CPU_PAGE_SIZE]' to make the boundary explicit
 - add a range check to ensure that there is no overflow

 v2 -> v3:
 * update the array size of lapic_id_array per discussion with Fengwei

 v1 -> v2:
 * remove the unnecessary range check in parse_madt in cpu.c

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 13:08:05 +08:00
Kaige Fu
44a175e4fe HV: instr_emul: Add new function vie_update_rflags
There are some duplicate codes in emulate_xxx functions which update rflags and
it deserves a common function to deal with the situation. So, this patch
introduces a new function vie_update_rflags to updating rflags accordingly.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-13 13:07:24 +08:00
Kaige Fu
2f3eb6723d HV: Remove SIB decode related code in decode_modrm
We will decode SIB in decode_sib after decode_modrm. So, there is no need to
decode SIB related field in decode_modrm. This patch remove it.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-13 13:07:24 +08:00
Kaige Fu
0fbdf374a3 HV: instr_emul: Cleanup ASSERT
There so many ASSERT following the function vie_read_register and vm_get_seg_desc.
It's better to move the ASSERT to those two functions and make the code more
compact.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 13:06:22 +08:00
Huihuang Shi
e3302e87e8 HV:transfer vm_hw_logical_core_ids's type and rename it
rename vm_hw_logical_core_ids to vm_pcpu_ids
and changed the type to uint16_t.

V1->V2:rename the vm_hw_logical_core_ids

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 13:05:29 +08:00
Mingqiang Chi
1d628c640c hv:fix MISRA-C return value violation
1) Change these 5 APIs to void type:
   vcpu_inject_pf
   uart16550_calc_baud_div
   uart16550_set_baud_rate
   console_init
   ptdev_activate_entry
No need to return 'entry' for ptdev_activate_entry
since the input parameter is 'entry'.
2) no need to check return value for the caller
   such as sbuf_put/console_putc/serial_puts/serial_get_rx_data

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-07-13 13:04:39 +08:00
Xiangyang Wu
2a2adc76f6 HV:CPU:Fix a mistake introduced by MARCO replacing patch
Fixs: 7fd3c624 (HV:CPU:Constant values replace with
CPU MACRO)
There is a mistake in the previous MARCO replacing patch,
use CR4 value replaces CR0 MACRO.

Use CR0 value replaces CR0 MACRO.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-07-13 11:27:56 +08:00
Junjie Mao
e3452cf804 HV: vlapic: minimize explicit casts by adjusting types
To minimize explicit casts, this patch adjusts the types of function parameters
and structure fields related to vlapic and update the types in the internal
implementation accordingly.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 10:02:44 +08:00
Junjie Mao
e08a58ebe6 HV: vlapic: save complex expressions to local variables
Use local variables to hold struct members before using them, which helps us
avoid confusions from static checkers.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 10:02:44 +08:00
Junjie Mao
f05e2fc73b HV: vlapic: cleanup types in formatting strings
Make the type indicators in formatting strings aligned with the actual variables
passed.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 10:02:44 +08:00
Junjie Mao
6dd78d5ad1 HV: vlapic: convert loop variables to unsigned
Most loop variables in vlapic are used in unsigned contexts (include bitops,
arithmetic w/ other unsigned integers, etc). This patch refactors these loop so
the these variables can be unsigned.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 10:02:44 +08:00
Junjie Mao
87f2d4c042 HV: vlapic: add suffix 'U' when necessary
For constants used in unsigned contexts, a 'U' suffix is required per MISRA C
standard.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Dong Eddie <eddie.dong@intel.com>
2018-07-13 10:02:44 +08:00
Arindam Roy
4aa6cdacf7 HV: Fix missing brackets for MISRA C Violations
Patch 5 of 7
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-13 09:09:12 +08:00
Arindam Roy
d16d9e5751 HV: Fix missing brackets for MISRA C Violations
Patch 4 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-13 09:09:12 +08:00
Arindam Roy
82e0cdb808 HV: Fix missing brackets for MISRA C Violations
Patch 3 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-13 09:09:12 +08:00
Arindam Roy
dbfd0e5b67 HV: Fix missing brackets for MISRA C Violations
Patch 2 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-13 09:09:12 +08:00
Arindam Roy
88a3205d3c HV: Fix missing brackets for MISRA C Violations
Patch 1 of 7.
Added changes to make sure Misra C violations are fixed
for rules 11S and 12S.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-13 09:09:12 +08:00
Binbin Wu
b4fb261b18 hv: fix bug in some embedded assembly code in vmx
The patch fixes the issue when SOS can't boot using HV release version.

In current code, the assembly code for "sgdt" & "sidt" is not right.
The operand is output, not input.

Also, current code use "rdmsr" instruction to read MSR_IA32_SYSENTER_CS,
which doesn't sepcify the clobbered registers it uses.
This patch uses API msr_read to read MSR_IA32_SYSENTER_CS.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-12 17:32:51 +08:00
Shiqing Gao
194fd8ba1e hv: irq: fix 'Pointer arithmetic is not on array'
- Define the array for 'struct irq_desc' with its size
  The array size for 'struct irq_desc' is constant and will not be
   changed.

- Use array rather than a pointer to avoid the pointer arithmetic.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-12 17:32:09 +08:00
Victor Sun
401ffd1e39 HV: pm: cleanup for misra integral type violations
The patch fixes integral type related violations on HV pm part.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-12 17:31:11 +08:00
Qi Yadong
202bc541b6 HV: trusty: revise trusty_boot_param structure
Per new design of trusty memory allocation: VHM will reserve contiguous
memory for trusty when DM launch guest with trusty enabled. And OSloader
will relocate trusty to 511G directly and pass trusty's base/entry to HV
by trusty_boot_param when call HC_INIITIALIZE_TRUSTY.

So in this patch:
  1. Extend trusty_boot_param to support addr/entry above 4G.
  2. Remove size check for old version compatibility.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Zhu Bing <bing.zhu@intel.com>
2018-07-12 17:30:26 +08:00
Minggui Cao
4cab8b9cc5 HV: code cleanup as MISRA-C report for guest/vmsr
like: constant of unsigned int need add U/UL as surfix.
enum value can't use to give or compare with int directlly.
unsigned and signed mis-matched

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-12 17:27:53 +08:00
Ying Liu
fd81655e60 HV: add the missing brackets to loop body
MISRA-C requires the use of brackets, even when there is only one
statement in the loop body.

Signed-off-by: Ying Liu <ying2.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-12 17:27:29 +08:00
Kaige Fu
df038fc0db HV: vmx: Change variable field to uint32_t
With field defined as uint64_t, there are some implicit type conversions when
calling exec_vmwrite/read functions which takes a uint32_t for the first parameter.

This patch fixes it by change field to uint32_t.

v1 - > v2:
  - Keep the field as it is and change the defination of field to uint32_t.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-12 17:26:42 +08:00
Xiangyang Wu
4dc39fdb8e HV:treewide:Add 16-bit atomic operations and update vpid type
There are some integer type conversions reported by static
analysis tool for vcpu id, number of created vcpus, and
vpid, to reduce these type conversions, redesign vcpu id,
number of created vcpus, and vpid type as uint16_t as per
their usage, related 16-bit atomic operations shall be
added in HV.
MISRA C requires that all unsigned constants should have the suffix 'U'
(e.g. 0xffU), but the assembler may not accept such C-style constants.

Add 16-bit atomic add/dec/store operations;
Update temporary variables type and parameters type of
related caller;
Update vpid type as uint16_t;
Replace Macro with constant value for CPU_PAGE_SIZE.

Note: According to SDM A.10, there are some bits defined
in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID
instruction, these bits don't mean actual VPID, so
the vpid field in the data struct vmx_capability doesn't
be updated.

V1--V2:
	update comments for assembly code as per coding style;

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
2018-07-11 21:27:08 +08:00
Junjie Mao
a23549aa91 HV: build: make relocation-related code configurable
The relocation feature relies on the ld option "-z noreloc-overflow" which is
only available for binutils >= 2.27, while on Ubuntu 16.04 or older the default
version of binutils is 2.26.

This patch wraps the relocation code with a configurable macro and make it
undefined by default to avoid default build failures.

NOTE: This is just a hotfix. The code dropped with undefined CONFIG_RELOC needs
to be reviewed by the original author of this feature. Checks to the binutils
version will also follow up.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2018-07-11 19:18:26 +08:00
Abdul Rehman
057a384f8e HV: bug fix update RTE if trigger mode or polarity is updated
Signed-off-by: Abdul Rehman <abdulrehmanee010@gmail.com>
2018-07-11 11:12:03 +08:00
Mingqiang Chi
a9d04cc5ce [REVERT-ME]:handle discontinuous hpa for trusty
This is a temp solution to handle discontinuous hpa
when create/destroy secure world ept.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-07-11 11:11:24 +08:00
Yonghua Huang
5603afb2be HV: remove execute access attribute in trusty EPT table
- this patch is to prevent secure world(trusty) from
   fetching instructin from normal world memory.

 - copy valid PDPTEs from normal world EPT to secure
   world EPT, and remove 'IA32E_EPT_X_BIT' attribute in
   these entries.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-11 10:26:33 +08:00
Zide Chen
5cb9972919 hv: cleanup cpu.c and cpu.h
- move all relocatoin code from cpu.c and cpu.h to reloc.c and reloc.h
- no any logic changes

Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin fengwei <fengwei.yin@intel.com>
2018-07-11 10:25:16 +08:00
Zide Chen
6c9e451b41 hv: EFI can load Hypervisor to address other than COMNFIG_RAM_START
- UEFI: change __emalloc() function to allocate from any available memory
  under 4G
- Define CONFIG_RAM_START to the lowest possible address 1M, making sure
  HV can only be relocated to higher address

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin fengwei <fengwei.yin@intel.com>
2018-07-11 10:25:16 +08:00
Zide Chen
84d9da1d6a hv: build hypervisor as PIE (position-independent executable)
Build and link hypervisor with "-pie" and remove static linking so that
it generates .rela sections for relocation

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin fengwei <fengwei.yin@intel.com>
2018-07-11 10:25:16 +08:00
Zide Chen
92cd2612fc hv: fixup addresses in the c code for relocation
- Trampoline code doesn't have the same relocation delta with HV,
  Need to manually patch them when referenced from HV
- replace all references to CONFIG_RAM_START with the actual HV load
  address

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-07-11 10:25:16 +08:00
Zide Chen
bc8b3a40f8 hv: fixup addresses in the assembly code for relocation
In cpu_primary.S
- Assign %rsp in cpu_primary_start_64(), so we can call _relocate()
  before any references to the symbols that need to be patched
- Move lidtq instruction and the IDT fixup code after _relocate() call
- In code64 part, replace 'mov' with 'lea' for correct addressing
- No relocation is needed in code32 part

In trampoline.S:
- add trampoline_spinlock_ptr pointer, so we may be able to fixup
  trampoline code in HV

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-07-11 10:25:16 +08:00
Xiangyang Wu
f81fcf2f07 HV:MM:add 'U/UL' suffix for unsigned contant value
In the current memory module, there are many constatn value
without U/UL suffix, it is reported as MISRA C violations by
static analysis tool.

Add 'U/UL' suffix for unsigned contant value in memory module
as needed.

Note:In the most case, CPU_PAGE_SIZE(0x1000) is used as
unsigned integer contant value, so CPU_PAGE_SIZE is defined
as unsigned integer contant value, and it is safety converted
into unsigned long type according to MISRA C standard.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-11 09:23:03 +08:00
Jason Chen CJ
b3690987bd [REVERT-ME]: disable turbo mode
there is a bug for system hang on SBL bootloader after we enabled turbo mode.
so add tmp patch to disable turbo mode as the work-around.
after SBL fixed it, we revert this patch.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 16:37:40 +08:00
Mingqiang Chi
3fed57bb9f hv:fix return value violation in prepare_vm0
Check the return value for prepare_vcpu/start_vm

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 16:36:05 +08:00
Mingqiang Chi
f01e6efdf5 hv:fix return value violation in vmexit handler
Check return value for the called functions in vmexit handler

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 16:35:20 +08:00
Mingqiang Chi
2686fe76bc hv: no need to return error when inject GP
GP fault is a normal case,no need to return error.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 16:35:20 +08:00
Yang, Yu-chu
809eb9f6ca vioapic.c: Using suffix rather than casting
Using suffix "UL" rather than type casting 0xffffffff.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2018-07-10 15:56:16 +08:00
Xiangyang Wu
1185884b97 HV:treewide:Clean up field names of struct cpuinfo_x86
In the data struct cpuinfo_x86, some field names have
prefix x86, others don't have prefix.

In order to unify names, update field names of struct
cpuinfo_x86 as per its usage purpose, remove prefix x86.

V1-->V2:
	Resolve conflict in cpu.c by rebase command
V2-->V3:
        Remove track-on id as per jack's comments

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 13:24:55 +08:00
Junjie Mao
3956ce1596 HV: io: spell out explicit narrowing of integers
The MMIO/PIO write APIs in io.h always take a uint32_t value but may uses it as
8, 16 or 32-bit integers. This patch converts the prototypes to align with their
functionality.

The pointer conversion and assignment are splitted to separate statements to
prevent static checkers from being confused about the underlying types.

v1 -> v2:

    * Change the prototype of mmio-related functions, instead of keeping the
      explicit conversions internal. The addresses are kept void* since in most
      cases hva (in void*) is passed.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 13:10:10 +08:00
Yang, Yu-chu
e263d8ebb9 HV: No assignment inside while loop condition
The assigment should be done outside while loop condition. To fix
it, one assigment initializaion and update statement of for loop
have been applied. The only while loop reminds to avoid very long
for loop expression.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
2018-07-10 12:59:12 +08:00