Commit Graph

1534 Commits

Author SHA1 Message Date
Yin Fengwei
b01a81279a hv: add new function to get gva for MOVS/STO instruction
Drop the get_gla function and add
 - get_gva_di_si_nocheck
   get gva from ES:DI and DS(other segment):SI without
   check faulure case
 - get_gva_di_si_check
   get gva from ES:DI and DS(other segment):SI with failure
   case checked

TODO:
  - Save dst_gpa and src_gpa for instruction emulation phase
    use.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
8480c98053 hv: move check out of vie_calculate_gla
We will do check only during instruction decode phase.
vie_calculate_gla will be called both in instruction emulation
phase, we move the check out of vie_calculate_gla.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
54c254169d hv: remove unnecessary check for gva
According to SDM vol3 25.1.1
With VMX enabled, following exception will be handled by guest
without trigger VM exit:
 - faults based on privilege level
 - general protection due to relevent segment being unusable
 - general protection due to offset beyond limit of relevent segment
 - alignment check exception

ACRN always assume VMX is enabled. So we don't need to these check
in instruction emulation. But we need to do page fault related check.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
5663dd7d14 hv: extend the decode_modrm
If rm show there is no SIB following rm field, we should get
base_register info from rm.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yonghua Huang
3b6ccf0c91 HV: remove callbacks registration for APICv functions
- call these functions directly, no need to register
     callbacks.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:11:21 +08:00
Li, Fei1
93c1b07c1d hv: mmu: remove old map_mem
Now there is no one use it.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 11:10:26 +08:00
Li, Fei1
f3b825de9d hv: trusty: use ept_mr_add to add memory region
Use ept_mr_add to add memory region EPT mapping for trusty.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 11:10:26 +08:00
Li, Fei1
4bb8456de8 hv: ept: refine ept_mr_add base on mmu_add
Refine ept_mr_add base on mmu_add. The old map_mem could be removed
once this was done.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 11:10:26 +08:00
Li, Fei1
da57284ba5 hv: ptdev: simplify struct ptdev_msi_info
The virt_vector/phys_vector are only used for debugging.
Rename msix to is_msix.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:10:04 +08:00
Li, Fei1
2371839cad hv: ptdev: remove vector index from structure ptdev_msi_info
Since it's stored in source id already.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:10:04 +08:00
Li, Fei1
d8cc29b6ea hv: ptdev: check whether phys_pin is valid in add_intx_remapping
Then we don't need to check whether phys_pin is valid in others.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:10:04 +08:00
Li, Fei1
e8c0763de6 hv: ptdev: add source_id for ptdev to identify source
Then use the source id to lookup the ptdev remapping entry.
For msi interrupt ptdev: use bdf and vector_index to identify the id;
For intx interrupt ptdev: use pin and pin source to identify the id.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:10:04 +08:00
Zhi Jin
6367650a70 hv: debug: add the hypervisor NPK log
The npk_log is a log destination for the hypervisor, similar to the
console_log and the mem_log. It can be enabled/disabled/configured
by the SOS kernel via the hypercall HC_SETUP_HV_NPK_LOG.
The configuration includes:
1. Set the MMIO base address of the reserved NPK master.
2. Set the log level of the hypervisor NPK log.
After that, the npk_log can be enabled to write the hypervisor logs to
the MMIO address of the reserved NPK master with a simple header.

Signed-off-by: Zhi Jin <zhi.jin@intel.com>
Signed-off-by: Liu, Xiaojing <xiaojing.liu@intel.com>
Reviewed-by: CHEN Gang <gang.c.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:09:25 +08:00
Zhi Jin
3c6df9b70c hv: add mmio functions for 64bit values
Signed-off-by: Zhi Jin <zhi.jin@intel.com>
Reviewed-by: CHEN Gang <gang.c.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:09:25 +08:00
Zhi Jin
dcae438306 hv: add a hypercall for the hypervisor NPK log
The hypercall HC_SETUP_HV_NPK_LOG is added to enable/disable/configure
the hypervisor NPK log.

Signed-off-by: Zhi Jin <zhi.jin@intel.com>
Signed-off-by: Zhonghua Sun <zhonghua.sun@intel.com>
Reviewed-by: CHEN Gang <gang.c.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:09:25 +08:00
Li, Fei1
f4eef9710d hv: ptdev: simplify ptdev_intx_pin_remap logic
Since this interrupt pin is passed through to the guest, we could set
it as we like. There's no need a flag to emulate the masked status.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 09:07:26 +08:00
Yu Wang
a6c2065b2e hv: apicv: change the name of vapic to apicv
Remove the vapic name and unify to apicv.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Yu Wang
a0c625b85a hv: apicv: change the apicv related API with vlapic_apicv prefix
The apicv is one hardware acceleration feature of vlapic. All vlapic
APIs should keep vlapic_ as the prefix.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Yu Wang
74ff712085 hv: vlapic: local APIC ID related code cleaning up
From SDM Vol3 10.4.6:
Some processors permit software to modify the APIC ID. However, the
ability of software to modify the APIC ID is processor model specific.
Because of this, operating system software should avoid writing to the
local APIC ID register.

So to permit change APIC ID is not one *must* feature. Keep it simple,
we are also reject to modify it.

This patch does code cleaning up for LAPIC ID related emulation.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Mingqiang Chi
c43d0e4f01 hv:Changed several APIs to void type
Since these APIs always return 0,
change them to void type,
vcpu_set_cr0()
vmx_write_cr0()
vcpu_set_cr4()
vmx_write_cr4()
kick_notification()
tsc_deadline_handler()
dmar_fault_handler()
ptdev_interrupt_handler()

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-23 08:54:54 +08:00
Li, Fei1
b75a7df415 hv: vcpuid: disable some features in cpuid
We didn't emualte them well, so just disable them.
Here are PMU CPUID.0A, Intel RDT CPUID.0F and CPUID.10, Intel SGX CPUID.12,
Intel Processor Trace CPUID.14

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 08:54:27 +08:00
Shiqing Gao
42aaf5d46f hv: code clean up regarding to % and / operations
- Clean up some code regarding to % and / operations since bit
  operations are faster.
        x % 64U ---> x & 0x3fU
        x % 32U ---> x & 0x1fU
        x % 16U ---> x & 0xfU
        x % 8U  ---> x & 0x7U
        x % 4U  ---> x & 0x3U
        x % 2U  ---> x & 0x1U

        x / 64U ---> x >> 6U
        x / 32U ---> x >> 5U
        x / 16U ---> x >> 4U
        x / 8U  ---> x >> 3U
        x / 4U  ---> x >> 2U
        x / 2U  ---> x >> 1U
- Minor changes regarding to coding styles

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-22 15:37:53 +08:00
Binbin Wu
0c630d9003 dm: cmos: fix a logic error for read to clear range
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-22 14:04:34 +08:00
Shiqing Gao
3e598ebb28 hv: fix 'No definition in system for prototyped procedure'
Remove the functions without definition.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-08-22 13:11:25 +08:00
Yan, Like
65e01a0cd2 hv: pirq: use a bitmap to maintain irq use status
This commit replaces the "used" field of irq_desc with a bitmap to maintain
the irq use status to save memory and LOC, and improve the efficiency as well.

Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-22 12:52:43 +08:00
Yonghua Huang
e0d40feaa8 HV:refine 'apic_page' & 'pir_desc' in 'struct acrn_vlapic'
- update 'apic_page' field in 'struct acrn_vlapic',
   from pointer type to 'struct lapic_regs' type.

 - delete 'pir' and update 'pir_desc' to 'vlapic_pir_desc'
   type.

 - fix potential memory leak in 'vlapic_create()'
   should free allocated memory in case of registering
   mmio handler failure.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-08-22 12:52:07 +08:00
Yew, Chang Ching
17ef5076a4 ipu: virtio-ipu4 as default IPU DM
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Yew, Chang Ching <chang.ching.yew@intel.com>
Reviewed-by: Edwin Zhai <edwin.zhai@intel.com>
Reviewed-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-21 18:53:53 +08:00
Shiqing Gao
8924f6dabb hv: vmx: fix 'Array has no bounds specified'
MISRAC requires that the array size should be declared explicitly.

This patch fixes the issues caused by vm0_boot_context.

Fix pattern is like below:
   extern char start_of_ROM, end_of_ROM, start_of_FLASH;
   memcpy (& start_of_FLASH, & start_of_ROM, & end_of_ROM - &
start_of_ROM);

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-08-21 13:03:28 +08:00
Liang Yang
6988a17027 DM USB: xHCI: Change the default USB xHCI support to pass through.
So far, the xHCI mediator does not support USB HUB over usb pmapper. But
there are some USB touch devices integrated internal USB HUB, then
cause such touch models can't be supported. Will consider to re-enable
xHCI mediator by default once HUB support related patches get merged in
the near future.

Signed-off-by: Liang Yang <liang3.yang@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Binbin Wu<binbin.wu@intel.com>
2018-08-21 11:59:31 +08:00
Shiqing Gao
1017d91aa6 hv: treewide: fix 'Empty parameter list to procedure/function'
Use func(void) rather than func() for the function declaration and
definition based on MISRAC requirement.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-08-21 09:55:46 +08:00
Shiqing Gao
7a4dcfcc1a hv: treewide: fix 'Function prototype/defn param type mismatch'
Fix the parameter type mismatch between API declaration and definition.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-21 09:55:12 +08:00
Mingqiang Chi
752e311e11 hv:fixed MISRA-C return value violations
-- change send_start_ipi/do_copy_earlylog to void type
-- drop the return value for vcpu_queue_execption
   when inject GP/PF/UD/AC/SS

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-08-21 09:54:45 +08:00
Shiqing Gao
431ef57076 hv: vioapic: fix 'No definition in system for prototyped procedure'
Remove two APIs without definition

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-08-21 09:53:55 +08:00
Sainath Grandhi
b17de6a7e6 hv: Support HV console for multiple VMs - ACRN partition mode
ACRN in partition mode provides vUART for all VMs. This patch adds
support to add console redirection for multiple VMs.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-21 08:32:52 +08:00
Binbin Wu
b8c1fd6104 dm: pass vrpmb key via cmos interface
CMOS offset from 0x20 to 0x9F is used to store rpmb key information.
vsbl loader will init vrpmb key in CMOS when boot/reboot.
vsbl loader will not init vrpmb key during S3 resume.
vsbl will read vrpmb key via CMOS interface.
After reading, the key value is cleared in CMOS. So the key can only be
read once until next boot.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-20 12:55:37 +08:00
Wei Liu
c8c0e10a90 HV: enlarge the CMA size for uos trusty
sometimes, there would be CMA allocate failue when doing cycle rebooting android uos.
as there are different CMA clients, and android trusty need 16M contiguous memory,
32M CMA size may make this failure easy to come out.
This patch is to enlarge the CMA size to 64M, which mitigate the failure.

Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-20 11:15:10 +08:00
Mingqiang Chi
40fd8893b4 hv:fixed several return value violations
-- change two timer callbacks to void type
-- ignore the return value for add_timer
-- add (void) before several functions(memset/memcpy/
   vcpu_get_xxx)

v1-->v2:
   ignore the return value for add_timer
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-20 09:51:07 +08:00
Minggui Cao
b37008d74e HV: check secure/normal world for EPTP in gpa2hpa
for secure and normal world has different EPTP, in secure world,
it could trap to hypervisor and call gpa2hpa function. So it need
check if it is in normal or secure world for EPTP selection.

Detailed explanation from Yadong Qi <yadong.qi@intel.com>:
Currently, trusty OS does not handle interrupt, so when an interrupt
is delivering in trusty, trusty will set it to LAPIC IRR register by
inject self_ipi() and then call world_switch to switch to Android,
So android will receive/handle the interrupt properly.Since the
vLAPIC is enabled in ACRN, so when trusty try to inject self_ipi(),
APIC-ACCESS vmexit will happen. Then ACRN will do instruction
decode/emulation, so the GPA2HPA will fail since page walk is using
nworld_eptp. It is probability an issue.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-17 14:31:43 +08:00
Jason Chen CJ
10a4c6c7dc samples: let nuc uos only start with 1 cpu
there are only 2 CPUs on UP2 platform, so we can only start 1 cpu for
uos on UP2 platform.

as this is only an example script, user can modify the uos start CPU
number according his requirement.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-17 14:30:10 +08:00
Li, Fei1
709cd5749e hv: lib: add ffz64_ex
Add ffz64_ex to find the first zero bit in a uint64_t array.
Note: the API is lockless.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-17 14:27:12 +08:00
Yan, Like
538173838d hv: pirq: change the order of functions within irq.c
This commit changes the order of functions in arch/x86/irq.c, and internal
function names to make it looks cleaner, with no change within any function.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 14:25:52 +08:00
Yan, Like
a8cd6925fc hv: pirq: clean up irq handlers
There are several similar irq handlers with confusing function names and it's
not friendly to call update_irq_handler() to update a proper handler after
request_irq().

With this commit, a single generic irq handler is being used, in which, no lock
need to be acquired because our design could guarantee there is no concurrent
irq handling and irq handler request/free.
A flags field is added to irq_desc struct to select the proper processing flow
for an irq. Irqflags is defined as follows:
 IRQF_NONE       (0U)
 IRQF_LEVEL      (1U << 1U)       /* 1: level trigger; 0: edge trigger */
 IRQF_PT         (1U << 2U)       /* 1: for passthrough dev */

Because we have only one irq handler, update_irq_handler() should be replace by
set_irq_trigger_mode(), whichs set trigger mode flag of a certian irq.
Accordingly, the code where called update_irq_handler() need to be updated.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 14:25:52 +08:00
Yan, Like
2c044e0c4e hv: pirq: refactor vector allocation/free
This commit refactors vector allocation/free codes, two functions are
defined to help alloc/free vectors for an irq:
- uint32_t alloc_irq_vector(uint32_t irq)
  - alloc a free vector (0x20 ~ 0xDF), and bind it to irq, for legacy irqs
    and static mapped irqs, vector has been allocated and bind, so just
    check the mapping correctness;
  - return: valid vector on success, VECTOR_INVALID on failure.

- void free_irq_vector(uint32_t irq)
  - free vector allocated via alloc_irq_vector(), for legacy irqs and static
    mapped irqs, nothing need to do.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 14:25:52 +08:00
Yan, Like
1bf2fc342a hv: pirq: refactor irq num alloc/free
This commit refactors the alloc/free irq num, two functions are defined:
- uint32_t alloc_irq_num(uint32_t irq)
  - if irq is valid, mark the irq_desc as used; if it's IRQ_INVALID,
    alloc a free irq, or else do nothing;
  - return: irq num on success, or IRQ_INVALID on failure.

- void free_irq_num(uint32_t irq)
  - free the irq num allocated via alloc_irq_num();

And a global spinlock to protect it from concurrent allocation/free.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 14:25:52 +08:00
Yan, Like
f77d885d7e hv: pirq: clean up unnecessary fields of irq_desc
This commit cleans up fiels of struct irq_desc:
- remove name, irq_desc_state, irq_cnt and irq_lost_cnt which are not used.
- remove irq_ prefix of irq_lock field of struct irq_desc;
- change enum irq_state to enum irq_use_state;

Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Li, Fei <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 14:25:52 +08:00
Mingqiang Chi
bdcc3aef22 hv: fixed compiling warning
removed some unnecessary variables and functions.

v1-->v2:
   Replace div-by-zero with an inline ASM code

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 12:36:53 +08:00
Shiqing Gao
40745d90c5 hv: vuart: fix the data type violations
- Fix the data type violations based on MISRA-C requirements
- Add '-fsigned-char' in Makefile to let the compiler treats 'char' be
   signed, like 'signed char'.
  Otherwise, the static checker treats 'char', 'signed char' and 'unsigned
   char' as three different types.
- Fix some minor coding style issues, such as TAB issues, line over 80
   characters issues and comments style

v1 -> v2:
 * fix the violation regarding to 'fifo_getchar'

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-17 11:19:45 +08:00
Liang Yang
d82a86e648 DM USB: xHCI: enable USB xHCI emulation in LaaG and AaaG.
Change launch_uos.sh to enable USB xHCI full emulation support.

Signed-off-by: Liang Yang <liang3.yang@intel.com>
Signed-off-by: Xiaoguang Wu <xiaoguang.wu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Binbin Wu<binbin.wu@intel.com>
2018-08-17 11:18:23 +08:00
Sainath Grandhi
150b389120 hv: fix size issue in mptable guest copy - ACRN partition mode
1)Fix to take into account the size of proc entries in MPtable.
2)Change APIC ids to virtual APIC IDs

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-17 10:06:38 +08:00
Sainath Grandhi
0c93a1388c hv: sw_loader for VMs in ACRN partition mode
ACRN in partition mode needs to boot VMs from HV. This patch make ACRN
treat all VMs in the same way (as vm0)  w.r.t. setting up the guest memory
for kernel, bootargs and zeropage

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-17 10:04:51 +08:00