Commit Graph

1227 Commits

Author SHA1 Message Date
Li, Fei1
f582556865 hv: instr_emul: add const qualifier for some function
Add `const` qualifier for is_desc_valid and vie_calculate_gla

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 21:53:41 +08:00
Li, Fei1
5e38e0ffd6 hv: instr_emul: refine decode_prefixes to one exit point
Misra C requires Function must have only one return entry.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 21:53:41 +08:00
Li, Fei1
433a492a4e hv: instr_emul: remove goto in get_gva_di_check
remove goto statement in get_gva_di_check() routine

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 21:53:41 +08:00
Li, Fei1
cd85115ec9 hv: instr_emul: refine vie_calculate_gla to void
It always return zero, so there is no need to check the return vaule from it.
Just refine it to void.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 21:53:41 +08:00
Huihuang Shi
11f0f72627 hv:fix violations
fix
1."Value is not of appropriate type."
2."Function prototype/defn param type mismatch"

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 16:52:28 +08:00
Victor Sun
404fd9c935 HV: rename cb2_dnv to dnv_cb2
This will be consistent with naming of apl-mrb/kbl-nuc ...

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 10:55:14 +08:00
Shiqing Gao
e2971ebc98 hv: vlapic: code clean-up
* rename `vlapic_set_intr_ready` to `vlapic_accept_intr`
 * replace calling of `vlapic_intr_edge` with `vlapic_set_intr`
 * remove `vlapic_intr_level` and `vlapic_intr_edge`

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-11 09:44:10 +08:00
Mingqiang Chi
1fc10d514c hv:Unify the MACRO name for invalid interrupt pin
There are the following definitions in hypervisor,
  define IOAPIC_INVALID_PIN      0xffU
  define VPIC_INVALID_PIN        0xffU
  define PTDEV_INVALID_PIN       0xffU
this patch unify them to:
  define INVALID_INTERRUPT_PIN   0xffffffffU

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-01-10 23:52:25 +08:00
Mingqiang Chi
49166fc3ac hv: passthrough: Change interrupt pin to uint32_t
-- Change the type from uint8_t to uint32_t
-- Remove some typecast
-- Change union source_id

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-10 23:52:25 +08:00
Mingqiang Chi
196912fb6d hv: ioapic: Change interrupt pin to uint32_t
Change the type from uint8_t to uint32_t for interrupt pin

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-10 23:52:25 +08:00
Zide Chen
10db11b00a hv: emulate IA32_FEATURE_CONTROL MSR
All features controlled by IA32_FEATURE_CONTROL are disabled from guests,
so set the Lock bit to prevent it from writing by guests.

Also hide the MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX bit from guest.

Tracked-On: #1867
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-10 12:23:44 +08:00
Li, Fei1
40c5139ea3 hv: inst_emul: clean the "Procedure has more than one exit point"
Misra C requires Function must have only 1 return entry.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-01-10 09:16:54 +08:00
Huihuang Shi
625e51d18a fix "goto detected:exception_inject"
V1->V2:
    rename is_exception_inject to has_exception.
V2->V3:
    remove the else statement and add new if statement to check
has_exception.

Misra C requires not allowed to use goto.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-09 23:06:25 +08:00
Zide Chen
86526cddc5 hv: disable more features from guest CPUID
Silicon Debug Feature: CPUID.01H.ECX[11]
- We can't allow guests to have direct access to silicon wide resources.

Machine Check Exception: CPUID.01H.EDX[5]
- Need HV support before exposing it to the guests.

Perfmon and Debug: CPUID.01H.ECX[15]
Debug Store: CPUID.01H.EDX[21], CPUID.01H.ECX[2], CPUID.01H.ECX[4]
- HV emulation is needed to separate host and guest monitoring data.
- guest CPUID.0AH is forced to all-zero in ACRN so it makes sense to clear
  these bits as well.

Tracked-On: #1867
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-09 23:04:41 +08:00
Huihuang Shi
e966828cd2 hv: clean the "Procedure has more than one exit point".
Misra C requires Function must have only 1 return entry.
Fixed it by use "if ... else ..." format.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-08 14:47:01 +08:00
Mingqiang Chi
7907fef59e hv:Rename several APIs for vpic and vioapic
vpic:
   vpic_set_irq         --> vpic_set_irqline
   vpic_get_irq_trigger --> vpic_get_irqline_trigger_mode
vioapic:
   vioapic_set_irq_nolock --> vioapic_set_irqline_nolock
   vioapic_set_irq        --> vioapic_set_irqline_lock
   vioapic_send_intr      --> vioapic_generate_intr

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-01-08 14:32:20 +08:00
Shiqing Gao
272439d37f hv: rename register_io_emulation_handler
This patch renames `register_io_emulation_handler` to
`register_pio_emulation_handler`.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-08 11:28:13 +08:00
Minggui Cao
c5e072432a HV: modularization to refine boot/bsp related code.
1. add static for local functions and variables.
2. move vm_sw_loader from vcpu to vm
3. refine uefi.c to follow the code rules.
4. separate uefi.c for vm0 boot and bsp two parts. bsp layer just
access native HW related, can't access vm/vcpu, vm0 boot part can
access vm / vcpu data structure.

Tracked-On: #1842
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-01-08 08:46:15 +08:00
Mingqiang Chi
09ff94fc49 hv:Change structure boot_cpu_data to static
-- Change boot_cpu_data to static, only used in cpu_caps.c,
-- Add get_cpu_info() api, it will call this api instead of
   boot_cpu_data except cpu_caps.c

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-01-07 11:23:22 +08:00
Mingqiang Chi
7c4dd0d277 hv:Move pm state structure to pm.h
-- move structure 'cpu_state_info' from cpu_caps.h to host_pm.h
-- add get_cpu_pm_state_info() api

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-01-07 11:23:22 +08:00
Zide Chen
f4cce46605 hv: disable SMX (Safer Mode Extension) from guest CPUID
SMX should be disabled on guests.

Actually current code assumes SMX is disabled (no VM exit handler for GETSEC
and bit 2 of IA32_FEATURE_CONTROL is set), and this patch simply explicitly
clear guest CPUID.01H.ECX[6].

Since both CPUID.01H.ECX[5] and CPUID.01H.ECX[6] are cleared from guest CPUID,
MSR IA32_SMM_MONITOR_CTL is not available in guests.

Need to make sure CR4.SMXE is cleared in guests.

Tracked-On: #1867
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-04 16:05:50 +08:00
Zide Chen
a4b166d5e8 hv: add missing MSRs to unsupported_msrs[]
SMRR (System-Management Range Register) is disabled from vMTRR,
so treat IA32_SMRR_PHYSBASE and IA32_SMRR_PHYSMASK as unsupported.

IA32_SMBASE is available only when IA32_VMX_MISC[15] is set.

IA32_FIXED_CTR0/1/2 are available only when CPUID.0AH:EDX[4:0] is non-zero.

Intel Processor Trace feature has been disabled and the associated MSRs
need to be in unsupported_msr[] as well.

Tracked-On: #1867
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-04 16:05:50 +08:00
yuhong.tao@intel.com
97cb7d906e hv: virq: fix wrong coding style
hypervisor/arch/x86/virq.c missed a new line at:

if (bitmap_test_and_clear_lock(...)) { vioapic_update_tmr(vcpu);

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2019-01-04 11:10:30 +08:00
Chaohong guo
8ed393a03d HV: remove multi-returns in few routine in guest.c
To meet MISRA, remove multi-returns in routines

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-03 15:58:10 +08:00
Chaohong guo
e2c11c0c75 HV: remove multi returns in vlapic_set_apicbase
remove few calls to return statement in routines.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-03 15:58:10 +08:00
Chaohong guo
9efbdc829d HV: Remove goto in vlapic_read()
remove goto statement in vlapic_read() routine

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-03 15:58:10 +08:00
Chaohong guo
7a04db7cd8 HV: remove multiple exits in vlapic_set_intr_ready()
To meet MISRA, remove multiple return in the func.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-03 15:58:10 +08:00
Tw
b7fda27427 config: fix no serial output with SBL on UP2
SBL doesn't support 40-pin header for now, so the serial PCI
device(0:18:1) on it doesn't work. Let's just workaround this by
changing hv's default serial output device to 0:18:0. In the future,
we'd rather change it back if SBL supports it.

This change is only for SBL, for UEFI, now we offer serial configuration
through command line parameter(vuart=...).

Tracked-On: #1995
Signed-off-by: Tw <wei.tan@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
2019-01-03 13:01:07 +08:00
Chaohong guo
0884397361 HV: cycomatic complexity 20 in vlapic_icrlo_write_handler
MISRA compaint that the vlapic_icrlo_write_handler 's cyclomatic
complexity is greater than 20. Try to remove multiple returns/exits.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
eaa0e307b7 HV: remove multiple exit/return in routines in the file of vlapic.c
To meet MISRA, remove few return in routines of vlapic.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
8e00180c9f HV: Remove goto statement in guest.c
To meet MISRA, remove some goto statements in guest.c

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
2e01b4c8dc HV: trival changes to meet MISRA
add @pre for routines and bracks for condition checking in vlapic.c

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
971eb84c20 HV: add const qualifier for functions' argments in vlapic.c
If a argment is not changed in function, MISRA recommends to add const
qualifier for that argement.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
63eecf084e HV: remove multiple return statement in get_vcpu_paging_mode() routine
To meet MISRA, remove multiple return in get_vcpu_paging_mode() routine.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
b4b9ac593a HV: remove few return statement in while loop of copy_gva function
The coding style of multiple returns/exit in while loop is not MISRA
compatible. Remove the returns in while loop.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
5a583fb87c HV: move global variable into the scope of calling function
The static global variable apicv_apic_access_addr is used only by
vlapic_apicv_get_apic_access_addr(), to remove the warning by MISRA,
move it into function scope.

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
Chaohong guo
235eaf057d HV: APICBASE_RESERVED definition is not used by any code. Just remove it
To meet MISRA standard, remove unused micro definition

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 16:22:11 +08:00
yuhong.tao@intel.com
7a930d8833 hv: virq: refine hypervisor/arch/x86/virq.c
The MISRA-C Standards suggests use brackets to clarify the precedence
order of logical conjunctions.

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2019-01-02 12:49:44 +08:00
Minggui Cao
537adaeb46 HV: cleanup CONFIG_COM_IRQ related code
move CONFIG_COM_IRQ code into vuart, because it is just
used for vuart.

Tracked-On: #2170
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 12:15:53 +08:00
Minggui Cao
fde0bcc1ce HV: disable vuart when dbg uart is disabled
vuart it used for SOS to output log to HV console,
so if dbg uart is disabled, it need be disabled too:
just unregister its PIO.

Tracked-On: 2170
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-02 12:15:53 +08:00
Li, Fei1
860c444c55 hv: coding style: add const qualifier for some function
Add `const` qualifier for lookup_address and find_vcpuid_entry.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-01-02 09:35:00 +08:00
Binbin Wu
067273af18 hv: assign: fix remaining MISRA-C violations
This patch fixes the remaining MISRA-C violations in arch/x86/assign.c

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-29 10:32:09 +08:00
Yan, Like
1dfd05cdac hv: fix mis-usage of "PAGE_SHIFT"
Replace PAGE_SHIFT with MSI_ADDR_DEST_SHIFT in ptirq_build_physical_msi(), since it's not correct in semantics.

Tracked-On: #2209
Signed-off-by: Yan, Like <like.yan@intel.com>
2018-12-28 23:46:49 +08:00
Mingqiang Chi
5c6fe01c87 hv:Change pcpu_active_bitmap to static
-- Change pcpu_active_bitmap to static, only used in
   cpu.c
-- add get_pcpu_active_bitmap()

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-28 23:26:31 +08:00
Mingqiang Chi
682824de6d hv:Change phys_cpu_num to static
-- change phys_cpu_num to static
-- add get_pcpu_nums() and is_pcpu_active() APIs
-- replace phys_cpu_num with get_pcpu_nums() except cpu.c

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-28 23:26:31 +08:00
Shuo A Liu
952943c3ea hv: decouple IO completion polling from idle thread
IO completion polling will access vcpu and vm structs. If doing it in
idle thread, there might be some race issues between vm destroying and
idle thread. They are running on different cores.
Got suggestion from Fengwei, decouple the polling action from idle
thread and just do it in vcpu thread, then we can guarantee idle thread
in really idle status.

Tracked-On: #1821
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-12-27 12:35:40 +08:00
Shuo A Liu
e8ac97671f hv: use asm_pause() to replace inline ASM to satisfy MISRAC
pause_cpu() --> asm_pause()
hlt_cpu() --> asm_hlt()
inline ASM pause --> asm_pause()

Tracked-On: #1821
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-27 12:35:40 +08:00
Binbin Wu
21aa1907fd hv: vcpuid: cpuid leaf 07h has subleaf
Two changes:

1. cpuid leaf 07h has subleaf:
According to SDM 3-194 Vol.2A, Table 3-8, cpuid leaf 07h has sub-leaves.
cpuid.07.eax reports the maximum input for sub-leaves.
Since there is no definition for subleaf > 0 in SDM, hv only supports subleaf 0.

2. In currently hv code, cpuid leaf function 14h is disabled,
CPUID.07H:EBX.INTEL_PROCESSOR_TRACE should be disabled as well.

Tracked-On: #2198
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2018-12-27 09:05:12 +08:00
Yonghua Huang
55691aed46 hv: fix coding style violations in mmu.c
Fix violations that attempt to change parameter
 passed by value.

Tracked-On: #2056
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-26 14:17:24 +08:00
Kaige Fu
1274fca008 HV: x86: Fix "Variable should be declared static"
This patch mainly do the following:
  - Make pic_ioapic_pin_map static const by MISRA-C's requirement.
  - Make legacy_irq_to_pin and legacy_irq_trigger_mode static const as we will never change it.

Tracked-On: #861
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2018-12-26 13:47:51 +08:00
Tw
1dee629e75 hv:vtd: fix additional violations in vtd.c
this patch fix following violations:
- Use of single line comment(s).
- Logical conjunctions need brackets.
- More than one break or goto statement in loop.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2018-12-26 10:56:16 +08:00
Yonghua Huang
3998c97756 HV: [v2] bugfix in 'hv_access_memory_region_update()'
- bugfix:the actual 'size' of memory region that
    to be updated is incorrect.

  - replace CONFIG_UEFI_STUB with DMAR_PARSE_ENABLED
    when update memory pages for ACPI_RECLAIM region,
    as DMAR_PARSE_ENABLED may be enabled on non-EFI
    platform.

V2 update:
    wrap roundup to 2M and rounddown to 2M inline
    functions.

Tracked-On: #2056
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-12-25 22:06:02 +08:00
Shiqing Gao
7016244c22 hv: io: fix MISRA-C violations related to break
This patch fixes the MISRA-C violations in arch/x86/io.c
 * make the for loop have only one `break`

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-25 15:31:38 +08:00
Binbin Wu
68643b619f hv: vcpuid: leaf 0dh is percpu related
cpuid leaf 0dh is percpu related, no need to init in vcpuid_entries for vm.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-25 14:55:42 +08:00
Yonghua Huang
ea672c5b07 hv: update coding style for tampoline.c
- add API get trampoline_start16_paddr() instead
    of exporting this global variable.
  - other minor update.

Tracked-On: #2095
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-25 13:25:14 +08:00
yuhong.tao@intel.com
b89b12280c hv: virq: refine acrn_handle_pending_request() has more than one exit point
The MISRA-C Standards suggests procedures to be single exit

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-12-25 13:14:19 +08:00
yuhong.tao@intel.com
e692d4c721 hv: virq: refine acrn_handle_pending_request() use goto instruction
The MISRA-C Standards suggests not to use 'goto' instruction.

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-12-25 13:14:19 +08:00
Sainath Grandhi
ef03385f42 hv: Write Buffer Flush - VT-d
This patch does the following changes
According to VT-d spec Section 6.8 "Write Buffer Flushing" DRAM write buffers
are flushed implicitly upon Remapping Hardware Caches Invalidation even on
platforms that set RWBF to 1 in capability register. So removed write buffer
flushing as current ACRN issues cache invalidation commands in all cases.

Tracked-On: #1855
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-12-24 22:18:30 +08:00
Shiqing Gao
a5113d922d hv: remove duplicated is_vmx_disabled
This patch fixes the duplicated functions introduced by cpu caps
modularization.

In cpu caps modularization, function `is_vmx_disabled` was supposed
to be moved from `arch/x86/vmcs.c` to`arch/x86/cpu_caps.c`,
but the original one was not removed.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-24 14:04:55 +08:00
Huihuang Shi
1b37ed50d8 hv: vmcall: fix "goto detected" violations
Remove the goto by split the function into two,
dispatch_hypercall and vmcall_vmexit_handler.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-24 09:57:43 +08:00
yuhong.tao@intel.com
88a7d8b2cc hv: virq: refine vcpu_inject_hi_exception()
The MISRA-C Standards suggests use brackets to clarify the precedence
order of logical conjunctions.

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-12-23 22:32:51 +08:00
yuhong.tao@intel.com
3bfa695565 hv: virq: refine vcpu_inject_vlapic_int() has more than one exit point
The MISRA-C Standards suggests procedures to be single exit.

Tracked-On: #861
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
2018-12-23 22:32:51 +08:00
Binbin Wu
c3250030aa hv: vcpuid: remove unnecessary check code
The removed check code is not necessary.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-21 19:44:20 +08:00
Binbin Wu
83f32c93f0 hv: vcpuid: leaf 02h has no subleaf, delete un-needed code.
According to SDM Vol. 2A 3-191 & Vol. 2A 3-213, leaf 02h has no subleaf.
This patch removes the un-needed code.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-21 19:44:20 +08:00
Li, Fei1
36dcb0f605 hv: lib: refine inline assembly use in bitmap operation
Try to minimize the C code in inline assembly function. Now only
construct data structure and return a value is permitted.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-21 19:39:56 +08:00
Shiqing Gao
ddd07b955b hv: cpu_state_tbl: fix multiple exits
This patch fixes the MISRA-C violations in arch/x86/cpu_state_tbl.c
 * make the function have only one exit point

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-21 16:19:09 +08:00
Shiqing Gao
eb77e25ff9 hv: ept: fix MISRA-C violations
This patch fixes the MISRA-C violations in arch/x86/ept.c
* add local variable if the input parameter passed by value
  is changed in function definition
* remove the duplicated semi colon

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-21 15:27:46 +08:00
Li, Fei1
738f2536fe hv: coding style: refine cpu related function to one exit
2) Fix procedure has more than one exit point.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-21 13:34:01 +08:00
Jason Chen CJ
9672538c85 init: move init_scheduler into cpu.c
now init_scheduler should belong to and move to hwmgmt module

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <edide.dong@intel.com>
2018-12-21 10:34:15 +08:00
Jason Chen CJ
ff0703dd40 scheduler: make scheduling based on struct sched_object
use struct sched_object as the main interface of scheduling, then
make scheduler as an independent module to vcpu:
- add struct sched_object as one field in struct vcpu
- define sched_object.thread for switch_to thread
- define sched_object.prepare_switch_out/in for prepare_switch before
  switch_to
- move context_switch_out/context_switch_in into vcpu.c as
  vcpu.sched_obj.prepare_switch_out/in
- make default_idle as global idle.thread for idle_thread
- make vcpu_thread as vcpu.sched_obj.thread for each vcpu thread
- simplify switch_to based on sched_object

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <edide.dong@intel.com>
2018-12-21 10:34:15 +08:00
Jason Chen CJ
8aae0dff87 scheduler: refine make_reschedule_request
just use pcpu_id for make_reschedule_request is enough

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <edide.dong@intel.com>
2018-12-21 10:34:15 +08:00
Jason Chen CJ
6d67364881 scheduler: refine runqueue related functions
add struct sched_object, and use it as input param instead of vcpu for
below functions:
- add_to_cpu_runqueue renamed from add_vcpu_to_runqueue
- remove_from_cpu_runqueue renamed from remove_vcpu_from_runqueue
- get_next_sched_obj added to get next sched object

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <edide.dong@intel.com>
2018-12-21 10:34:15 +08:00
Huihuang Shi
93e588bc7e hv: fix e820.c violations
fix e820.c violations related misra c.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2018-12-21 10:33:32 +08:00
Tw
60f78e1e70 hv:vtd: fix MISRA-C violations on procedure has more than one exit point
This patch fix MISRA-C violations in arch/x86/vtd.c
on Procedure has more than one exit point.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-21 10:32:53 +08:00
Tw
a98a1a690c hv:vtd: fix MISRA-C violations on pointer not checked for null before use
This patch fix MISRA-C violations in arch/x86/vtd.c
on Pointer not checked for null before use.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-21 10:32:53 +08:00
Tw
725e1921e5 hv:vtd: fix MISRA-C violations on comment possibly contains code
This patch fix MISRA-C violations in arch/x86/vtd.c
on Comment possibly contains code.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-21 10:32:53 +08:00
Tw
897ffa2739 hv:vtd: fix MISRA-C violations on logical conjunctions need brackets
This patch fix MISRA-C violations in arch/x86/vtd.c
on logical conjunctions need brackets.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-21 10:32:53 +08:00
Tw
80b392a854 hv:vtd: fix MISRA-C violations on pointer param should be declared pointer to const
This patch fix MISRA-C violations in arch/x86/vtd.c
on pointer param should be declared pointer to const.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-21 10:32:53 +08:00
Tw
5282fa899d hv:vtd: fix MISRA-C violations on scope of variable could be reduced
This patch fix the MISRA-C violations in arch/x86/vtd.c
on scope of variable could be reduced.

Tracked-On: #861
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-21 10:32:53 +08:00
Arindam Roy
bec21d147b Patch for modularising ioapic.[c/h] and related files.
This adds few functions to access the daata structures
defined inside ioapic.c. Removes the same data structures
from ioapic.h
Also this modifies some of the names of existing APIs to
conform to the ioapic module name.
Modified gsi_table identifier to gs_table_data, to avoid
a MISRA C Violation.

Tracked-On: #1842
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-12-21 09:58:25 +08:00
Shiqing Gao
50f5b0f6bb hv: vmexit: fix MISRA-C violations related to multiple exits
This patch fixes the MISRA-C violations in arch/x86/vmexit.c
 * make the function have only one exit point

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 23:05:13 +08:00
Li, Fei1
0a713e6fbc hv: coding style: refine set_vcpuid_entries to one exit
Fix procedure has more than one exit point.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-20 22:07:53 +08:00
Li, Fei1
a56abee9ff hv: coding style: refine find_vcpuid_entry
1) add local_find_vcpuid_entry to find whether a cpuid leaf exist
in vcpuid cache entries.
2) find_vcpuid_entry will return the found entry if local_find_vcpuid_entry
return is not null. Otherwise, call local_find_vcpuid_entry again
when necessary.
In this case, there could eliminate recursion in find_vcpuid_entry.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-20 22:07:53 +08:00
Minggui Cao
58d2a418d5 HV: fix pm code for multi-exits & unsigned const
1. change multi "return" to one exit.
2. add "U" to unsigned const as postfix.

Tracked-On: #861
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-20 21:56:48 +08:00
Li, Fei1
1c99a975ea hv: coding style: refine trusty
Refine the reminding part: fix procedure has more than one exit point.

Tracked-On: #2120
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-20 21:53:51 +08:00
Li, Fei1
1dca17cd29 hv: coding style: refine initialize_trusty to one exit
1) Move data copy out of initialize_trusty
2) Fix procedure has more than one exit point

Tracked-On: #2120
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-20 21:53:51 +08:00
Mingqiang Chi
81a9de6067 hv:fix MISRA-C violations in create_vm
-- fix "more than one exit point" and "goto detected" violations
-- change prepare_vm0_memmap to void type
-- Add free_vm_id when create vm failed

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-20 18:47:57 +08:00
Zide Chen
bb47184f3c hv: fix enable_msr_interception() function
Fixed three MISRA-C violations:
11S: No brackets to loop body
7C: Procedure has more than one exit point.
8D: DD data flow anomalies found.
  initialize read_map and write_map in the declaration statements.

Fixed one bug:
Use "msr <= 0x1FFFU" instead of "msr < 0x1FFFU" because 0x1FFF is a valid MSR
bitmap address.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-20 18:46:19 +08:00
Shiqing Gao
56af4332e3 hv: io: fix MISRA-C violations related to multiple exits
This patch fixes the MISRA-C violations in arch/x86/io.c.
 * make the function have only one exit point

v1 -> v2:
 * replace `ASSERT` with `pr_err`

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 18:45:21 +08:00
Shiqing Gao
c03bad1fef hv: io: fix MISRA-C violations related to style
This patch fixes the MISRA-C violations in arch/x86/io.c.
 * add the required brackets for logical conjunctions
 * add the required 'else' for 'if ... else if' case

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 18:45:21 +08:00
Li, Fei1
f27aa70fb5 hv: coding style: refine page related
1) Fix procedure has more than one exit point.
2) Add some brackets to make logical conjunctions more readable.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-20 15:44:08 +08:00
Binbin Wu
71a80d2d60 hv: assign: change ptirq vpin source type from enum to macro
This patch fixes the MISRA-C violations on implicit type conversion.
For ptirq vpin source type, there is no need to define a enum.
Remove enum ptirq_vpin_source.
Define two macro:
- PTDEV_VPIN_IOAPIC
- PTDEV_VPIN_PIC

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 13:43:47 +08:00
Binbin Wu
d5865632ec hv: assign: remove added ptirq entries if fails to add all
When adding ptirq entries, either successes with all number of entries added or
fails with none entries addes.
So remove added ptirq entries if error occurs during the process.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 13:43:47 +08:00
Binbin Wu
d48dc38780 hv: assign: fix MISRA-C violations on multiple exits
This patch fixs the MISRA-C violations in arch/x86/assign.c
on multiple exits.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-20 13:43:47 +08:00
Binbin Wu
e8b3e44fc0 hv: assign: fix MISRA-C violations on potential null pointer deference
This patch fix the MISRA-C violations in arch/x86/assign.c
on potential null pointer deference.
Also add a break in case statement.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 13:43:47 +08:00
Binbin Wu
e19dcf5735 hv: assign: fix MISRA-C violations on implicit type conversion
This patch fixes the MISRA-C violations in arch/x86/assign.c
on implicit type conversion.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 13:43:47 +08:00
Minggui Cao
23c2166aa9 HV: change serial PCI cfg to bus:dev.func format
before PCI_BDF uses its hex value like "0xC2" for "0:18.2" to
configure, now use "0:18.2" directly to make it more readable
and easier to configure.

Tracked-On: #2031
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-20 10:11:02 +08:00
Yan, Like
530388db30 hv: irq: fix MISRA-C violations in irq.c and idt.h
This commit fixed following violations:
- Procedure has more than one exit point: free_irq_vector/request_irq/dispatch_interrupt
- goto detected: dispatch_interrupt
- Pointer param should be declared pointer to const: fixup_idt
- basic type declaration used: fixup_idt

Tracked-On: #861
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 09:09:31 +08:00
Yan, Like
08cf8f648c hv: lapic: fix MISRA-C violation of potential numeric overflow
This patch fixes the MISRA-C violations in arch/x86/lapic.c, change local variable from
uint32_t to uint64_t to avoid potential numeric overflow.

Tracked-On: #861
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-20 09:09:31 +08:00
Li, Fei1
38c117841f hv: coding style: refine mmu.c
1) Separate ASM and C code inserts as pure procedures with a defined interface.
2) Fix procedure has more than one exit point.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-19 15:11:31 +08:00