This patch implements relocation support for ACRN RISC-V to enable
position-independent execution. The hypervisor can now be loaded at any
physical address and will automatically relocate itself at runtime. Key
changes:
- Add relocate() function to process R_RISCV_RELATIVE relocations in
.rela sections during early boot
- Implement arch_get_hv_image_delta() to calculate the load address offset
from the configured base address
- Add relocation processing in cpu_entry.S before jumping to C code
- Update linker script to include .rela sections for relocation data
- Define R_RISCV_RELATIVE relocation type and linker symbol definitions
Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
add BSP and AP initialization function.
and call uart16550_init to update uart_base_address
after init paging.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
riscv only need to map mmio and hv owned memory, donot
need to map guest memory. And need detection for svpbmt extension
to support page table defined memory attribute programming.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add functions get_board_hv_device_start/get_board_hv_device_size
to get mmio device start address and size. These are needed to be
generated by config tool or runtime parsing DTS, wrap the method
here.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
this patch calculate riscv static pages number for page pool.
riscv donot need to map guest memory. use link script address
label to map code size.
For risc-v:
1) if the platform doesn't support PCIe devices
The address space layout for risc-v is like
| |
| MMIO |
| |
| ... |
| |
| RAM |
| |
For all its address space, one 1GB page table is enough which cover 512G
For MMIO or RAM, if its start address and end address is 1G aligned, there's no 2M
or 4K page table is needed. if their address are not 1G aligned, two 2M page table
is enough for MMIO or RAM. The issue here is that if we neetid 4K page entries for
different page attributes. So we need to reserve enough 4K page tables for that requirement.
2) if the platform support PCI devices, for the low MMIO range, another two 2MB page
table may needed. for the high MMIO range, its depends on the max physical address bits of
the platform and the high MMIO range reserved by the BIOS.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add hypervisor pagetable manipulate interface to riscv arch directory,
which is needed by the common interface, and add riscv ppt pgtable
structure implementation.
Tracked-On: #8831
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: hangliu1 <hang1.liu@intel.com>
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move some funcitons like hpa2hva to common file.
change some files to include file from asm/pgtable.h to common/pgtable.h
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
For now, BOARD should use the qemu-riscv for risc-v.
For RISC-V:
make hypervisor BOARD=qemu-riscv SCENARIO=shared ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-
For x86:
make hypervisor BOARD=qemu SCENARIO=shared [ARCH=x86]
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Now doesn't want introduce the PCI module since PCI CFG access should be arch
special.
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
get_vm_from_vmid,is_paused_vm and is_poweroff_vm should be common APIs.
But now doesn't implement them as common for not introduce more VM related
data structure and APIs.
Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
send_single_ipi/send_dest_ipi_mask are calling sbi_send_ipi. According
to SBI spec:
- uint64_t hart_mask is a scalar bit-vector containing hartids
- uint64_t hart_mask_base is the starting hartid from which the
bit-vector must be computed
Logical pCPU ID and pCPU ID mask need to be converted to physical hart
ID mask and physical hart ID base.
Tracked-On: #8811
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
init sched and call run_idle_thred in init_pcpu_comm_post to switch to idle
thread after AP initialization finish.
Tracked-On: #8812
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
implement arch_cpu_dead and arch_cpu_do_idle for riscv, arch_cpu_dead and
arch_cpu_do_idle will be called by common module.
Tracked-On: #8812
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch calls timer_init() to initialize timer for
pcpu on risc-v platform.
Tracked-On: #8816
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Convert IRQ-related macros to static inline functions and introduce
wrappers for arch-specific implementations. This follows the style we
defined for multi-arch development.
This is a follow-up update for commit
a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h").
CPU_IRQ_ENABLE_ON_CONFIG -> local_irq_enable
CPU_IRQ_DISABLE_ON_CONFIG -> local_irq_disable
CPU_INT_ALL_DISABLE -> local_irq_save
CPU_INT_ALL_RESTORE -> local_irq_restore
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
This patch implements interrupt initialization and the basic
exception/interrupt handling flow on RISC-V.
init_interrupt() needs to be invoked during CPU initialization to
set up the trap vector and enable the interrupt.
RISC-V exception and interrupt handling includes:
- Saving and restoring CPU registers around traps
- Implementing handlers for:
- Supervisor software interrupt
- Supervisor timer interrupt
- Halting the CPU for all other interrupts and exceptions
------
TODOs:
1. add support for registering interrupt handlers via request_irq() and
further adoption of the common IRQ framework.
2. add support for external interrupt.
Tracked-On: #8813
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Enable acrnlog (memory logging) in release builds, default log level
is still controlled by DEBUG_OPTIONS/MEM_LOGLEVEL in scenario file.
Tracked-On: #8805
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Without -fpie or -fno-pie specified in the CFLAGS and ASFLAGS, different
versions of riscv64-linux-gnu-gcc have different behavior, for example,
Ubuntu 13.3.0-6ubuntu2~24.04 will compile as if -fpie, but 15.1.0 will
compile as if -fno-pie. To make the build consistent specify -fpie when
CONFIG_RELOC=y and -fno-pie otherwize explicitly.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch adds the basic logics to bring up all APs in the C
entry of BSP boot. The mapping between logcial CPU IDs and physical
hart IDs is setup based on the pre-generated data from config tool
by parsing the device tree. Logical CPU ID BSP_CPU_ID will always
map to the BSP hart ID. The per pCPU logic ID is saved in tp register.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Extension Zihintpause (Pause hint) is mandatory for RVA23. asm_pause
is implemented based on "pause" instruction.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Use tp register to hold the current logical CPU ID. This follows the
same design as x86 which uses MSR_IA32_SYSENTER_CS for the same purpose.
riscv uses SBI HSM to start the APs.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This is just for temporary build and should be reverted when
common debug module is integrated.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since there is no common IPI abstraction, the arch_ prefix is redundant.
This patch renames the functions as follows:
- arch_send_dest_ipi_mask -> send_dest_ipi_mask
- arch_send_single_ipi -> send_single_ipi
Tracked-On: #8799
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This patch implements risc-v specific timer codes. Basically,
risc-v adapts to acrn timer framework with some specific
behaviors. So far, it enables sstc support in h-mode.
Tracked-On: #8792
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Co-developed-by: Yong Li <yong.li@intel.com>
Signed-off-by: Yong Li <yong.li@intel.com>
Co-developed-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The following tasks are done for both BSP and APs:
- Mask all interrupts
- Disable FPU
- Setup stack
- Jump to the C entry of BSP/AP initialization
Additionally, clear BSS sections during BSP boot before
jumping to the C entry point.
Tracked-On: #8788
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Haicheng Li <haicheng.li@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the IPI for RISC-V using SBI interface.
There is no common IPI concept abstracted, due to the following reasons:
- RISC-V:
Software delivers an IPI to target CPUs via software interrupts.
The interrupt number is fixed for each privilege mode (e.g.,
Supervisor Software Interrupt = IRQ 1, Machine Software Interrupt = IRQ 3).
The actual purpose of the IPI is indicated by an IPI message type,
which is a software-level concept. When the IPI is received,
the target CPU must check the message type to determine the required action.
- x86:
Software delivers an IPI to target CPUs using a specific vector number.
During CPU initialization, software can assign dedicated vectors for
particular purposes. When the IPI is received, the target CPU could
directly invoke the handler bound to that vector.
Each architecture provides its own IPI implementation, and other SW modules
directly call these arch-specific functions.
------
Notes:
* To ensure RISC-V builds pass, an empty `include/arch/riscv/asm/cpu.h`
is added since `debug/logmsg.h` includes `asm/cpu.h`.
* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
Legacy SBI extensions are not supported in ACRN.
----------
Changelog:
* Updated commit message and code comments to state explicitly that
legacy SBI extensions are not supported in ACRN.
* Refined the prototype of sbi_send_ipi() to align with the SBI spec:
From: int64_t sbi_send_ipi(uint64_t mask)
To: int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
In ACRN it is invoked as sbi_send_ipi(dest_mask, 0UL), with mask_base
set to 0UL.
* Renamed send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() respectively.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the common SBI interfaces, including
sbi_ecall(), common macros and data structures.
Changelog:
* Renamed SBI_EXPERIMENTAL_x and SBI_VENDOR_x.
* Added description for sbi_ecall().
* Renamed SBI-related enums, macros, and data structures to align with
the SBI specification.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit adds riscv build skeleton and adds some dummy files that
prints out hello world.
To build riscv acrn.out/acrn.bin, simply:
make hypervisor \
BOARD=<any existing board> \
SCENARIO=<any existing scenario> \
ARCH=riscv
We still need to specify board and scenario as those were required by
project level makefile.
Tracked-On: #8782
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
