Commit Graph

1522 Commits

Author SHA1 Message Date
Binbin Wu
245a732055 hv: sgx: add basic support to init sgx resource for vm
Get the platform EPC resource and partiton the EPC resource for VMs
according to VM configurations.
Don't support sgx capability in SOS VM.
init_sgx is called during platform bsp initialization.
If init_sgx() fails, consider it as configuration error, panic the system.
init_sgx() fails if one of the following happens when at least one VM requests
EPC resource if no enough EPC resource for all VMs.
No further check if sgx is not supported by platform or not opted-in in BIOS,
just disable SGX support for VMs.

Tracked-On: #3179
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-29 11:24:13 +08:00
Yin Fengwei
c5cfd7c200 vm state: reset vm state to VM_CREATED when reset_vm is called
When we call reset_vm() function to reset vm, the vm state
should be reset to VM_CREATED as well.

Tracked-On: #3182
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-29 10:43:03 +08:00
Binbin Wu
b833e2f90c hv: vtd: fix a logic error when set iommu page walk coherent
Fix a logic error when set iommu page walk coherent.

Tracked-On: #3160
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-27 14:57:46 +08:00
Victor Sun
f2fe35472b HV: remove mptable in vm_config
Define a static mptable array and each VM could index its vmptable by
vm id, then mptable is not needed in vm configurations;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-27 12:13:37 +08:00
Binbin Wu
7e80a6eee3 hv: vm: enable iommu after vpci init
In current code, vpci do the pci enumartion and add pci devices to the
context table of iommu.
Need to enable iommu DMA address translation later than vpci init.
Otherwise, in UEFI platform, there will be a shot time that address translation
is enabled, but the context table is not setup.
For the devices active in UEFI environment will have problem on address translation.

Tracked-On: #3160
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-24 11:46:44 +08:00
Zide Chen
bfc08c2812 hv: move msr_bitmap from acrn_vm to acrn_vcpu_arch
At the time the guest is switching to X2APIC mode, different VCPUs in the
same VM could expect the setting of the per VM msr_bitmap differently,
which could cause problems.

Considering different approaches to address this issue:
1) only guest BSP can update msr_bitmap when switching to X2APIC.
2) carefully re-write the update_msr_bitmap_x2apic_xxx() functions to
   make sure any bit in the bitmap won't be toggled by the VCPUs.
3) make msr_bitmap as per VCPU.

We chose option 3) because it's simple and clean, though it takes more
memory than other options.

BTW, need to remove const modifier from update_msr_bitmap_x2apic_xxx()
functions to get it compiled.

Tracked-On: #3166
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-24 11:37:13 +08:00
Victor Sun
f96ae3f106 HV: enforce Cx of apl nuc with SPACE_SYSTEM_IO
APL NUC would expose different MWAIT support status with different
BIOS configuration, then the acpi idle driver would have problem if
we provide MWAIT Cx data only. Now we will enforce guest enter port
IO Cx even BIOS expose support of MWAIT.

Given all Broxton family share same port IO Cx data, we use a unified
struct cpu_cx_data cx_bxt[] for all Broxton SoCs;

Tracked-On: #3158

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-24 11:36:54 +08:00
Victor Sun
1fe5711170 HV: validate pstate by checking px ctl range
The previous function just check the pstate target value in PERF_CTL msr
by indexing px data control value which comes from ACPI table, this would
bring a bug in the case that guest is running intel_pstate_driver:
the turbo pstate target value from intel_pstate driver is in a range
instead of fixed value in ACPI _PSS table, thus the turbo px request would
be rejected. This patch fixed this issue.

Tracked-On: #3158

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-24 11:36:54 +08:00
Victor Sun
57275a58b3 HV: add px cx data for kbl nuc refresh
Add Px/Cx data of Intel Core(TM) i7-8650U CPU which used by NUC7i7DNH to
enable guest controlled CPU power states;

Tracked-On: #3158

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-24 11:36:54 +08:00
Mingqiang Chi
04ccaacb9c hv:not allow SOS to access prelaunched vm memory
filter out prelaunched vm memory from e820 table
and unmap prelaunched vm memory from ept table
before boot service OS

Tracked-On: #3148
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-05-23 19:01:48 +08:00
Zide Chen
5a23f7b664 hv: initial host reset implementation
- add the GUEST_FLAG_HIGHEST_SEVERITY flag to indicate that the guest has
  privilege to reboot the host system.

- this flag is statically assigned to guest(s) in vm_configurations.c in
  different scenarios.

- implement reset_host() function to reset the host. First try the ACPI
  reset register if available, then try the 0xcf9 PIO.

Tracked-On: #3145
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-23 18:24:17 +08:00
dongshen
a6503c6af3 HV: remove function pci_pdev_foreach()
And make other related changes accordingly:
 Remove pci_pdev_enumeration_cb define
 Create init_vdevs() to iterate through the pdev list and create vdev for each pdev
 Export num_pci_pdev and pci_pdev_array as globals in header file

Minor cosmetic fix:
 Remove trailing whitespace

Tracked-On: #3022
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-05-23 14:06:51 +08:00
Sainath Grandhi
536c69b9ff hv: distinguish between LAPIC_PASSTHROUGH configured vs enabled
ACRN supports LAPIC emulation for guests using x86 APICv. When guest OS/BIOS
switches from xAPIC to x2APIC mode of operation, ACRN also supports switching
froom LAPIC emulation to LAPIC passthrough to guest. User/developer needs to
configure GUEST_FLAG_LAPIC_PASSTHROUGH for guest_flags in the corresponding
VM's config for ACRN to enable LAPIC passthrough.

This patch does the following

1)Fixes a bug in the abovementioned feature. For a guest that is
configured with GUEST_FLAG_LAPIC_PASSTHROUGH, during the time period guest is
using xAPIC mode of LAPIC,  virtual interrupts are not delivered. This can be
manifested as guest hang when it does not receive virtual timer interrupts.

2)ACRN exposes physical topology via CPUID leaf 0xb to LAPIC PT VMs. This patch
removes that condition and exposes virtual topology via CPUID leaf 0xb.

Tracked-On: #3136
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-05-23 11:15:31 +08:00
yliu79
c5391d2592 HV: remove unused function vcpu_inject_ac
Change-Id: I4b139e78c372d0941923fc8260db7a3578a894f2
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
26de86d761 HV: remove unused function copy_to_gva
Change-Id: I18a6c860ba4bcec4e5915fa6a2a18ed1ecb20fff
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
163c63d21f HV: remove unused function resume_vm
Change-Id: Ia6b6617e55044b5555a2d80c26a4ef7d7e56b7fa
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
c68c6e4af2 HV: remove unused function shutdown_vcpu
Change-Id: Ia6f9aa4d2d603d23bc0cb9c3b12032d1a96504db
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
83012a5a0a HV: remove unused function disable_iommu
Change-Id: Ia2347008082991d56cdbfab9f9940cfccc473702
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
Minggui Cao
fc1cbebe31 HV: remove vcpu arch lock, not needed.
the pcpu just write its own vmcs, not need spinlock.
and the arch.lock not used other places, remove it too.

Tracked-On: #3130

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:35:26 +08:00
Minggui Cao
9876138b69 HV: add spinlock to dmar_enable/disable_qi
add spinlock to dmar_enable_qi & dmar_disable_qi to protect
struct dmar_unit variables; keep consistent with other same
level functions.

Tracked-On: #3130

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:35:26 +08:00
Victor Sun
90f3ce442d HV: remove unused UNDEFINED_VM
The enum of UNDEFINED_VM has never been used, remove it;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-05-22 10:01:20 +08:00
Andy
aba357dd36 1. fix cpu family calculation
2. Modifie the parameter 'fl' order

Tracked-On:#3142
Signed-off-by: Andy <andyx.liu@intel.com>
2019-05-21 10:37:17 +08:00
Jason Chen CJ
238d8bbaa2 reshuffle init_vm_boot_info
now only SOS need decide boot with de-privilege or direct boot mode, while
for other pre-launched VMs, they should use direct boot mode.

this patch merge boot/guest/direct_boot_info.c &
boot/guest/deprivilege_boot_info.c into boot/guest/vboot_info.c,
and change init_direct_vboot_info() function name to init_general_vm_boot_info().

in init_vm_boot_info(), depend on get_sos_boot_mode(), SOS may choose to init
vm boot info by setting the vm_sw_loader to deprivilege specific one; for SOS
using DIRECT_BOOT_MODE and all other VMS, they will use general_sw_loader as
vm_sw_loader and go through init_general_vm_boot_info() for virtual boot vm
info filling.

this patch also move spurious handler initilization for de-privilege mode from
boot/guest/deprivilege_boot.c to boot/guest/vboot_info.c, and just set it in
deprivilege sw_loader before irq enabling.

Changes to be committed:
	modified:   Makefile
	modified:   arch/x86/guest/vm.c
	modified:   boot/guest/deprivilege_boot.c
	deleted:    boot/guest/deprivilege_boot_info.c
	modified:   boot/guest/direct_boot.c
	renamed:    boot/guest/direct_boot_info.c -> boot/guest/vboot_info.c
	modified:   boot/guest/vboot_wrapper.c
	modified:   boot/include/guest/deprivilege_boot.h
	modified:   boot/include/guest/direct_boot.h
	modified:   boot/include/guest/vboot.h
	new file:   boot/include/guest/vboot_info.h
	modified:   common/vm_load.c
	modified:   include/arch/x86/guest/vm.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-05-20 18:49:59 +08:00
Zide Chen
865ee2956e hv: emulate ACPI reset register for Service OS guest
Handle the PIO reset register that is defined in host ACPI:

Parse host FADT table to get the host reset register info, and emulate
it for Service OS:

- return all '1' for guest reads because the read behavior is not defined
  in ACPI.
- ignore guest writes with the reset value to stop it from resetting host;
  if guest writes other values, passthru it to hardware in case the reset
  register supports other functionalities.

Tracked-On: #2700
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Zide Chen
26f08680eb hv: shutdown guest VM upon triple fault exceptions
This patch implements triple fault vmexit handler and base on VM types:

- post-launched VMs: shutdown_target_vm() injects S5 PIO write to request
  DM to shut down the target VM.
- pre-launched VMs: shut down the guest.
- SOS: similarly, but shut down all the non real-time post-launched VMs that
  depend to SOS before shutting down SOS.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Zide Chen
9aa3fe646b hv: emulate reset register 0xcf9 and 0x64
- post-launched RTVM: intercept both PIO ports so that hypervisor has a
  chance to set VM_POWERING_OFF flag.
- all other type of VMs: deny these 2 ports from guest access so that
  guests are not able to reset host.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Zide Chen
8ad0fd98a3 hv: implement NEED_SHUTDOWN_VM request to idle thread
For pre-launched VMs and SOS, VM shutdown should not be executed in the
current VM context.

- implement NEED_SHUTDOWN_VM request so that the BSP of the target VM can shut
  down the guest in idle thread.
- implement shutdown_vm_from_idle() to shut down target VM.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Li, Fei1
86f5993bc9 hv: vlapic: fix tpr virtualization when VID is not enabled.
1) According SDM Vol 3, Chap 29.1.2, Any VM exit caused by TPR virtualization
is trap-like: the instruction causing TPR virtualization completes before the VM
exit occurs (for example, the value of CS:RIP saved in the guest-state area of
the VMCS references the next instruction). So we need to retain the RIP.
2) The previous implement only consides the situation the guest will reduce the
TPR. However, the guest will increase it. So we need to update the PPR before we
find a deliverable interrupt. For examples: a) if the guest increase the TPR before
a irq windows vmexit, we need to update the PPR when check whether there has a pending
delivery interrupt or not; b) if the guest increase the TPR, then an external irq raised,
we need to update the PPR when check whether there has a deliverable interrupt to inject
to guest.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-15 08:59:39 +08:00
Li, Fei1
a68dadb74a hv: vm: minor fix about vRTC
For prelaunched VM, Service OS and postlaunched RT VM, we only need the vRTC
provides backed-up date, so we could use the simple vRTC which implemented
in hypervisor. For postlaunched VM (which is not a RT VM), we needs the device
module to emulate the vRTC for it.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
2019-05-15 08:59:39 +08:00
Victor Sun
8afbdb7505 HV: enable Kconfig of ACPI_PARSE_ENABLED
Previously we use Kconfig of DMAR_PARSE_ENABLED to choose pre-defined DMAR info
or parse it at runtime, at the same time we use MACRO of CONFIG_CONSTANT_ACPI
to decide whether parse PM related ACPI info at runtime. This looks redundant
so use a unified ACPI_PARSE_ENABLED Kconfig to replace them.

Tracked-On: #3107

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-14 11:53:02 +08:00
Mingqiang Chi
397986913e hv:merge static_checks.c
now there are 2 static_checks.c,
./arch/x86/static_checks.c
./common/static_checks.c
they are used for static checks when build time,
this check should not belong to any HV layer from
modularization view, then add and move it to pre_build folder.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
	modified:   Makefile
	deleted:    common/static_checks.c
	renamed:    arch/x86/static_checks.c -> pre_build/static_checks.c
2019-05-14 09:16:33 +08:00
Li, Fei1
bdae8efb7f hv: instr_emul: fix movzx return memory opsize wrong
There're some instructions which not support bit 0(w bit) flag but which
memory opcode size is fixed and the memory opcode size is not equal to the
register opcode size. In our code, there is movzx (which opcode is 0F B7)
which memory opcode size is fixed to 16 bits. So add a flag VIE_OP_F_WORD_OP
to indicate a instruction which memory opcode size is fixed to 16 bits.

Tracked-On: #1337
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-13 11:53:51 +08:00
Mingqiang Chi
795d6de0fb hv:move several files related X86 for lib
modified:   Makefile
renamed:    lib/memory.c -> arch/x86/lib/memory.c
renamed:    include/lib/atomic.h -> include/arch/x86/lib/atomic.h
renamed:    include/lib/bits.h -> include/arch/x86/lib/bits.h
renamed:    include/lib/spinlock.h -> include/arch/x86/lib/spinlock.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-05-13 10:12:20 +08:00
Shiqing Gao
7b8abe156c hv: refine 'init_percpu_lapic_id'
This patch refines 'init_percpu_lapic_id' to move the error
handling to 'init_pcpu_pre'.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2019-05-10 14:51:29 +08:00
Shiqing Gao
dbb41575e7 hv: remove dynamic memory allocation APIs
This patch removes dynamic memory allocation APIs, including:
- calloc
- malloc
- free

The corresponding data structures, MACROs, and Kconfig items
are also removed.

v1 -> v2: no change

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2019-05-10 11:33:37 +08:00
Shiqing Gao
5629ade9a0 hv: add default DRHD MACROs in template platform acpi info
This patch adds default DRHD MACROs in template platform acpi info.

It is the preparation patch to remove dynamic memory allocation
in dmar_parse.c. So that the dmar info can be initialized with
default size and values when CONFIG_DMAR_PARSE_ENABLED is set
to y.

v1 -> v2: no change

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2019-05-10 11:33:37 +08:00
Binbin Wu
a581f50600 hv: vmsr: enable msr ia32_misc_enable emulation
Add MSR_IA32_MISC_ENABLE to emulated_guest_msrs to enable the emulation.
Init MSR_IA32_MISC_ENABLE for guest.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
8e310e6ea1 hv: vcpuid: modify vcpuid according to msr ia32_misc_enable
According to SDM Vol4 2.1, modify vcpuid according to msr ia32_misc_enable:
- Clear CPUID.01H: ECX[3] if guest disabled monitor/mwait.
- Clear CPUID.80000001H: EDX[20] if guest set XD Bit Disable.
- Limit the CPUID leave maximum value to 2 if guest set Limit CPUID MAXVal.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
ef19ed8961 hv: vcpuid: reduce the cyclomatic complexity of function guest_cpuid
This patch reduces the cyclomatic complexity of the function guest_cpuid.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
f0d06165d3 hv: vmsr: handle guest msr ia32_misc_enable read/write
Guest MSR_IA32_MISC_ENABLE read simply returns the value set by guest.
Guest MSR_IA32_MISC_ENABLE write:
- Clear EFER.NXE if MSR_IA32_MISC_ENABLE_XD_DISABLE set.
- MSR_IA32_MISC_ENABLE_MONITOR_ENA:
  Allow guest to control this feature when HV doesn't use this feature and hw has no bug.

vcpuid update according to the change of the msr will be covered in following patch.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
a0a6eb43c4 hv: msr: use UL since ia32_misc_enable is 64bit
Merge two parts of different definitions for MSR_IA32_MISC_ENABLE fields.
- use the prefix "MSR_IA32_" to align with others
- Change MSR_IA32_MISC_ENABLE_XD to MSR_IA32_MISC_ENABLE_XD_DISABLE to
  align the meaning of the filed since it is "XD bit disable"
Use UL instead of U as the filed bit mask because MSR_IA32_MISC_ENABLE is 64-bit.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Jason Chen CJ
41ac9e5d10 rename function & definition from firmware to guest boot
The interface struct & API changes like below:
  struct uefi_context->struct depri_boot_context
  init_firmware_operations()->init_vboot_operations()
  init_firmware()->init_vboot()
  firmware_init_irq()->init_vboot_irq()
  firmware_get_rsdp()->get_rsdp_ptr()
  firmware_get_ap_trampoline()->get_ap_trampoline_buf()
  firmware_init_vm_boot_info()->init_vm_boot_info()

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:33:44 +08:00
Jason Chen CJ
20f97f7559 restruct boot and bsp dir for firmware stuff
currently, ACRN hypervisor can either boot from sbl/abl or uefi, that's
why we have different firmware method under bsp & boot dirs.
but the fact is that we actually have two different operations based on
different guest boot mode:
1. de-privilege-boot: ACRN hypervisor will boot VM0 in the same context as
native(before entering hypervisor) - it means hypervisor will co-work with
ACRN UEFI bootloader, restore the context env and de-privilege this env
to VM0 guest.
2. direct-boot: ACRN hypervisor will directly boot different pre-launched
VM(including SOS), it will setup guest env by pre-defined configuration,
and prepare guest kernel image, ramdisk which fetch from multiboot modules.

this patch is trying to:
- rename files related with firmware, change them to guest vboot related
- restruct all guest boot stuff in boot & bsp dirs into a new boot/guest dir
- use de-privilege & direct boot to distinguish two different boot operations

this patch is pure file movement, the rename of functions based on old assumption will
be in the following patch.

Changes to be committed:
	modified:   ../efi-stub/Makefile
	modified:   ../efi-stub/boot.c
	modified:   Makefile
	modified:   arch/x86/cpu.c
	modified:   arch/x86/guest/vm.c
	modified:   arch/x86/init.c
	modified:   arch/x86/irq.c
	modified:   arch/x86/trampoline.c
	modified:   boot/acpi.c
	renamed:    bsp/cmdline.c -> boot/cmdline.c
	renamed:    bsp/firmware_uefi.c -> boot/guest/deprivilege_boot.c
	renamed:    boot/uefi/uefi_boot.c -> boot/guest/deprivilege_boot_info.c
	renamed:    bsp/firmware_sbl.c -> boot/guest/direct_boot.c
	renamed:    boot/sbl/multiboot.c -> boot/guest/direct_boot_info.c
	renamed:    bsp/firmware_wrapper.c -> boot/guest/vboot_wrapper.c
	modified:   boot/include/acpi.h
	renamed:    bsp/include/firmware_uefi.h -> boot/include/guest/deprivilege_boot.h
	renamed:    bsp/include/firmware_sbl.h -> boot/include/guest/direct_boot.h
	renamed:    bsp/include/firmware.h -> boot/include/guest/vboot.h
	modified:   include/arch/x86/multiboot.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:33:44 +08:00
Yin Fengwei
8626e5aa3a vm_state: Update vm state VM_STATE_INVALID to VM_POWERED_OFF
Replace the vm state VM_STATE_INVALID to VM_POWERED_OFF.
Also replace is_valid_vm() with is_poweroff_vm().
Add API is_created_vm() to identify VM created state.

Tracked-On: #3082
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-08 16:58:41 +08:00
Victor Sun
1f93f7f46c HV: remove some redundant includes
vm_config.h has included types.h/acrn_common.h/vm_configurations.h,
acrn_common.h has included types.h, so remove the redundant includes;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-05-08 16:57:46 +08:00
Victor Sun
ad3658ee17 HV: remove CONFIG_CONSTANT_ACPI from Kconfig
The MACRO of CONFIG_CONSTANT_ACPI will be defined per scenario usage,
so move it from Kconfig to vm_configurations.h;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-07 11:39:51 +08:00
Victor Sun
e2d723d4fa HV: enable acpi pm1a register info fixup
Previously ACPI PM1A register info was hardcoded to 0 in HV for generic boards,
but SOS still can know the real PM1A info so the system would hang if user
trigger S3 in SOS. Enabling PM1A register info fixup will let HV be able to
intercept the operation on PM1A and then make basic function of S3 work for
all boards;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-07 11:39:51 +08:00
Mingqiang Chi
da9ed0eda9 hv:remove some unnecessary includes
remove some unnecessary includes

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-05-07 09:10:13 +08:00
Zide Chen
5f87e716b8 hv: release IOMMU irte when releasing ptirq remapping entries
IRTE is freed if ptirq entry is released from remove_msix_remapping() or
remove_intx_remapping(). But if it's called from ptdev_release_all_entries(),
e.g. SOS shutdown/reboot, IRTE is not freed.

This patch adds a release_cb() callback function to do any architectural
specific cleanup. In x86, it's used to release IRTE.

On VM shutdown, vpci_cleanup() needs to remove MSI/MSI-X remapping on
ptirq entries, thus it should be called before ptdev_release_all_entries().

Tracked-On: #2700
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-06 18:25:37 +08:00
Conghui Chen
dd86a78e75 HV: rename 'type' in struct io_request
Rename 'type' in struct io_request to 'io_type' to be more readable.

Tracked-On: #3061
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-06 18:25:20 +08:00
Shiqing Gao
94e1e362fb hv: rename 'interrupt_init' to 'init_interrupt'
This patch renames 'interrupt_init' to 'init_interrupt'.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-06 16:58:27 +08:00
Yan, Like
31efa2b522 hv: add one more guest VM to the industry scenario
This commmit added one more guest VM to the industry scenario, to
be aligned with the HLD for the industry usage.
With this commit, 4 VMs could be launched at maximum: 1 SOS VM and 3 post-launced VM.

Tracked-On: #3039
Signed-off-by: Yan, Like <like.yan@intel.com>
2019-05-05 16:38:57 +08:00
Conghui Chen
e6670b32f4 HV: rename structure acrn_vm_type
Rename structure acrn_vm_type to acrn_vm_load_order as it is used to
indicate the load order instead of the VM type.

Tracked-On: #2291
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-05 11:50:36 +08:00
Yonghua Huang
be2fe2a44d hv:remove accessing shared log buffer cases between stac/clac
Shared buffer is allocated by VM and is protected by SMAP.
Accessing to shared buffer between stac/clac pair will invalidate
SMAP protection.This patch is to remove these cases.
Fix minor stac/clac mis-usage,and add comments as stac/clac usage BKM

Tracked-On: #2526
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-05 10:00:32 +08:00
Yan, Like
624185c3ca hv: add scenario for the industry use case
This scenario is typical for industry usage with 3 VMs: 1 pre-launched SOS VM,
1 post-launched user VM for HMI and 1 post-launched  RT VM for real-time control.

Tracked-On: #3039
Signed-off-by: Yan, Like <like.yan@intel.com>
2019-04-29 17:03:19 +08:00
Victor Sun
00ebe8630f HV: remove dummy DRHD in template platform acpi info
The DRHD MACROs are needed only when CONFIG_DMAR_PARSE_ENABLED set to n,
whereas the template platform_acpi_info.h is prepared for generic boards
that usually CONFIG_DMAR_PARSE_ENABLED is set to y, so remove these dummy
DRHD info MACROs.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-29 15:25:25 +08:00
Victor Sun
6378b74db4 HV: add generic board config
hypervisor/arch/x86/configs/($CONFIG_BOARD) will store Board specific configs,
add a generic folder to store configs for generic boards that they can share
one build binary with minimal and common features in some scenarios like SDC.

Please be aware that BDF of pci devices are different on each board, so one
binary for LOGICAL_PARTITION scenario is not supported.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-29 15:25:25 +08:00
Sainath Grandhi
9214c84600 hv: Rename NORMAL_VM to POST_LAUNCHED_VM
The name NORMAL_VM does not clearly reflect the attribute that these VMs
are launched "later". POST_LAUNCHED_VM is closer to the fact
that these VMs are launched "later" by one of the VMs launched by ACRN.

Tracked-On: #3034
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-29 09:19:51 +08:00
Li, Fei1
536bc5bd12 hv: instr_emul: fix operand size decode
1) For some instructions (like movsx, movzx which we support), there're two operands
and the source operand size is not equal to the dest operand size. In this case,
if we update the memory operand size according to the bit 0(w bit) of opcode,
we will lost the register operand size. This patch tries to fix this by calculating
memory operand size when we want to use it.
2) Calculate memory operand size form operand size and the bit 0(w bit) of opcode
when we want to operate on memory operand.

Tracked-On: #1337
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-28 11:53:24 +08:00
Victor Sun
4bbf946fdd HV: minor changes on pci devices config
- The pci device config is related to VM configurations, so move the device
mapping MACROs from pci_devices.h to vm_configurations.h. Also considering
pci_devices.h should be generated by offline parse tool, this code change
would decouple the relationship between VM configuration tool and target
paser tool;

- Another minor change is add post-fix in number for each PCI device subclass
name to make target parse tool interface friendly;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-28 11:53:06 +08:00
Conghui Chen
a3922797af HV: cleanup SHARING_MODE and PARTITION_MODE
As SHARING_MODE and PARTITION_MODE are not used anymore, cleanup the
code.

Tracked-On: #2291
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-26 17:06:39 +08:00
Victor Sun
3bb4308361 HV: check vm id param when dispatching hypercall
If the vmcall param passed from guest is representing a vmid, we should
make sure it is a valid one because it is a pre-condition of following
get_vm_from_vmid(). And then we don't need to do NULL VM pointer check
in is_valid_vm() because get_vm_from_vmid() would never return NULL.

Tracked-On: #2978

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-26 16:21:14 +08:00
Zide Chen
1b7d33a426 hv: separate host e820 and SOS ve820
There are 2 reasons why SOS ve820 has to be separated from host e820:
- in hybrid mode, SOS may not own all the host memory.
- when SOS is being re-launched, it needs an untainted version of host
  e820 to create SOS ve820.

This patch creates sos_e820 table for SOS and keeps host e820 intact
during SOS creation.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-26 16:20:50 +08:00
Conghui Chen
235d886103 HV: vuart: enable vuart console for VM
In previous code, only for pre-launched VM, hypervisor would create
vuart console for each VM. But for post-launched VM, no vuart is
created.
In this patch, create vuart according to configuration in structure
acrn_vm_config. As the new configuration is set for pre-launched VM and
post-launched VM, and the vuart initialize process is common for each
VM, so, remove CONFIG_PARTITION_MODE from vuart related code.

Tracked-On: #2987
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 11:21:54 +08:00
Conghui Chen
3c92d7bbc7 HV: vuart: refine vuart config
Add vuart config in acrn_vm_config struct, support configuring 2 vuarts for
each VM. The first vuart is used to work as VM's console. The second vuart
is used to connect to other VM's vuart. When the port base for a vuart
is set to 0, hypervisor will not create this vuart.

Tracked-On: #2987
Signed-off-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 11:21:54 +08:00
Victor Sun
2362e58509 HV: correct usage of GUEST_FLAG_IO_COMPLETION_POLLING
The guest flags of GUEST_FLAG_IO_COMPLETION_POLLING work for NORMAL_VM only;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 11:07:21 +08:00
Yin Fengwei
578592b566 vlapic: refine IPI broadcast to support x2APIC mode
According to SDM 10.6.1, if dest fields is 0xffU for register
ICR operation, that means the IPI is for broadcast.

According to SDM 10.12.9, 0xffffffffU of dest fields for x2APIC
means IPI is for broadcast.

We add new parameter to vlapic_calc_dest() to show whether the
dest is for broadcast. For IPI, we will set it according to
dest fields. For ioapic and MSI, we hardcode it to false because
no broadcast for ioapic and MSI.

Tracked-On: #3003
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 09:12:16 +08:00
Kaige Fu
581c0a239a HV: move AP_MASK to cpu.h
It is better to use an unified MACRO. So, this patch moves AP_MASK to cpu.h
and removes the defination of the MACRO spanning different source files.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 11:55:23 +08:00
Kaige Fu
7b6fe14517 HV: Remove unnecssary indent in pm.c
This patch just removes unnecessary indent before #include in pm.c.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 10:50:38 +08:00
Kaige Fu
a85d11ca7a HV: Add prefix 'p' before 'cpu' to physical cpu related functions
This patch adds prefix 'p' before 'cpu' to physical cpu related functions.
And there is no code logic change.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 10:50:28 +08:00
li bing
25741b62db HV: fix the issue of ACRN_REQUEST_EXCP flag is not cleared.
the problem is : System will crash when run crashme.
The root cause of this problem is that when the ACRN_REQUEST_EXCP flag is set by calling
the vcpu_make_request function, the flag is not cleared.
Add the following statement to the vcpu_inject_exception function to fix the problem:
bitmap_test_and_clear_lock(ACRN_REQUEST_EXCP, &vcpu->arch.pending_req);
Tested that one night, there was no crash.

Tracked-On: #2527
Signed-off-by: bing.li<bingx.li@intel.com>
Acked-by:      Eddie Dong<eddie.dong@intel.com>
2019-04-23 15:17:13 +08:00
Li, Fei1
28d50f1b96 hv: vlapic: add apic register offset check API
Add apic rgister offset check before do vlapic read/write.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
70dd254456 hv: vmsr: refine x2apic MSR bitmap setting
In theory, we should trap out all the x2apic MSR access if APICv is not enabled.
When "Use TPR shadow" and "Virtualize x2APIC mode" are enabled, we could disable
TPR interception; when APICv is fully enabled, besides TPR, we could disable all
MSR read, EOI and self-IPI interception; when we pass through lapic to guest, we
could disable all the MSR access interception except XAPICID/LDR read and ICR write.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
0c347e607a hv: vlapic: wrap APICv check pending delivery interrupt
When in fully APICv mode, we enable VID. All pending delivery interrupts
will inject to VM before VM entry. So there is no pending delivery interrupt.
However, if VID is not enabled, we can only inject pending delivery interrupt
one by one. So we always need to do this check.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
037fffc203 hv: vlapic: wrap APICv inject interrupt API
apicv_advanced_inject_intr is used if APICv fully features are supported,
it uses PIR to inject interrupt. otherwise, apicv_basic_inject_intr is used.
it will use VMCS INTR INFO field to inject irq.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
1db8123c2d hv: virq: refine pending event inject coding style
In order to combine vlapic_apicv_inject_pir and vcpu_inject_vlapic_int.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
fde2c07c0a hv: vlapic: minor fix about APICv inject interrupt
When VID is enabeld, we should always inejct the pending interrupts when vm enter.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
846b5cf6b7 hv: vlapic: wrap APICv accept interrupt API
The APICv ops is decided once the APICv feature on the physical platform is detected.
We will use apicv_advanced_ops if the physical platform support fully APICv feature;
otherwise, we will use apicv_basic_ops.
This patch only wrap the accept interrupt API for them.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Yonghua Huang
f991d179b0 hv: fix possible buffer overflow in vlapic.c
Possible buffer overflow will happen in vlapic_set_tmr()
  and vlapic_update_ppr(),this path is to fix them.

Tracked-On: #1252
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-23 13:43:25 +08:00
Li, Fei1
2c13ac7400 hv: vmcs: minor fix about APICv feature setting
1) Shouldn't try to set APIC-register virtualization if the physical doesn't
support APICV advanced mode.
2) Remove all APICv features VMCS setting when LAPIC is passed through to guest.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 09:47:36 +08:00
Li, Fei1
4fc2009770 hv: instr_emul: check the bit 0(w bit) of opcode when necessary
Not every instruction supports the operand-size bit (w). This patch try to correct
what done in commit-id 9df8790 by setting a flag VIE_OP_F_BYTE_OP to indicate which
instruction supports the operand-size bit (w).

This bug is found by removing VMX_PROCBASED_CTLS2_VAPIC_REGS VMCS setting when the
physical doesn't support this APICv feature. However, if emulated this in MRB board,
the android can't boot because when switch to trusty world, it will check
"Delivery Status" in ICR first. It turns out that this Bit Test instruction is not
emulated correctly.

Tracked-On: #1337
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-04-23 09:47:36 +08:00
Kaige Fu
7ccb44afda HV: Remove dead loop in stop_cpus
This patch removes dead loop in stop_cpus because timeout never occurs.
If target cpu received a NMI and panic, it has called cpu_dead and stop_cpus success.
If target cpu is running, an IPI will be delivered to it and then call cpu_dead.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Kaige Fu
91c1408197 HV: Reset physical core of lapic_pt vm when shutdown
The physical core of lapic_pt vm should be reset for security and
correctness when shutdown the vm.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Kaige Fu
e52917f7d1 HV: Reshuffle start_cpus and start_cpu
This patch makes the following changes:
  - Add one parameter 'mask' to start_cpus for later use.
  - Set cpu state as DEAD instead of dead loop when fail to start cpu.
  - Panic when there are any failures when start cpus in init_cpu_post and host_enter_s3.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Kaige Fu
cfe8637cc1 HV: Kconfig: Remove CPU_UP_TIMEOUT
This patch remove the over design CPU_UP_TIMEOUT and
use CPU_UP_TIMEOUT and CPU_DOWN_TIMEOUT instead.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Kaige Fu
565f3c723a HV: Clear DM set guest_flags when shutdown vm
Currently, the previous configurations about guest_flags set by DM will
not be cleared when shutdown the vm. Then it might bring issue for the
next dm-launched vm.

For example, if we create one vm with LAPIC_PASSTHROUGH flag and shutdown it.
Then the next dm-launched vm will has the LAPIC_PASSTHROUGH flag set no matter
whether we set it in DM.

This patch clears all the DM set flags when shtudown vm.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Zide Chen
a3207b2bc2 hv: allocate vpid based on vm_id and vcpu_id mapping
Currently vpid is not released in reset_vcpu() hence the vpid resource
could be exhausted easily if guests are re-launched.

This patch assigns vpid according to the fixed mapping of runtime vm_id
and vcpu_id to guarantee the uniqueness of vpid.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-04-22 19:57:28 +08:00
Victor Sun
9673f3dad4 HV: validate target vm in hypercall
- The target vm in most of hypercalls should be a NORMAL_VM, in some
exceptions it might be a SOS_VM, we should validate them.

- Please be aware that some hypercall might have limitation on specific
target vm like RT or SAFETY VMs, this leaves "TODO" in future;

- Unify the coding style:

	int32_t hcall_foo(vm, target_vm_id, ...)
	{
		int32_t ret = -1;
		...

		if ((is_valid_vm(target_vm) && is_normal_vm(target_vm)) {
			ret = ....
		}

		return ret;
	}

Tracked-On: #2978

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:57:03 +08:00
Cai Yulong
887d41683b hv: check vm state before creating a VM
If launch two UOS with same UUID by acrn-dm, current code path will
return same VM instance to the acrn-dm, this will crash the two UOS.

Check VM state and make sure it's in VM_STATE_INVALID state before
creating a VM.

Tracked-On: #2984
Signed-off-by: Cai Yulong <yulongc@hwtc.com.cn>
2019-04-22 15:18:03 +08:00
Qi Yadong
fa47554054 hv: seed: fix potential NULL pointer dereferencing
The 'boot_params' and 'entry' might be dereferenced after they were
positively checked for NULL. Refine checking logic to fix the issue.

Tracked-On: #2979
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Zhu Bing <bing.zhu@intel.com>
2019-04-22 15:17:33 +08:00
Zide Chen
aee9f3c666 hv: reset per cpu sbuf pointers during vcpu reset
When shutting down SOS VM, the shared sbuf is released from guest OS, but
the per cpu sbuf pointers in hypervisor keep inact. This creates a problem
that after SOS is re-launched, hypervisor could write to the shared
buffer that no longer exists.

This patch implements sbuf_reset() and call it from reset_vcpu() to
reset sbuf pointers.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-04-19 16:20:34 +08:00
Li, Fei1
56acaacc29 hv: vlapic: add TPR below threshold implement
Add TPR below threshold implement for "Virtual-interrupt delivery" not support.
Windows will use it to delay interrupt handle.

Complete all the interrupts in IRR as long as they are higher priority than
current TPR. Once current IRR priority is less than current TPR enable TPR
threshold to IRR, so that if guest reduces the TPR threshold, it would be good
to take below TPR threshold exit and let interrupts to go thru.

Tracked-On: #1842
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-19 11:11:54 +08:00
Yuan Liu
b1e68453bd hv: enable vMCE from guest CPUID
Enable vMCE feature to boot windows guest.

vMCE is set in EDX from Microsoft TLFS spec, to support windows guest
vMCA and vMCE should be supported by guest CPUID.

Support MSR_IA32_MCG_CAP and MSR_IA32_MCG_STATUS reading when vMCE is enabled,
but they are not emulated yet, so return 0 directly.

Tracked-On: #1867
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-18 09:00:42 +08:00
Sainath Grandhi
824caf8ce0 hv: Remove need for init_fallback_iommu_domain and fallback_iommu_domain
In the presence of SOS, ACRN uses fallback_iommu_domain which is the same
used by SOS, to assign domain to devices during ACRN init. Also it uses
fallback_iommu_domain when DM requests ACRN to remove device from UOS domain.
This patch changes the design of assign/remove_iommu_device to avoid the
concept of fallback_iommu_domain and its setup. This way ACRN can commonly
treat pre-launched VMs bringup w.r.t. IOMMU domain creation.

Tracked-On: #2965
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-04-17 11:42:36 +08:00
Xiangyang Wu
48be6f1fd7 HV:config:Add config to enable logic partition on KBL NUC i7
In the current design, logic partition scenario is supported
on KBL NUC i7 since there is no related configuration and
no the cooresponding boot loader supporting.
The boot loader supporting is done in the previous patch.

Add some configurations such physical PCI devices information,
virtual e820 table etc for KBL NUC i7 to enable logical
partition scenario.
In the logical partition of KBL NUC i7, there are two
pre-launched VM, this pre-launched VM doesn't support
local APIC passthrough now. The hypervisor is booted through
GRUB.

TODO: In future, Local APIC passthrough and some real time
fetures are needed for the logic partition scenario of KBL
NUC i7.

V5-->V6:
	Update "Tracked-On"

Tracked-On: #2944

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-04-16 12:07:58 +08:00
Yonghua Huang
46480f6e23 hv: add new hypercall to fetch platform configurations
add new hypercall get platform information,
 such as physical CPU number.

Tracked-On: #2538
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-15 22:14:13 +08:00
Sainath Grandhi
16a2af5715 hv: Build mptable for guest if VM type is Pre-Launched
ACRN builds mptable for pre-launched VMs. It uses CONFIG_PARTITION_MODE
to compile mptable source code and related support. This patch removes
the macro and checks if the type of VM is pre-launched to build mptable.

Tracked-On: #2941
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-15 15:51:02 +08:00
Shiqing Gao
869de39757 hv: rename 'assign_iommu_device' and 'unassign_iommu_device'
- rename 'assign_iommu_device' to 'assign_pt_device'
- rename 'unassign_iommu_device' to 'unassign_pt_device'

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@inte.com>
2019-04-15 15:38:01 +08:00
Victor Sun
445999af5d HV: make vm id statically by uuid
Currently VM id of NORMAL_VM is allocated dymatically, we need to make
VM id statically for FuSa compliance.

This patch will pre-configure UUID for all VMs, then NORMAL_VM could
get its VM id/configuration from vm_configs array by indexing the UUID.

If UUID collisions is found in vm configs array, HV will refuse to
load the VM;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 13:45:32 +08:00
Victor Sun
cb10dc7e73 HV: return bool in sanitize_vm_config
Return true if vm configs is sanitized successfully, otherwise return false;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 13:45:32 +08:00