Commit Graph

624 Commits

Author SHA1 Message Date
Zide Chen
83dbfe4fd3 hv: implement sharing_mode.c for PCI emulation in sharing mode
Compared with partition_mode.c, the major difference between them is
the list of PCI devices is statically defined or dynamically
enumerated and allocated.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
7c506ebc69 hv: implement msix.c for MSI-X remapping
Similar to MSI emulation, this patch emulates the Message Control word
within MSI-X Capability Structure.

Also it emulates MSI-X table. MSI-X remapping is triggered when the guest
is changing the Mask bit in Vector Control, or the Message Data/Addr when
MSI-X Enable bit is set.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
dcebdb8e98 hv: implement msi.c to handle MSI remapping for vm0
Emulate MSI Capability structure for vm0 in sharing mode:

- it intercepts the IO requests for MSI Capability structure, emulates
  the Message Control word, and bypasses all other I/O requests to the
  physical device.

- criteria to trigger MSI remapping: MSI Enable bit is being changed,
  Message Data/Addr is being changed when MSI Enable is set.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
6af47f249c hv: vpci: add callback functions to struct vpci
Add 'struct vpci_ops *ops' to 'struct vpci' so we have clearer structure:

- struct vpci: include struct vpci_ops pointing to different callback
  functions for partition or sharing mode repsectively.
- struct pci_vdev: includes struct pci_vdev_ops to handle different vpci
  functionalities:
      hostbridge emulation
      passthrough device BAR emulation
      msi/msi-x remapping

This patch moves the code around but doesn't change the underlying logic
in terms of PCI spec handling. More detailed implementation:

- create new file partition_mode.c to house the implementation of partition mode
  regarding the vpci layer.
- vpci.c: only keeps the abstract code which calls vpci->ops to functions
  in partition_mode.c, and potentially to sharing_mode.c.
- the following functions are moved to partition_mode.c and renamed with
  partition_mode prefix.
    - vpci_init() -> partition_mode_vpci_init()
    - vpci_cleanup() -> partition_mode_vpci_deinit()
    - pci_cfg_io_write() -> partition_mode_cfgread()
    - pci_cfg_io_read() -> partition_mode_cfgwrite()

Track-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
3e54c70d0f hv: rework the MMIO handler callback hv_mem_io_handler_t arguments
commit 026ae83bd5 ("hv: include: fix 'Unused procedure parameter'")
removed the then unused parameter handler_private_data from
hv_mem_io_handler_t because MISRA-C requires that there should be no
unused parameters in functions.

This patch removes vcpu from the parameter list as well since this may
not be used by all users. Also it brings back handler_private_data which
is more flexible. For example, vioapic_mmio_access_handler() can use it
to pass vcpu pointer.

Tracked-On: #861
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
ec5b90f11e hv: implement PCI bus scan function
- It starts from scaning bus 0 and scan other buses only if it is referred
  as a Secondary Bus by a PCI-to-PCI bridge.
- Skip to next device if function 0 is not implemented.
- Don't enumerate function 1-7 if a device is not a multi-function device.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
9cc1f57f63 hv: change function parameters: pci_pdev_read_cfg and pci_pdev_write_cfg
In order to allow these functions to be called without an associated
struct pci_pdev (for example, at the time of PCI bus enumeration), these
two functions can not take the struct vdev as input parameter.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
19e1b9675f hv: MSI Message Address should be 64 bits
Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
7b4b78c323 hv: minor cleanup for dm/vpci code
- It makes more sense to return bool from pci_bar_access()
- other minor changes for cleanup

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
bc4f82d1d1 hv: more cleanup for pci.h
Don't have any logical changes.
- add more common PCI macros
- remove redundant definitions in dmar_parse.c
- move all the common mascos from vpci.h to pci.h

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Mingqiang Chi
dff441a0d5 hv:Replace dynamic memory with static for pcpu
--remove 'calloc' for pcpu, change it to static array
--rename 'init_percpu_data_area' to 'init_percpu_lapic_id'
Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-29 10:14:25 +08:00
Mingqiang Chi
298044d95b hv: Add MAX_PCPU_NUM in Kconfig
--Removed MAX_PCPU_NUM in cpu.h
--Changed the default value from 128 to 8 for
  MAX_PCPU_NUM

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-29 10:14:25 +08:00
Chinthapally, Manisha
cab93c053a HV:Added SBuf support to copy samples generated to guest.
sbuf.h:
    Added new shared buffer types for SEP and SOCWATCH

profiling.c
   sbuf_next_ptr - returns  address of next available buffer

profiling_sbuf_put_variable:
   This function allows to write data of variable size into shared buffer.

profiling_generate_data:
     Read profiling data and transfer to SOS
     Drops transfer of profiling data if sbuf is full/insufficient and log it

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Chinthapally, Manisha
5985c1216e HV:Added implementation for PMI handler function
irq.c/.h:
	Added new variables(ctx_rflags, ctx_rip, ctx_cs) in irq_desc
	On each interrupt this information is populated
	Added api's to access the irq_desc members

profiling.c:
	profiling_pmi_handler:On each PMI generates gets the context and other information that	caused it

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Chinthapally, Manisha
a7cbee1802 HV:Added support to get VM enter and exit information
profiling_vmenter_handler:Saves vm information

profiling_vmexit_handler: Saves vm information and vm exit reason

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Chinthapally, Manisha
fc8f9d792c HV:Added support to perform MSR operation on all cpus
MSR operations are directly done based on physical cpu's

profiling_handle_msrops:
	Per cpu function, performs the MSR operations (Read, Read clear,Write)
	For SOCWATCH/ power tool, generates MSR samples.

profiling_msr_ops_all_cpus :
	Receives required information for MSR operations from guest,
	SMP calls profiling_handle_msrops,
	Copies the information collected to guest

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Manisha Chinthapally
1786f6222a HV:Added support to setup tool & start/stop profing
profiling_set_control:
    Receives tool control information from guest and sets control switches accordingly,
    tool control information includes:
         type - sep/socwatch
         action - Start/stop
         feature - What to collect(core/lbr/vm switch)
    This function provides interface to start and stop profiling data collection

profiling_start_pmu:
    Initialize sep state and enable PMU counters
    SMP calls profiling_enable_pmu

profiling_stop_pmu:
    Reset sep state and Disable all the PMU counters
    SMP calls profiling_disable_pmu

profiling_enable_pmu:
    Enable all the Performance Monitoring Control registers.
    Unmask LAPIC entry for PMC register to enable performance monitoring
    Walk through the entries and write to PMU control regiesters

profiling_disable_pmu:
    Disable all Performance Monitoring Control registers

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Chinthapally, Manisha
898b9c8d4a HV:Added support to configure PMI and VM switch info
This patch provides interface to configure(setup before actual
collection) PMI and VM switch tracing information.

profiling_config_pmi:
    Receives required information for configuring PMI from guest,
    populates the information info per_cpu region and SMP calls profiling_initilaize_pmi

profiling_initialize_pmi:
    Configure the PMU's for sep/socwatch profiling.
    Initial write of PMU registers.
    Walk through the entries and write the value of the register accordingly.

profiling_config_vmsw:
    Receives required information for configuring
    VMswitch from guest, Configure for VM-switch data on all cpus

profiling_initialize_vmsw: initializes VMSwitch	tracing

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Chinthapally, Manisha
df549096f2 HV:Added support to get phy CPU, VM, tool information
This patch includes support to following
1. Collection of physical cpuid information
2. Collection of List of VM's available and information
3. Tool version information
4. Sending tool control information to guest

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Chinthapally, Manisha
8ba333d275 HV: Added Initial support for SEP/SOCWATCH profiling
This patch adds support to sep/socwatch profiling
     Adds 2 new files include/arch/x86/profiling.h and arch/x86/profiling.c
     which contains most of the implementation for profiling,most of the functions
     in profiling.c have dummy implementation and will be implemented in next patches

     a. cpu.c, Initial profiling setup is done as part of bsp_boot_post
  and cpu_secondary_post flow
     b. vmcall.c, New ioctl is added for performing profiling related
  operations in vmcall_vmexit_handler
	ioctl - HC_PROFILING_OPS
        function - hcall_profiling_ops()
     c. common/hypercall.c, hcall_profiling_ops() implementation.
     d. hv_main.c, In vcpu_thread calling profiling related functions
  to save vm context
     e. acrn_hv_defs.h, list all the profiling command types

Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
2018-10-26 13:39:07 +08:00
Mingqiang Chi
1568a4c095 hv:Remove deadcode 'vm_lapic_from_pcpuid'
This api is not used, remove it.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-10-25 13:45:40 +08:00
Huihuang Shi
46d198244f HV:vcpu fix "Pointer param should be declared pointer to const"
Fix violations whose parameter can be read-only.
This patch only fix the parameter whose name is vcpu.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:45:14 +08:00
Huihuang Shi
ea32c34ae1 HV:fix "Pointer param should be declared pointer to const"
Fix violations for function whose parameter can be read-only.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:45:14 +08:00
Huihuang Shi
d79007ae70 HV:add const to bitmap_test parameter addr
bitmap_test parameter addr should be read-only,
the addr is in the asm code "output" region,
change it to the "input" region.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:45:14 +08:00
Sainath Grandhi
09193c3913 hv: x2apic support for acrn
All the platforms supported by ACRN supports x2APIC. So enabled
x2APIC for ACRN hv. Removed any code that is needed for xAPIC mode
of operation.

Tracked-On: #1455
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed by:  Yonghua Huang <yonghua.huang@intel.com>
2018-10-25 13:41:29 +08:00
Huihuang Shi
107eaa3ab0 HV:fix MACRO value mismatch
The commit id "c5f4c5" translats from enum to macro, the content
is not correct,fixed now.

Tracked-On: #1553
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Zhi Jin <zhi.jin@intel.com>
2018-10-24 18:13:57 +08:00
Zide Chen
a6677e6e69 hv: create new file core.c and pci.c
- move the functions to access physical PCI configuration space from
  pci_pt.c to the new file dm/hw/pci.c, so they can be accessed in
  sharing mode as well. The new folder dm/hw is created in order to
  move APIs talking to physical PCI devices out of dm/vpci.
- move the common vpci code from header file pci_priv.h to core.c.
- move file include/dm/vpci/vpci.h one level up. It seems the folder
  include/dm/vpci is not necessary.
- This patch only moves code around, and doesn't make any logical
  changes. Besides removes the static keyword from pci_pdev_read_cfg()
  and pci_pdev_write_cfg()

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-24 18:11:02 +08:00
Zide Chen
4741fcfff2 hv: pci_priv.h code cleanup
- move most of the content of pci_priv.h to include/dm/pci.h.
  This allows other code outside dm/vpci to be able to share these macros.
- code cleanup: fix alignments etc.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-24 18:11:02 +08:00
Li, Fei1
39fde060c3 hv: ept: remove EPT paging table for HPA to GPA
There's no need to walk these paging tables to transfer HPA to GPA
for a VM, so remove it.

Tracked-On: #1124
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-23 09:12:51 +08:00
Li, Fei1
70ddca3a87 hv: mmu: add pre-assumption for hpa2gpa
They're: (a) only SOS would use hpa2gpa and (b) the GPA and HPA
in SOS is identical mapping.
Rename hpa2gpa to vm0_hpa2gpa then.

Tracked-On: #1124
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-10-23 09:12:51 +08:00
Huihuang Shi
60b216a460 HV:fixed "Pointer param should be declared pointer to const"
Pointer param should be declared pointer to const if
the parameter is keeped read-only.
This patch changes pointer param whose name is vm.

Tracked-On:#861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-19 22:49:38 +08:00
Jason Chen CJ
1c7d2f653a vuart: change irq from 4 to 6
irq 4 is sharing with idma, after change vuart to level trigger, the idma
driver could handle this irq 4 and send out EOI, which cause the irq storm.

move vuart irq to a not used 6.

Tracked-On: https://github.com/projectacrn/acrn-hypervisor/issues/1476
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-10-19 18:06:31 +08:00
Jason Chen CJ
6485666a93 Revert "hv: x2apic support for acrn"
This reverts commit 348e2ba168.
2018-10-19 17:24:56 +08:00
Mingqiang Chi
85ececd2d7 hv:Simplify for-loop when walk through the vcpu
-- Not return NULL for vcpu_from_vid
  We have replaced dynamic memory with static memory for vcpu,
  then if vcpu_id is valid, this API should not return NULL.
-- Simplify the for-loop when walk through the vcpu

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-19 14:23:08 +08:00
Victor Sun
ca65e8c727 HV: refine APIC base address to platform acpi info
The base address of LAPIC and IOAPIC should be parsed from MADT table,
so move the definition to platform_acpi_info.h.

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Victor Sun
8f701b0ff7 HV: move NR_IOAPICS to platform acpi info
The I/O APIC number should be parsed from host ACPI table, so move the
definition from Kconfig to platform_acpi_info.h.

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Victor Sun
bf834072d4 HV: platform acpi info refactor
Replace platform_acpi_info.c with platform_acpi_info.h and define needed
host ACPI info in MACROs. Then the struct host_acpi_info is not needed
any more.

This header file should be generated by offline tool automatically;

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Huihuang Shi
4620b935de fix "use of single line comments(s) //"
Replace "//" with '/*','*/' couples.

V1->V2:
    Correct comment "Tracked-On" format

V2->V3:
    Remove "/* ==...===*/" comment

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-17 16:16:31 +08:00
Qi Yadong
d9df6e93f3 HV: parse seed from ABL
ABL pass seed_lists to HV through different interface/structures.
So, in this patch, add interface to retrieve seed from ABL and refactor
the seed parsing logic.

Tracked-On: #1488
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Zhu Bing <bing.zhu@intel.com>
2018-10-17 14:30:52 +08:00
Sainath Grandhi
348e2ba168 hv: x2apic support for acrn
All the platforms supported by ACRN supports x2APIC. So enabled
x2APIC for ACRN hv. Removed any code that is needed for xAPIC mode
of operation.

Tracked-On: #1455
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed by:  Yonghua Huang <yonghua.huang@intel.com>
2018-10-17 08:46:42 +08:00
Wei Liu
96412ac147 hv: add suffix(U/UL) to come up MISRA-C into include
MISRA-C required the suffix(U/UL), such as:
(1) ---> (1U)
(1) ---> (1UL)
(1U << 0) ---> (1U << 0U)
This patch will add the suffix(U/UL) to come up MISRA-C into
hypervisor/include directory.

Tracked-On: #1468
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 22:33:30 +08:00
Yonghua Huang
38d5df723d hv:enable APICv-Posted Interrupt
to enable APICv Posted interrupt supported, following the
 specifications defined in Intel SDM Section #29.6, Volume3.

 Posted-interrupt processing is a feature by which a processor
 processes the virtual interrupts by recording them as pending
 on the virtual-APIC page.

 Injecting interrupts to VCPU from remote CPU without causing
 VM exit on the destination, following steps in SDM Section 29.6,volume3:

Tracked-On: #1447
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 22:18:24 +08:00
Jason Chen CJ
a028567b9c vpic: change assert/deassert method
use pin_state[pin] to record vpic pin signal, and change the interface name
accordingly.

Tracked-On: #1269
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-10-15 15:50:55 +08:00
Mingqiang Chi
1d725c89c0 hv:Replace dynamic memory with static for vcpu
-- Replace dynamic memory allocation with static memory
-- Remove parameter check if vcpu is NULL

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 13:44:25 +08:00
junjunshan1
7dd35cb72e hv: Fix identifier reuse
Now we have name reuse definitions in hypervisor as following:
"enum cpu_state cpu_state" in per_cpu.h,
"struct shell_cmd *shell_cmd" in shell_priv.h.
MISRAC requires that tag names shall not be reused anywhere
with in a program.So these definitions violate MISRAC rules
"identifier resue".This patch is used to fix it.

1. modify the definitions to "enum pcpu_boot_state boot_state"
and "struct shell_cmd *cmds".
2. modifty the relevant usage.

v1->v2
    update commit message to be more explicit.

v2->v3
    update the enum definition.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:34 +08:00
Yin Fengwei
dbd9ab07e1 hv: Cleanup: Remove dead code.
Now, UOS will use hypercall to init BSP state, we could remove
set_bsp_real_mode_entry() and set_bsp_protect_mode_regs().

For SOS, GDT will inherit from SBL or UEFI. For UOS, DM will
prepare GDT. We don't need hypervisor to prepare GDT for guest.

The entry_addr of vcpu struct could be removed. The guest entry
is set through BSP rip register.

GUEST_CFG_OFFSET is not needed any more after this patchset.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
b454a067be hv: remove the vm loader for UOS in hv.
Now, we make UOS to set BSP init state by using hypercall. We
could drop the old UOS loader in HV and make vm loader in HV
only for SOS.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
3cfbc004f5 hv: add hypercall to set vcpu init state
DM will use this hypercall to initialize the UOS BSP state.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
90eca21d16 hv: simplify the function init_guest_state
The vcpu state is initialized outside of init_guest_state:
 - SOS BSP state is initialized in SOS loader
 - UOS BSP state is initialized in UOS loader
 - AP state is initialized during SIPI signal emulation

We could make init_guest_state only update the vcpu state
to VMCS structure.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 16:27:45 +08:00
Yin Fengwei
a5fc3e5eac hv: Add function to set UOS BSP init state
NOTE: this patch is only workaround patch for UOS BSP state init.
Eventually, the DM will call hypercall to init UOS BSP state.

We use this workaround patch here to simplify the init_guest_state.
Will make the caller of init_guest_state calls init_guest_vmx
directly.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 16:27:45 +08:00