Commit Graph

59 Commits

Author SHA1 Message Date
Jiaqing Zhao
eae668268e hv: handle reboot from Service VM properly
Service VM may write 0x6 to port 0xcf9 to trigger a warm reset, but
current hypervisor always performs a cold reset by writing 0xE to CF9.
Hypervisor should reboot the system in the same mode as Service VM
specified. Specific OS features (like linux pstore) requires warm
reset to keep data across reboot.

The behavior of hv console's reboot command (cold reset) remains
unchanged.

Tracked-On: #8539
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2024-09-09 14:37:16 +08:00
Haiwei Li
3d6ca845e2 hv: s3: add timer support
When resume from s3, Service VM OS will hang because timer interrupt on
BSP is not triggered. Hypervisor won't update physical timer because
there are expired timers on pcpu timer list.

Add suspend and resume ops for modules that use timers.

This patch is just for Service VM OS. Support for User VM will be added
in the future.

Tracked-On: #8623
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
2024-06-27 11:26:09 +08:00
Haiwei Li
9c139681f2 hv: s3: hwp: enable hwp after resume from s3
After Service OS resume from s3, an error occurs:

[3649827us][cpu=1][idle1][sev=2][seq=1749]:= Unhandled exception: 13 (General Protection)

[3658622us][cpu=1][idle1][sev=2][seq=1750]:
Host Registers:

[3664881us][cpu=1][idle1][sev=2][seq=1751]:=  Vector=0x000000000000000D  RIP=0x000000000040F9F0

[3674213us][cpu=1][idle1][sev=2][seq=1752]:=     RAX=0x0000000080003801  RBX=0x0000000001800800  RCX=0x0000000000000774

[3685787us][cpu=1][idle1][sev=2][seq=1753]:=     RDX=0x0000000000000000  RDI=0x0000000000000080  RSI=0x0000000000000000

[3697371us][cpu=1][idle1][sev=2][seq=1754]:=     RSP=0x0000000000616C18  RBP=0x0000000000616C38  RBX=0x0000000001800800

[3708947us][cpu=1][idle1][sev=2][seq=1755]:=      R8=0x0000000000000038   R9=0x0000000000000001  R10=0x00000000000003F8

[3720539us][cpu=1][idle1][sev=2][seq=1756]:=     R11=0x000000000000000D  R12=0x0000000000458245  R13=0x0000000000000000

[3732114us][cpu=1][idle1][sev=2][seq=1757]:=  RFLAGS=0x0000000000010202  R14=0x0000000000000000  R15=0x0000000000000000

[3743699us][cpu=1][idle1][sev=2][seq=1758]:= ERRCODE=0x0000000000000000   CS=0x0000000000000008   SS=0x0000000000000010

[3755305us][cpu=1][idle1][sev=2][seq=1759]:= CR2=0x0000000000000000

The error occurs in `msr_write(MSR_IA32_HWP_REQUEST, reg)`, when HWP is
not available.

This patch is to initialize HWP after resume.

Tracked-On: #8623
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
2024-06-27 11:26:09 +08:00
Muhammad Qasim Abdul Majeed
3be3b394ad hypervisor: Fix spelling and grammar mistakes.
Tracked-On: #8533
Signed-off-by: Muhammad Qasim Abdul Majeed <qasim.majeed20@gmail.com>
2023-10-24 11:10:47 +08:00
Wu Zhou
fbdc2774af hv: add ACRN CPU frequency initializer
The design of ACRN CPU performance management is to let hardware
do the autonomous frequency selection(or set to a fixed value),
and remove guest's ability to control CPU frequency.

This patch is to implement the CPU frequency initializer, which will
setup CPU frequency base on the performance policy type.

Two performance policy types are provided for user to choose from:
  - 'Performance': CPU runs at its CPU runs at its maximum frequency.
    Enable hardware autonomous frequency selection if HWP is presented.
  - 'Nominal': CPU runs at its guaranteed frequency.

The policy type is passed to hypervisor through boot parameter, as
either 'cpu_perf_policy=Nominal' or 'cpu_perf_policy=Performance'.
The default type is 'Performance'.

Both HWP and ACPI p-state are supported. HWP is the first choice, for
it provides hardware autonomous frequency selection, while keeps
frequency transaction time low.

Two functions are added to the hypervisor to call:
  - init_frequency_policy(): called by BSP at start up time. It processes
    the boot parameters, and enables HWP if it is presented.
  - apply_frequency_policy(): called after init_frequency_policy().
    It applies initial CPU frequency policy setting for each core. It
    uses a set of frequency limits data struct to quickly decide what the
    highest/nominal frequency is. The frequency limits are generated by
    config-tools.

The hypervisor will not be governing CPU frequency after initial policy
is applied.

Cores running RTVMs are fixed to nominal/guaranteed frequency, to get
more certainty in latency. This is done by setting the core's frequency
limits to highest=lowest=nominal in config-tools.

Tracked-On: #8168
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2022-10-08 11:13:21 +08:00
Ziheng Li
eb8bcb06b3 Update copyright year range in code headers
Modified the copyright year range in code, and corrected "int32_tel"
into "Intel" in two "hypervisor/include/debug/profiling.h" and
"hypervisor/include/debug/profiling_internal.h".

Tracked-On: #7559
Signed-off-by: Ziheng Li <ziheng.li@intel.com>
2022-07-15 11:48:35 +08:00
Yifan Liu
5c9456462b hv && config-tool: Add compilation option to disable all interrupts in HV
This patch adds an option CONFIG_KEEP_IRQ_DISABLED to hv (default n) and
config-tool so that when this option is 'y', all interrupts in hv root
mode will be permanently disabled.

With this option to be 'y', all interrupts received in root mode will be
handled in external interrupt vmexit after next VM entry. The postpone
latency is negligible. This new configuration is a requirement from x86
TEE's secure/non-secure interrupt flow support. Many race conditions can be
avoided when keeping IRQ off.

v5:
Rename CONFIG_ACRN_KEEP_IRQ_DISABLED to CONFIG_KEEP_IRQ_DISABLED

v4:
Change CPU_IRQ_ENABLE/DISABLE to
CPU_IRQ_ENABLE_ON_CONFIG/DISABLE_ON_CONFIG and guard them using
CONFIG_ACRN_KEEP_IRQ_DISABLED

v3:
CONFIG_ACRN_DISABLE_INTERRUPT -> CONFIG_ACRN_KEEP_IRQ_DISABLED
Add more comment in commit message

Tracked-On: #6571
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2021-12-10 09:50:17 +08:00
Shuo A Liu
6e0b12180c hv: dm: Use new power management data structures
struct cpu_px_data		->	struct acrn_pstate_data
struct cpu_cx_data		->	struct acrn_cstate_data
enum pm_cmd_type		->	enum acrn_pm_cmd_type
struct acpi_generic_address	->	struct acrn_acpi_generic_address
cpu_cx_data			->	acrn_cstate_data
cpu_px_data			->	acrn_pstate_data

IC_PM_GET_CPU_STATE		->	ACRN_IOCTL_PM_GET_CPU_STATE

PMCMD_GET_PX_CNT		->	ACRN_PMCMD_GET_PX_CNT
PMCMD_GET_CX_CNT		->	ACRN_PMCMD_GET_CX_CNT
PMCMD_GET_PX_DATA		->	ACRN_PMCMD_GET_PX_DATA
PMCMD_GET_CX_DATA		->	ACRN_PMCMD_GET_CX_DATA

Tracked-On: #6282
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
2021-07-15 11:53:54 +08:00
Liang Yi
3547c9cd23 hv/mod_timer: make timer into an arch-independent module
x86/timer.[ch] was moved to the common directory largely unchanged.

x86 specific code now resides in x86/tsc_deadline_timer.c and its
interface was defined in hw/hw_timer.h. The interface defines two
functions: init_hw_timer() and set_hw_timeout() that provides HW
specific initialization and timer interrupt source.

Other than these two functions, the timer module is largely arch
agnostic.

Tracked-On: #5920
Signed-off-by: Rong Liu <rong2.liu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2021-05-18 16:43:28 +08:00
Liang Yi
51204a8d11 hv/mod_timer: separate delay functions from the timer module
Modules that use udelay() should include "delay.h" explicitly.

Tracked-On: #5920
Signed-off-by: Rong Liu <rong2.liu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2021-05-18 16:43:28 +08:00
Liang Yi
688a41c290 hv: mod: do not use explicit arch name when including headers
Instead of "#include <x86/foo.h>", use "#include <asm/foo.h>".

In other words, we are adopting the same practice in Linux kernel.

Tracked-On: #5920
Signed-off-by: Liang Yi <yi.liang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2021-05-08 11:15:46 +08:00
Liang Yi
33ef656462 hv/mod-irq: use arch specific header files
Requires explicit arch path name in the include directive.

The config scripts was also updated to reflect this change.

Tracked-On: #5825
Signed-off-by: Peter Fang <peter.fang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2021-03-24 11:38:14 +08:00
Yin Fengwei
bfa19e9104 pm: S5: update the system shutdown logical in ACRN
For system S5, ACRN had assumption that SOS shutdown will trigger
system shutdown. So the system shutdown logical is:
   1. Trap SOS shutdown
   2. Wait for all other guest shutdown
   3. Shutdown system

The new logical is refined as:
   If all guest is shutdown, shutdown whole system

Tracked-On: #4270
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2019-12-23 15:15:09 +08:00
Qi Yadong
3ebeecf060 hv: save/restore TSC in host's suspend/resume path
TSC would be reset to 0 when enter suspend state on some platform.
This will fail the secure timer checking in secure world because
secure world leverage the TSC as source of secure timer which should
be increased monotonously.

This patch save/restore TSC in host suspend/resume path to guarantee
the mono increasing TSC.

Note: There should no timer setup before TSC resumed.

Tracked-On: #3697
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-09-19 13:50:50 +08:00
Mingqiang Chi
60adef33d3 hv:move down structures run_context and ext_context
Now the structures(run_context & ext_context) are defined
in vcpu.h,and they are used in the lower-layer modules(wakeup.S),
this patch move down the structures from vcpu.h to cpu.h
to avoid reversed dependency.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-09-16 14:51:36 +08:00
Yin Fengwei
6b6aa80600 hv: pm: fix coding style issue
This patch fix the coding style issue introduced by previous two
patches.

Tracked-On: #3564
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2019-09-11 17:30:24 +08:00
Yin Fengwei
f039d75998 hv: pm: enhencement platform S5 entering operation
Now, we have assumption that SOS control whether the platform
should enter S5 or not. So when SOS tries enter S5, we just
forward the S5 request to native port which make sure platform
S5 is totally aligned with SOS S5.

With higher serverity guest introduced,this assumption is not
true any more. We need to extend the platform S5 process to
handle higher severity guest:
  - For DM launched RTVM, we need to make sure these guests
    is off before put the whole platfrom to S5.

  - For pre-launched VM, there are two cases:
    * if os running in it support S5, we wait for guests off.
    * if os running in it doesn't support S5, we expect it
      will invoke one hypercall to notify HV to shutdown it.
      NOTE: this case is not supported yet. Will add it in the
      future.

Tracked-On: #3564
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2019-09-11 17:30:24 +08:00
Yin Fengwei
ce9375874c hv: pm: correct the function name
do_acpi_s3 actually not limit to do s3 operation. It depends on
the paramters pm1a_cnt_val and pm1b_cnt_val. It could be s3/s5.
Update the function name from xx_s3 to xx_sx.

Tracked-On: #3564
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-09-11 17:30:24 +08:00
Yin Fengwei
81435f5504 vm reset: refine platform reset
We did following to do platform reset:
1. Try ACPI reset first if it's available
2. Then try 0xcf9 reset method
3. if 2 fails, try keyboard reset method
This introduces some timing concern which needs be handled carefully.

We change it by following:
assume the platforms which ACRN could be run on must support either
ACPI reset or 0xcf9 reset. And simplify platform reset operation
a little bit:
    If ACPI reset register is generated
        try ACPI reset
    else
        try 0xcf9 reset method

Tracked-On: #3609
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2019-09-09 09:49:59 +08:00
Mingqiang Chi
bd09f471a6 hv:move some APIs related host reset to pm.c
move some data structures and APIs related host reset
from vm_reset.c to pm.c, these are not related with guest.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-08-22 14:09:18 +08:00
Victor Sun
1f93f7f46c HV: remove some redundant includes
vm_config.h has included types.h/acrn_common.h/vm_configurations.h,
acrn_common.h has included types.h, so remove the redundant includes;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-05-08 16:57:46 +08:00
Victor Sun
e2d723d4fa HV: enable acpi pm1a register info fixup
Previously ACPI PM1A register info was hardcoded to 0 in HV for generic boards,
but SOS still can know the real PM1A info so the system would hang if user
trigger S3 in SOS. Enabling PM1A register info fixup will let HV be able to
intercept the operation on PM1A and then make basic function of S3 work for
all boards;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-07 11:39:51 +08:00
Mingqiang Chi
da9ed0eda9 hv:remove some unnecessary includes
remove some unnecessary includes

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-05-07 09:10:13 +08:00
Kaige Fu
581c0a239a HV: move AP_MASK to cpu.h
It is better to use an unified MACRO. So, this patch moves AP_MASK to cpu.h
and removes the defination of the MACRO spanning different source files.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 11:55:23 +08:00
Kaige Fu
7b6fe14517 HV: Remove unnecssary indent in pm.c
This patch just removes unnecessary indent before #include in pm.c.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 10:50:38 +08:00
Kaige Fu
a85d11ca7a HV: Add prefix 'p' before 'cpu' to physical cpu related functions
This patch adds prefix 'p' before 'cpu' to physical cpu related functions.
And there is no code logic change.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 10:50:28 +08:00
Kaige Fu
e52917f7d1 HV: Reshuffle start_cpus and start_cpu
This patch makes the following changes:
  - Add one parameter 'mask' to start_cpus for later use.
  - Set cpu state as DEAD instead of dead loop when fail to start cpu.
  - Panic when there are any failures when start cpus in init_cpu_post and host_enter_s3.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Jason Chen CJ
286731d9d1 hv:move instr_emul_ctxt instance to struct vcpu
move instr_emul_ctxt instance from struct per_cpu_region
to struct vcpu, and rename it from g_inst_ctxt to inst_ctxt

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-13 14:04:20 +08:00
Mingqiang Chi
b24a8a0f59 hv:cleanup header file for guest folder
cleanup arch/x86/guest, only include some necessary
header files, doesn't include hypervisor.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
	modified:   arch/x86/guest/assign.c
	modified:   arch/x86/guest/ept.c
	modified:   arch/x86/guest/guest_memory.c
	modified:   arch/x86/guest/instr_emul.c
	modified:   arch/x86/guest/io_emul.c
	modified:   arch/x86/guest/pm.c
	modified:   arch/x86/guest/trusty.c
	modified:   arch/x86/guest/ucode.c
	modified:   arch/x86/guest/vcpu.c
	modified:   arch/x86/guest/vcpuid.c
	modified:   arch/x86/guest/virq.c
	modified:   arch/x86/guest/virtual_cr.c
	modified:   arch/x86/guest/vlapic.c
	modified:   arch/x86/guest/vm.c
	modified:   arch/x86/guest/vmcall.c
	modified:   arch/x86/guest/vmcs.c
	modified:   arch/x86/guest/vmexit.c
	modified:   arch/x86/guest/vmsr.c
	modified:   arch/x86/guest/vmtrr.c
	modified:   arch/x86/pm.c
	modified:   include/arch/x86/guest/assign.h
	modified:   include/arch/x86/guest/ept.h
	modified:   include/arch/x86/guest/guest_memory.h
	modified:   include/arch/x86/guest/instr_emul.h
	modified:   include/arch/x86/guest/io_emul.h
	modified:   include/arch/x86/guest/trusty.h
	modified:   include/arch/x86/guest/vcpu.h
	modified:   include/arch/x86/guest/vmcs.h
	modified:   include/arch/x86/io_req.h
	modified:   include/arch/x86/irq.h
	modified:   include/arch/x86/lapic.h
	modified:   include/arch/x86/mmu.h
	modified:   include/arch/x86/pgtable.h
	modified:   include/common/ptdev.h
	modified:   include/debug/console.h
2019-02-21 10:38:30 +08:00
Arindam Roy
de8d85753e HV: Modularize vtd.c to remove acrn_vm usage
This patch is a modified one. It removes the usage
of acrn_vm struct from inside vtd.c.
It also puts struct iommu_domain inside vtd.h,
from vtd.c.
It modifies the signature of init_iommu_domain
in order to remove dependency on acrn_vm from
inside vtd.c.
Incorporated comments from Jason and Eddie.
Changed the name of sos_vm_domain to
fallback_iommu_domain
Removed any reference of sos_vm from vtd.[c|h]
files, including comments.

Tracked-On: #2496
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-02-06 08:53:46 +08:00
Yonghua Huang
ea672c5b07 hv: update coding style for tampoline.c
- add API get trampoline_start16_paddr() instead
    of exporting this global variable.
  - other minor update.

Tracked-On: #2095
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-25 13:25:14 +08:00
Arindam Roy
bec21d147b Patch for modularising ioapic.[c/h] and related files.
This adds few functions to access the daata structures
defined inside ioapic.c. Removes the same data structures
from ioapic.h
Also this modifies some of the names of existing APIs to
conform to the ioapic module name.
Modified gsi_table identifier to gs_table_data, to avoid
a MISRA C Violation.

Tracked-On: #1842
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-12-21 09:58:25 +08:00
Minggui Cao
f81fb21a58 HV: modularization to refine pm related code.
1. move out vm related code from arch/pm.
2. remove unnecssary global variables.
3. keep the global variables as static, not used
by other modules directlly.

Tracked-On: #1842
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-19 13:02:09 +08:00
Jason Chen CJ
36863a0b54 modulization: vmx on/off should not use vcpu param
vmx.c should only take care host vmx operations, which should not
contain vcpu reference, so refine vmx on/off APIs, move out use
of vcpu by adding one per cpu vmcs_run pointer.

as now each pcpu only run on one vcpu, so just keep running vmcs
in per cpu vmcs_run pointer is enough.

Changes to be committed:
	modified:   arch/x86/cpu.c
	modified:   arch/x86/init.c
	modified:   arch/x86/pm.c
	modified:   arch/x86/vmcs.c
	modified:   arch/x86/vmx.c
	modified:   include/arch/x86/per_cpu.h
	modified:   include/arch/x86/vmx.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-18 10:00:56 +08:00
Yin Fengwei
69dc939243 hv: drop the temperory stack for AP startup
By switching AP wakeup from broadcast to one by one, we could
set correct stack for each AP and drop the temp stack used during
AP boot.

Tracked-On: #2034
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-17 19:16:43 +08:00
Yonghua Huang
4fc5dcfc3e hv: enable SMAP in hypervisor
With SMAP enabled, hypervisor can't access pages that
owned by guest(either SOS or UOS), and an override is
is provided: stac()/clac() to enable/disable access to
guest's memory pages.

 Pre-conditon:
    Mark hypervisor owned pages as supervisor mode (U/S = 0),
       and set all othter memory pages as user mode (U/S = 1).

Tracked-On: #2056
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-14 15:24:26 +08:00
Li, Fei1
7a62154e36 hv: remove the theoretic infinite loop
There may the theoretic infinite loop with some code. But actually it doesn't.
This patch make these code more obvious it's not a potentially infinite loop.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-05 13:17:38 +08:00
Huihuang Shi
10bde520a5 hv: other: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Reduce the count of the "return entries".
Fix the violations which is comply with the cases list below:
1.Function has 2 return entries.
2.The first return entry is used to return the error code of
checking variable whether is valid.

Fix the violations in "if else" format.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-03 11:10:04 +08:00
Jason Chen CJ
51bfafd6fb modularization: boot component -- move functions
Boot component prepares the very basic platform boot env. It finally call
into platform initilization entries:

- bsp_boot_init & cpu_secondary_init for start up
- or restore_s3_context for wakeup

this patch move functions for AP trampoline into trampoline.c from reloc.c

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-12-03 09:09:44 +08:00
Shiqing Gao
6971cc832a hv: fix '(void) missing for discarded return value'
MISRA-C requires that the function call in which the returned
value is discarded shall be clearly indicated using (void).

This patch fixes the violations related to the following
function calls.
- instr_check_gva
- vlapic_set_local_intr
- prepare_vm
- enter_s3
- emulate_instruction
- ptdev_intx_pin_remap
- register_mmio_emulation_handler

v1 -> v2:
 * discard the return value of enter_s3

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-11-15 10:54:42 +08:00
Xiangyang Wu
99586e32cc HV:treewide:rename vm data structure
For data structure types "struct vm", its name is identical
with variable name in the same scope. This is a MISRA C  violation.

Naming convention rule:If the data structure type is used by multi
modules, its corresponding logic resource is exposed to external
components (such as SOS, UOS), and its name meaning is simplistic
(such as vcpu, vm), its name needs prefix "acrn_".

The following udpates are made:
struct vm *vm-->struct acrn_vm *vm

Tracked-On: #861

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2018-11-05 15:35:49 +08:00
Huihuang Shi
ea32c34ae1 HV:fix "Pointer param should be declared pointer to const"
Fix violations for function whose parameter can be read-only.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:45:14 +08:00
Victor Sun
bf834072d4 HV: platform acpi info refactor
Replace platform_acpi_info.c with platform_acpi_info.h and define needed
host ACPI info in MACROs. Then the struct host_acpi_info is not needed
any more.

This header file should be generated by offline tool automatically;

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Shiqing Gao
0317cfb2b6 hv: fix 'No brackets to then/else'
- add missing brackets for 'if/else' statements based on MISRA-C
  requirements

v1 -> v2:
 * add brackets for each conditions in 'if' statements to improve
   the readability
 * modify 'ptdev_init' to make the logic clearer

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-10-11 16:48:11 +08:00
Shiqing Gao
4544d28ee1 hv: fix 'User name starts with underscore'
There are chances that names with leading underscore declared by
developers are conflict with the ones reserved for the compiler.

What this patch does:
- rename these functions/variables/macros starting with
  underscore to avoid such unintentational mistakes.
- remove gpr.h without any contents

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-30 14:45:37 +08:00
Shiqing Gao
97aeb7f4ff hv: pgtable: fix 'Use of function like macro'
Convert HPA2HVA, HVA2HPA, GPA2HVA and HVA2GPA to inline functions.

v1 -> v2:
 * Modify the following statement.
   rsdp = biosacpi_search_rsdp((char *)hpa2hva((uint64_t)(*addr << 4)),
                                                                0x400);
   Instead of "(uint64_t)(*addr << 4)", "(uint64_t)(*addr) << 4U" would
   be clearer.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-07 11:11:06 +08:00
Jason Chen CJ
72f9c9a26e pm: use cpu_context for s3 save/restore
use structure cpu_context and update offsets in wakeup.S

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-07 09:55:13 +08:00
Mingqiang Chi
61782d7430 hv:Rename port/mmio read and write APIs
mmio_write_long --> mmio_write32
mmio_write_word --> mmio_write16
mmio_write_byte --> mmio_write8
mmio_read_long  --> mmio_read32
mmio_read_word  --> mmio_read16
mmio_read_byte  --> mmio_read8

io_write_long --> pio_write32
io_write_word --> pio_write16
io_write_byte --> pio_write8
io_read_long  --> pio_read32
io_read_word  --> pio_read16
io_read_byte  --> pio_read8
io_write      --> pio_write
io_read       --> pio_read

setl --> set32
setw --> set16
setb --> set8

igned-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-08-02 14:03:38 +08:00
Xiangyang Wu
6e77a8d5f1 HV:treewide:rename enum vpic_wire_mode, stack_canary, segment_override, pde_index
For data structure types "enum vpic_wire_mode, struct stack_canary",
its name is identical with variable name in the same scope.
This MISRA C  violation is detected by static analysis tool.
For variables "segment_override, pde_index", its name is identical
with function name. This MISRA C  violation is detected.
Naming convention rule:Variable name can be shortened from
its data structure type name.

The following udpates are made:
enum vpic_wire_mode vpic_wire_mode-->enum vpic_wire_mode wire_mode
struct stack_canary stack_canary-->struct stack_canary stk_canary
uint8_t segment_override:1 --> uint8_t seg_override:1
uint32_t pde_index--> uint32_t pde_idx

V1-->V2:
	Remove update "enum cpu_state cpu_state-->enum cpu_state state"
	and "enum irqstate irqstate-->enum irq_ops_mode ops_mode", other
	patch will cover it.
V2-->V3:
	Update "uint32_t pde_index--> uint32_t pde_idx".

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2018-07-31 11:20:21 +08:00
Victor Sun
401ffd1e39 HV: pm: cleanup for misra integral type violations
The patch fixes integral type related violations on HV pm part.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-12 17:31:11 +08:00