Commit Graph

491 Commits

Author SHA1 Message Date
Huihuang Shi
46d198244f HV:vcpu fix "Pointer param should be declared pointer to const"
Fix violations whose parameter can be read-only.
This patch only fix the parameter whose name is vcpu.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:45:14 +08:00
Huihuang Shi
ea32c34ae1 HV:fix "Pointer param should be declared pointer to const"
Fix violations for function whose parameter can be read-only.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:45:14 +08:00
Yin Fengwei
85bec0d0d1 hv: Move the guest_sw_loader() call from vcpu to vm
guest software loading is per VM instead of vcpu. So we move it
from prepare_vcpu to prepare_vm. And make sure it's called for
all VMs for partition mode.

Tracked-On: #1565
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-25 13:43:46 +08:00
Sainath Grandhi
09193c3913 hv: x2apic support for acrn
All the platforms supported by ACRN supports x2APIC. So enabled
x2APIC for ACRN hv. Removed any code that is needed for xAPIC mode
of operation.

Tracked-On: #1455
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed by:  Yonghua Huang <yonghua.huang@intel.com>
2018-10-25 13:41:29 +08:00
Li, Fei1
39fde060c3 hv: ept: remove EPT paging table for HPA to GPA
There's no need to walk these paging tables to transfer HPA to GPA
for a VM, so remove it.

Tracked-On: #1124
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-23 09:12:51 +08:00
Huihuang Shi
60b216a460 HV:fixed "Pointer param should be declared pointer to const"
Pointer param should be declared pointer to const if
the parameter is keeped read-only.
This patch changes pointer param whose name is vm.

Tracked-On:#861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-19 22:49:38 +08:00
Jason Chen CJ
6485666a93 Revert "hv: x2apic support for acrn"
This reverts commit 348e2ba168.
2018-10-19 17:24:56 +08:00
Mingqiang Chi
85ececd2d7 hv:Simplify for-loop when walk through the vcpu
-- Not return NULL for vcpu_from_vid
  We have replaced dynamic memory with static memory for vcpu,
  then if vcpu_id is valid, this API should not return NULL.
-- Simplify the for-loop when walk through the vcpu

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-19 14:23:08 +08:00
Mingqiang Chi
fabe607247 hv:Replace dynamic memory with static for microcode
Reserve 256KB static memory for microcode

v1-->v2:
  -- add spinlock when update microcode

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-18 09:32:27 +08:00
Victor Sun
bf834072d4 HV: platform acpi info refactor
Replace platform_acpi_info.c with platform_acpi_info.h and define needed
host ACPI info in MACROs. Then the struct host_acpi_info is not needed
any more.

This header file should be generated by offline tool automatically;

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Sainath Grandhi
348e2ba168 hv: x2apic support for acrn
All the platforms supported by ACRN supports x2APIC. So enabled
x2APIC for ACRN hv. Removed any code that is needed for xAPIC mode
of operation.

Tracked-On: #1455
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed by:  Yonghua Huang <yonghua.huang@intel.com>
2018-10-17 08:46:42 +08:00
Huihuang Shi
c6c1e42b79 HV:fix 'missing for discarded return value' violations
Return value should be checked,fix it by add
"void" when the function return value is not used.

V1->V2:
    replace printf with pr_warn.
V2->V3:
    change the commit to make read easily.

Tracked-On:#861

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-16 13:31:02 +08:00
Wei Liu
96412ac147 hv: add suffix(U/UL) to come up MISRA-C into include
MISRA-C required the suffix(U/UL), such as:
(1) ---> (1U)
(1) ---> (1UL)
(1U << 0) ---> (1U << 0U)
This patch will add the suffix(U/UL) to come up MISRA-C into
hypervisor/include directory.

Tracked-On: #1468
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 22:33:30 +08:00
Yonghua Huang
38d5df723d hv:enable APICv-Posted Interrupt
to enable APICv Posted interrupt supported, following the
 specifications defined in Intel SDM Section #29.6, Volume3.

 Posted-interrupt processing is a feature by which a processor
 processes the virtual interrupts by recording them as pending
 on the virtual-APIC page.

 Injecting interrupts to VCPU from remote CPU without causing
 VM exit on the destination, following steps in SDM Section 29.6,volume3:

Tracked-On: #1447
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 22:18:24 +08:00
Mingqiang Chi
1d725c89c0 hv:Replace dynamic memory with static for vcpu
-- Replace dynamic memory allocation with static memory
-- Remove parameter check if vcpu is NULL

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 13:44:25 +08:00
Yin Fengwei
dbd9ab07e1 hv: Cleanup: Remove dead code.
Now, UOS will use hypercall to init BSP state, we could remove
set_bsp_real_mode_entry() and set_bsp_protect_mode_regs().

For SOS, GDT will inherit from SBL or UEFI. For UOS, DM will
prepare GDT. We don't need hypervisor to prepare GDT for guest.

The entry_addr of vcpu struct could be removed. The guest entry
is set through BSP rip register.

GUEST_CFG_OFFSET is not needed any more after this patchset.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
b1ccde55a8 hv: Cleanup: set vcpu mode in vcpu_set_regs
Move vcpu mode set to function vcpu_set_regs.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
113adea0de hv: not start vm automatically when reset vm
For UOS, there is no BSP init state saved in hv. We always need
DM to set BSP init state by using hypercall. So we can't auto
start vm during vm reset.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
b454a067be hv: remove the vm loader for UOS in hv.
Now, we make UOS to set BSP init state by using hypercall. We
could drop the old UOS loader in HV and make vm loader in HV
only for SOS.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
3cfbc004f5 hv: add hypercall to set vcpu init state
DM will use this hypercall to initialize the UOS BSP state.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-15 09:04:10 +08:00
Yin Fengwei
90eca21d16 hv: simplify the function init_guest_state
The vcpu state is initialized outside of init_guest_state:
 - SOS BSP state is initialized in SOS loader
 - UOS BSP state is initialized in UOS loader
 - AP state is initialized during SIPI signal emulation

We could make init_guest_state only update the vcpu state
to VMCS structure.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 16:27:45 +08:00
Yin Fengwei
a5fc3e5eac hv: Add function to set UOS BSP init state
NOTE: this patch is only workaround patch for UOS BSP state init.
Eventually, the DM will call hypercall to init UOS BSP state.

We use this workaround patch here to simplify the init_guest_state.
Will make the caller of init_guest_state calls init_guest_vmx
directly.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 16:27:45 +08:00
Yin Fengwei
26627bd1fc hv: add function to set AP entry
With reset_vcpu_regs as pre-condition, we only need to set
cs_selector and cs_base for AP.

We call set_ap_entry in two places:
 1. When emulation AP SIPI
 2. When sos BSP resume from S3. The BSP is resumed to real
    mode with entry set to wakeup_vec. We call set_ap_entry
    API here with entry twisted from wakeup_vec.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 16:27:45 +08:00
Yin Fengwei
f7b11c8341 hv: add function to reset vcpu registers
This reset_vcpu_regs function will reset the vcpu registers to
default value: realmode with entry 0xFFFFFFF0

Make call to reset_vcpu_regs during create_vcpu and reset_vcpu

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 16:27:45 +08:00
Mingqiang Chi
790d8a5ce7 hv:Remove CONFIG_VM0_DESC
If defined CONFIG_VM0_DESC, HV will use predefined vm0_desc
to config VM0,now it is unneccessary, then remove these code.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 14:41:48 +08:00
Shiqing Gao
0317cfb2b6 hv: fix 'No brackets to then/else'
- add missing brackets for 'if/else' statements based on MISRA-C
  requirements

v1 -> v2:
 * add brackets for each conditions in 'if' statements to improve
   the readability
 * modify 'ptdev_init' to make the logic clearer

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-10-11 16:48:11 +08:00
Xiangyang Wu
a11a10fa4e HV:MM:gpa2hpa related error checking fix
In the current hypervisor design, when HPA is not
found for the specified gpa by calling gpa2hpa or
local_gpa2hpa, 0 will be returned as a error code,
but 0 may be a valid HPA for vm0; error checking
is missed when invoking gpa2hpa or local_gpa2hpa;
when invoking lookup_address, the caller guarantees
that parameter pointer pml4_page and pointer pg_size
is not NULL.

If local_gpa2hpa/gpa2hpa returns a invalid HPA,
it means that this function fails to find the
HPA of the specified gpa of vm. If local_gpa2hpa/gpa2hpa
return value is a valid HPA, it means that this
function have found the HPA of the specified gpa of vm.

Each valid vm's EPTP is initialized during vm creating,
vm's EPTP is valid until this vm is destroyed. So the caller
can guarantee parameter pointer pml4_page is not NULL.
The caller uses a temporary variable to store page size.
So the caller can guarantee parameter pointer pg_size
is not NULL.

In this patch, define a invalid HPA for gpa2hpa and
local_gpa2hpa;add some error checking when invoking
local_gpa2hpa/gpa2hpa;add precondition for lookup_address
function and remove redundant error checking.

V1-->V2:
	Define INVALID_HPA as a invalid HPA for gpa2hpa
	and local_gpa2hpa;
	Updated related error checking when invoking
	gpa2hpa or local_gpa2hpa;
V2-->V3:
	Add some debug information if specified gpa2hpa
	mapping doesn't exit and ept_mr_del is called;
	Update INVALID_HPA definition easier to be reviewed.
V3-->V4:
	Add vm->id and gpa into pr_error;
	Add precondition to ept_mr_del to cover [gpa,gpa+size)
	unmapping case.
V4-->V5:
	Update comments;
	Update pr_error message.

Tracked-On: #1258

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-10-11 15:16:11 +08:00
Huihuang Shi
c5f4c5109c HV:fix type related violations
1.Function return type inconsistent
2.cast on a constant value

V1->V2 add () to return type
V2->V3 keep the sbuf_get and sbuf_put return code

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-10 13:02:00 +08:00
Huihuang Shi
723c22fc7f HV:fix expression is not boolean
Expression should be boolean immediate before 'if','while' key-words.
V1->V2 add () to bool expression

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-10 13:02:00 +08:00
Li, Fei1
2b24b3780f hv: mmu: add some API for guest page mode check
add is_long_mode to check whether the processor is operating in IA-32e mode
add is_paging_enabled to check whether paging is enabled
add is_pae to check whether physical address extension is enabled.

Tracked-On: #1379
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-10-10 09:35:29 +08:00
Mingqiang Chi
eff2ac7a90 hv: Remove vm_list
Loop the global vm_array[] instead of the vm_list.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-09 13:24:21 +08:00
Mingqiang Chi
b8e59e1638 hv:Replace dynamic memory with static for vm
-- Replace dynamic memory allocation with static memory
-- Remove the parameter check if the vm is NULL

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-09 13:24:21 +08:00
Mingqiang Chi
ff3f9bd1e6 hv: Remove const qualifier for struct vm
This patch is ready for next one,we will switch from
pointer to embedded structures such as structure vcpu,
some const qualifiers can be improper and raise compilation errors,
this patch remove const qualifier for struct vm.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-09 13:24:04 +08:00
Sainath Grandhi
5b28b37842 hv: Fix for PARTITION_MODE compilation
This patch fixes compilation issue for PARTITION_MODE.

Tracked-On: #1404
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-10-08 22:04:27 +08:00
Shiqing Gao
4544d28ee1 hv: fix 'User name starts with underscore'
There are chances that names with leading underscore declared by
developers are conflict with the ones reserved for the compiler.

What this patch does:
- rename these functions/variables/macros starting with
  underscore to avoid such unintentational mistakes.
- remove gpr.h without any contents

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-30 14:45:37 +08:00
Yin Fengwei
1c0a3d9a02 hv: Add API to set vcpu register
set_vcpu_regs function is added to set vcpu registers.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-09-29 15:34:02 +08:00
Yin Fengwei
ba1aa40707 hv: add struct acrn_vcpu_regs
Add struct acrn_vcpu_regs and make struct boot_ctx based on
struct acrn_vcpu_regs.

vm0_boot_context is also changed from struct boot_ctx to struct
acrn_vcpu_regs.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-09-29 09:24:00 +08:00
Yin Fengwei
b207f1b942 hv: struct seg_desc_vmcs name change
struct seg_desc_vmcs is actually for segment descriptor vmcs fields.
Change its name to vmcs_seg_field

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-29 09:24:00 +08:00
Junjun Shan
5c92329606 hv:clear up the usage of printf data struct
The printf related functions have been called by other various
functions, e.g. get_ptdev_info(), get_ioapic_info, etc. The patch
is used to clear up the usage.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-28 16:40:07 +08:00
Yin Fengwei
9df8790ffc hv: Fix two minor issues in instruction emulation code
1. The wrong operand size is assigned in instruction decode phase
   if the operand size is 1 byte.

   According to the SDM, the bit 0(w bit) of opcode should be checked
   first to detect whether the operand size is 1 byte. Then, check
   whether there is prefix to overwrite the default operand size.

   The original instruction decode doesn't care about the operand
   size. But do opsize fixup during instruction emulation phase.
   With ACRN we need operand size packed to ioreq and send to DM
   after instruction decode.

2. We should always touch the GPA by following opsize to avoid side
   effect (especially when GPA is for a MMIO).

Tracked-On: #1337
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-28 13:10:54 +08:00
Yonghua Huang
dd6a5fbe95 HV: Add hypercall to set/clear IRQ line
- wraps ASSERT/DEASSERT IRQ line hypercalls.
    - remove 'intr_type' from set/clear IRQ line interface.
    - deprecate "IRQ_ASSERT", "IRQ_DEASSERT" & "IRQ_PULSE".
    - new adding hypercall will support "GSI_SET_HIGH"/
      "GSI_SET_LOW"/ "GSI_RAISING_PULSE"/ "GSI_FALLING_PULSE"
      operations

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-27 16:49:52 +08:00
Shiqing Gao
05ad6d6628 hv: drop the macro arguments acting as formal parameter names
This patch fixes the following issue pointed by Xiangyang and Junjie.
There are some macro arguments acting as formal parameter names.
Drop such arguments since they make no difference to the expanded
implementation and they might confuse some developers.

Here is an example.
'ptr' is dropped in this patch, which is acting as a formal parameter
name and make no difference to the expanded implementation.

-#define build_atomic_load(name, size, type, ptr)       \
+#define build_atomic_load(name, size, type)            \
 static inline type name(const volatile type *ptr)      \
{                                                       \
        type ret;                                       \
        asm volatile("mov" size " %1,%0"                \
                        : "=r" (ret)                    \
                        : "m" (*ptr)                    \
                        : "cc", "memory");              \
        return ret;                                     \
}

Some minor coding style fixes are also included in this patch.
- use TAB for the alignment rather than mixing TAB with space
- fix some typo in the comments

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-27 16:07:22 +08:00
Shiqing Gao
74622d7d29 hv: merge hv_lib.h and hypervisor.h
merge hv_lib.h and hypervisor.h into one file

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-27 15:55:41 +08:00
Yin Fengwei
6bcfa1520b hv: Enable the compiler warning as error for HV
Fix the compiler warning and turn on the flag to make
compiler warning as compiler error.

Tracked-On: #1343
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-27 11:22:44 +08:00
Zhao Yakui
a189be26ff HV: Add one hcall to set the upcall vector passed from sos_kernel
Currently the acrn-hypervisor is using the PLATFORM_IPI vector to notify
the sos_kernel. And then sos_kernel will handle the notification from acrn
hypervisor in PLATFORM_IPI ISR. But as the PLATFORM_IPI ISR can be registered
by the other modules, it will have the conflict when trying to register
acrn intr ISR. So the HYPERVISOR_CALLBACK_VECTOR will be used instead.

In order to switch the notification vector from PLATFORM_IPI to
HYPERVISOR_CALLBACK_VECTOR, one API is added so that sos can configure
the up-notifier interrrupt vector.

Tracked-On: https://github.com/projectacrn/acrn-hypervisor/issues/1325
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-26 11:23:34 +08:00
Junjun Shan
89ca54cafa hv:Fix unused var value on all paths
MISRAC checks whether a variable is assigned a value not used in
all branches of a program. Var value which is unused on all paths
can be removed with a consequent improvement in the readability
and efficiency of the code. This patch is used to fix these
violations.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-26 11:10:21 +08:00
Shiqing Gao
8787c06d3b hv: arch: fix 'Unused procedure parameter'
MISRA-C requires that there should be no unused parameters in
functions.

In some cases, we will keep the unused parameters.
vmexit handler is one example. It is used as function pointer.
Some of the vmexit handlers use the input parameter 'vcpu', some of
them don't. We still need to keep the unused parameters 'vcpu' for
those handlers don't use 'vcpu'.

This patch removes the unused parameters that is not being used
unconditionally.

v1 -> v2:
 * remove the non-implemented API 'vlapic_id_write_handler'

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-26 10:48:55 +08:00
Shiqing Gao
71b047cb61 hv: fix 'Switch case not terminated with break'
MISRA-C requires that every switch case shall be terminated with break
to avoid the unintentional fall through.

The code will become redundant if we enforce this rule.
So, we will keep the current implementation for the following two cases.
1. The fall through is intentional.
2. The function is returned in the switch case.
    If we decide to eliminate the mutiple returns in one function later,
    this case would be handled properly at that time.

What this patch does:
- add the mssing break for the default case
- add the pre condition for some functions and remove the corresponding
  panic which will never happen since the function caller could guarantee
  the pre condition based on the code implementation

v1 -> v2:
 * remove the redundant cases above default in 'vlapic_get_lvtptr'
 * add the similar pre condition for 'lvt_off_to_idx' as
   'vlapic_get_lvtptr' since all the function callers could guarantee it
 * remove the assertion in 'lvt_off_to_idx' since the pre condition
   could guarantee that the assertion will never happen
 * add the similar pre condition for 'vpic_set_irqstate' as
   'vioapic_set_irqstate' since all the function callers could guarantee it
 * remove the assertion in 'vpic_set_irqstate' since the pre condition
   could guarantee that the assertion will never happen

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-25 11:10:44 +08:00
Minggui Cao
d123083fa9 HV: add hypercall to monitor UOS PTdev intr status
The hypercall can be used by SOS/DM to monitor UOS
pass-thru devices' interrupt data; and if an "interrupt
storm" happens in UOS, it can be used to delay the UOS
PTdev interrupt's injection for sometime.

The two functions are implemented by one hypercall with
two sub-commands, and with the data/params in the buffer.

Tracked-On: #866
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-25 11:09:35 +08:00
Minggui Cao
918403f925 HV: modify code for intr storm detect & handling
This patch is to enhance the feature of "interrupt storm
mitigation"; when interrupt storm happens on one UOS
it should keep as smaller effect to SOS as possible.

Add variables in PTdev entry & VM, used to record one
UOS's pass-thru devices' interrupt data; add a function
to collect the data.

Also add a timer used to delay UOS pass-thru devices'
interrupt injection if an "interrupt storm" detected
by SOS.

Tracked-On: #866
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-25 11:09:35 +08:00
Yonghua Huang
994a375103 HV:fix potential buffer overflow issues
- use sizeof(struct lapic_regs),instead of arbitrary size
   to lear 'apic_page' memory region in vlapic.c
 - fix potential buffer overflow issues in vpic.c & ioapic.c

Tracked-On: #1252
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 16:14:27 +08:00
Junjun Shan
eb8c4fb0d5 hv:Fix Implict conversion:actual to formal param
MISRAC has requirement about implict conversion: actual to formal
param. This patch is used to fix part of these violations.

1.Add a new structure seg_desc_vmcs to hold the VMCS field address of
segment selector to clean up seg_desc structure.

2.Add the definition of maximum MSI entry and the relevant judgement.

3.The violations in shell.c, logmsg.c will be fixed in other series of
patches with modification of function snprintf(), vsnprintf() and other
related usages.

v1->v2:
  *Move the definition of struct seg_desc_vmcs from instr_emul.h to
   instr_emul.c.
  *Modify the formal parameter type in function definition from uint8_t
   to char instead of using cast.
  *Drop the const declaration for char data in formal parameter.

v2->v3:
  *update the data missing conversion.
  *change type of internal parameter len to avoid casting in npklog.c.
  *change the conversion from signed char to unsigned int in
   uart16550_getc() to solve sign-extension.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 13:09:39 +08:00
Xiangyang Wu
bb0a2bc2ab HV:Hypercall:Remove redundant error checking
In the current hypervisor hypercall, first all vcpu is
allocated to SOS, vcpu's vm field is initialized to vm0.
When the vcpu is offlined, vcpu will be paused and vcpu's
vm field is set as NULL by DM. When UOS is created, vcpu's
vm field is set as UOS's vm. So when vmcall_vmexit_handler
is invoked, vcpu's vm filed is always non-NULL.
error checking for vm pointer is done in the function
"vmcall_vmexit_handler", vmcall_vmexit_handler will
guarantee that vm is vm0.

So all hypercall functions (these functions is just for handler
hypercall, except vmcall_vmexit_handler) don't need to check
whether invoking vm is NULL and don't need to check whether
invoking vm is vm0 or not.

Remove related invoking vm error checking for hypercall handling.

V1 --> V2:
	Add pre-condition for hypercall in the head file.
V2 --> V3:
	Add pre-condition for copy_from_gpa and copy_to_gpa.
V3 --> V4:
	Add pre-condition both in the head file and source file.

Tracked-On:#1258

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 09:43:24 +08:00
Yonghua Huang
2af08d9619 HV: refine 'struct lapic_regs' definition.
- remove 'PAD3' & 'PAD4'
 - define local APIC registers by 'struct lapic_reg' type.

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 09:09:44 +08:00
Qi Yadong
8858634493 HV: update opcode when decode_two_byte_opcode()
The vie->opcode should be updated when decode_two_byte_opcode(),
otherwise for two bytes opcode emulate(movzx/movsx) will fail.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-09-14 09:26:48 +08:00
Junjun Shan
4fd5102edc hv:treewide:fix multiple MISRAC violations
MISRAC has requirements about literal value requires a U suffix and
signed/unsigned conversion with cast. This patch is used to solve
these violations.

v1->v2
 *Drop the cast of sz from uint32_t to int32_t, the signed/unsigned
  violation of nchars will be solved by other patch together with
  printf/sprintf/console/vuart/uart code.

 *Delete the unnecessary L suffix of shifting operand.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Reviewed by: Junjie Mao <junjie.mao@intel.com>
2018-09-13 11:12:29 +08:00
Yin Fengwei
44a2d77c32 hv: add SMAP/SMEP check during guest page walking
According to SDM 4.6 Access Rights definition, if SMAP/SMEP
is enabled, more conditions are used to decide the access rights
like SMAP/SMEP, EFLAGS.AC, R/W bit in every paging-structure entry
for page walking.

This patch add the check to guest page walking function and inject
page fault accordingly.

Tracked-On: #1207
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-13 09:21:59 +08:00
Yin Fengwei
d958d31e1b hv: fix the issue of movs emulation
The current movs emulation has issues:
1. it use gva to get/put data.
2. it only support src and dst operand are memory which does not
   apply to our case (one of them should be mmio and triggers
   EPT voilation).

This patch fix the issue by:
1. convert the address from gva to hva before access it.
2. handle mmio emulation.

Also fix the issue introduced by previous instruction reshuffle
patchset:
1. the desc validation should be only applied to none-64bit mode.
2. gva2gpa should be given correct guest virtual address.

Specailly for movs, we cache the dst gpa if the check during
movs decoding success. And use it directly during movs
emulation.

Tracked-On: #1207
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Tested-by: Qi Yadong <yadog.qi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-13 09:21:59 +08:00
Mingqiang Chi
60c05ace1a hv:Replace vlapic pointer with instance in vcpu_arch
-- update 'vlapic' in 'struct vcpu_arch' from pointer
   to instance
-- add inline function(vcpu_vlapic) in vcpu.h

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
aae5018bec hv:Move vlapic structure to vlapic.h
move structure vlapic_pir_desc/vlapic_timer/
acrn_vlapic from vlapic_priv.h to vlapic.h

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
fdb64095c4 hv:Replace dynamic memory allocation for apic access address
Replace pointer with static memory for apicv_apic_access_addr

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
887ebf0b08 hv: Replace dynamic memory allocation for MSR bitmap
Replace pointer with static memory for msr_bitmap
inside structure vm_arch.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
02e7edc063 hv: Replace dynamic memory allocation for I/O bitmaps
-- Replace pointer with static memory for io_bitmap
  inside structure vm_arch.
-- Refine allow_guest_pio_access/deny_guest_pio_access

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
eada04b800 hv:Replace dynamic memory allocation for vmcs region
Replace vmcs pointer with static memory for vmcs region
inside structure vcpu_arch.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Shiqing Gao
bcaede0c0e hv: treewide: fix 'Use of function like macro'
- convert function like macros to inline functions based on MISRA-C
  requirement
- remove some unused and duplicated macros

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-11 10:49:48 +08:00
Jason Chen CJ
8773dfb1f6 vlapic: unmap vlapic base only for SOS
as SOS mapped all memory at the beginning, so trap vlapic need unmap its
memory; for UOS, there is no need as UOS never mapped it.

Tracked-On: #1124
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Jason Chen CJ
457ac7408d vcpu: replace start_vcpu with run_vcpu
run_vcpu should be a more suitable name

Tracked-On: #1199
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Minggui Cao
99285f844a HV: improve pass-thru device interrupt process
for each pass-thru device and its entry owned by one VM, so
change the pass-thru device's softirq lock & entry list into
per VM, so one VM's PT device interrupt process will not
interfere with other VMs; especially in case one user OS
"interrupt storm" happens, it will have little effect on
service OS.

Tracked-On: #866
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-10 10:12:45 +08:00
Shiqing Gao
97aeb7f4ff hv: pgtable: fix 'Use of function like macro'
Convert HPA2HVA, HVA2HPA, GPA2HVA and HVA2GPA to inline functions.

v1 -> v2:
 * Modify the following statement.
   rsdp = biosacpi_search_rsdp((char *)hpa2hva((uint64_t)(*addr << 4)),
                                                                0x400);
   Instead of "(uint64_t)(*addr << 4)", "(uint64_t)(*addr) << 4U" would
   be clearer.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-07 11:11:06 +08:00
Shiqing Gao
f2f719cfa8 hv: fix 'Procedure is not called or referenced in code analysed'
MISRA-C requires that each function defined and declared shall be called
or referenced in code analyzed.

In some cases, we would like to keep the non-called functions for code
completeness, such as
vcpu_inject_extint/vcpu_inject_nmi/vcpu_inject_gp/vcpu_inject_pf
/vcpu_inject_ud/vcpu_inject_ac/vcpu_inject_ss.

This pacth removes some functions that are independent and are not
called in our code base.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-06 12:01:30 +08:00
Shiqing Gao
67038794af hv: treewide: convert some MACROs to inline functions
MISRA-C requires that each parameter in the MACRO shall be in brackets.

In some cases, adding brackets for all of the parameters may not be a
perfect solution.
For example, it may affect the code readability when there are many
parameters used in the MACRO.
And duplicated brackets will appear when one MACRO called another MACRO
which is using same parameters.

This patch convert some MACROs to inline functions to avoid such cases.

v1 -> v2:
 * Remove the unnecessary changes in hypervisor/bsp/uefi/efi/boot.h

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-04 12:27:18 +08:00
Shiqing Gao
54439ecae1 hv: treewide: fix 'Expression is not Boolean'
MISRA-C requires that the controlling expression of an if statement or
an iteration-statement shall be Boolean type.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-03 11:23:53 +08:00
Kaige Fu
f611012d28 HV: Refine two log info about vcpu and instr_emul
We have two same log message in decode_instruction. It's a little bit confusing.
So, this patch refine the log message to make it more explicit.

BTW, we refine one message in create_vcpu.

Tracked-On: #1136

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 11:23:15 +08:00
Shiqing Gao
96dba0d8fe hv: fix MISRA-C issues related to space or newline
This patch fixes the following issues:
- No newline after semi colon.
- No space after semi colon in for expression.
- No space between if, while, for and expresn.

v1 -> v2:
 * Fix the typo for the for loop change.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-09-03 09:35:15 +08:00
Li, Fei1
9257ecf4bb hv: mmu: cleanup mmu.h
Remove unused Macro defininion.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Sainath Grandhi
c102c44c16 hv: Device MSIs in partition mode ACRN
VMs in partition mode uses a kernel patch to switch to physical mode xAPIC.
The kernel patch together with this patch makes sure device MSIs use
physical mode as DM and physical APIC IDs in Destination field.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-09-03 09:32:15 +08:00
Shiqing Gao
10c64a5fca hv: fix MISRA-C issues related to for loop
This patch fixes the following issues:
- Assignment operation in expression.
- For loop incrementation is not simple.
- No brackets to loop body.
- Use of comma operator.

v1 -> v2:
 * Replace &x->y with &(x->y) based on our new coding rule

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-31 09:20:48 +08:00
Shiqing Gao
2a184f353c hv: code clean up regarding to guest_msrs
Change guest_msrs in vcpu data structure from pointer to array, which
could avoid the dynamic memory allocation.

v1 -> v2:
 * Remove the unnecessary initialization for guest_msrs[] since vcpu is
   allocated by calloc.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-28 11:08:48 +08:00
Mingqiang Chi
4e8798e018 hv:Replace vioapic pointer with instance in structure vm
-- rename struct vioapic --> struct acrn_vioapic
-- update 'vioapic' field in 'struct arch_vm' from pointer
   to instance
-- change vm_ioapic(vm) to inline, and move it to vm.h
-- change vioapic_init to void type

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Mingqiang Chi
29dbd1084d hv:Replace vuart pointer with instance in structure vm
-- update 'vuart' field in 'struct vm' from pointer
   to instance
-- replace MACRO with inline function for vm_vuart,
   and move it to vm.h
-- change vuart_init to void type
-- rename struct vuart -->struct acrn_vuart

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Mingqiang Chi
0b54946bac hv:Replace vpic pointer with instance in structure vm
-- update 'vpic' field in 'struct vm' from pointer
  to instance, and move it from 'struct vm' to 'struct arch_vm'
-- replace MACRO with inline function for vm_pic, and move it
   to vm.h
-- changed vpic_init to void type
-- removed vpic_cleanup
-- move struct acrn_vpic/i8259_reg_state from vpic.c to vpic.h

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Sainath Grandhi
925503ce36 hv: Build fix - ACRN partition mode
Patch to fix compile issue.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-24 11:17:33 +08:00
Yonghua Huang
7bc1a3f925 HV: Refine APICv capabilities detection
- by default, ACRN will not support platform without
   below APICv features:
    -- Use TPR shadow
    -- APIC-register virtualization

 - remove mmio emualtion of local APIC for guest

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-24 09:58:58 +08:00
Binbin Wu
f95d07dc43 hv: vtd: use EPT as translation table for PTDev in SOS
In current code, the address translation type for passthrough devices
in SOS is passthrough type, which means the device in SOS can access
the whole physcial memory.
This patch uses SOS EPT to translate address for passthrough
devices. So that the memory of VMM or trusty can be protected from
SOS PTDev.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:46:57 +08:00
Yin Fengwei
4579e57e7b hv: add gva check for the case gva is from instruction decode
For the instructions other than MOVS, one operand is register
and another one is memory which trigger EPT voilation. In this
case, there is one possibility that EPT voilation happens before
guest fault:
    the fault is triggered by related guest PTE access bit
    voilation (like write to a gva with R/W bit cleared in PTE).

So we do this kind of check and inject exception to guest
accordingly during instruction decoding phase.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
7dde0dfa4b hv: add GVA validation for MOVS
Unlike the other instructions we emulated, MOVS has two operands
both are memory.

So we need to check whether the operand is valid GVA. With VMX
enabled, the src operand is always checked first by VMX. Which
means if src operand is not valid GVA, it will trigger fault
in guest before trigger EPT. So we don't need to check src
operand. Only need to check dst operand here.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
b01a81279a hv: add new function to get gva for MOVS/STO instruction
Drop the get_gla function and add
 - get_gva_di_si_nocheck
   get gva from ES:DI and DS(other segment):SI without
   check faulure case
 - get_gva_di_si_check
   get gva from ES:DI and DS(other segment):SI with failure
   case checked

TODO:
  - Save dst_gpa and src_gpa for instruction emulation phase
    use.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
8480c98053 hv: move check out of vie_calculate_gla
We will do check only during instruction decode phase.
vie_calculate_gla will be called both in instruction emulation
phase, we move the check out of vie_calculate_gla.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
54c254169d hv: remove unnecessary check for gva
According to SDM vol3 25.1.1
With VMX enabled, following exception will be handled by guest
without trigger VM exit:
 - faults based on privilege level
 - general protection due to relevent segment being unusable
 - general protection due to offset beyond limit of relevent segment
 - alignment check exception

ACRN always assume VMX is enabled. So we don't need to these check
in instruction emulation. But we need to do page fault related check.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
5663dd7d14 hv: extend the decode_modrm
If rm show there is no SIB following rm field, we should get
base_register info from rm.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yonghua Huang
3b6ccf0c91 HV: remove callbacks registration for APICv functions
- call these functions directly, no need to register
     callbacks.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:11:21 +08:00
Li, Fei1
4bb8456de8 hv: ept: refine ept_mr_add base on mmu_add
Refine ept_mr_add base on mmu_add. The old map_mem could be removed
once this was done.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 11:10:26 +08:00
Zhi Jin
dcae438306 hv: add a hypercall for the hypervisor NPK log
The hypercall HC_SETUP_HV_NPK_LOG is added to enable/disable/configure
the hypervisor NPK log.

Signed-off-by: Zhi Jin <zhi.jin@intel.com>
Signed-off-by: Zhonghua Sun <zhonghua.sun@intel.com>
Reviewed-by: CHEN Gang <gang.c.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:09:25 +08:00
Yu Wang
a6c2065b2e hv: apicv: change the name of vapic to apicv
Remove the vapic name and unify to apicv.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Yu Wang
a0c625b85a hv: apicv: change the apicv related API with vlapic_apicv prefix
The apicv is one hardware acceleration feature of vlapic. All vlapic
APIs should keep vlapic_ as the prefix.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Yu Wang
74ff712085 hv: vlapic: local APIC ID related code cleaning up
From SDM Vol3 10.4.6:
Some processors permit software to modify the APIC ID. However, the
ability of software to modify the APIC ID is processor model specific.
Because of this, operating system software should avoid writing to the
local APIC ID register.

So to permit change APIC ID is not one *must* feature. Keep it simple,
we are also reject to modify it.

This patch does code cleaning up for LAPIC ID related emulation.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Mingqiang Chi
c43d0e4f01 hv:Changed several APIs to void type
Since these APIs always return 0,
change them to void type,
vcpu_set_cr0()
vmx_write_cr0()
vcpu_set_cr4()
vmx_write_cr4()
kick_notification()
tsc_deadline_handler()
dmar_fault_handler()
ptdev_interrupt_handler()

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-23 08:54:54 +08:00
Shiqing Gao
42aaf5d46f hv: code clean up regarding to % and / operations
- Clean up some code regarding to % and / operations since bit
  operations are faster.
        x % 64U ---> x & 0x3fU
        x % 32U ---> x & 0x1fU
        x % 16U ---> x & 0xfU
        x % 8U  ---> x & 0x7U
        x % 4U  ---> x & 0x3U
        x % 2U  ---> x & 0x1U

        x / 64U ---> x >> 6U
        x / 32U ---> x >> 5U
        x / 16U ---> x >> 4U
        x / 8U  ---> x >> 3U
        x / 4U  ---> x >> 2U
        x / 2U  ---> x >> 1U
- Minor changes regarding to coding styles

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-22 15:37:53 +08:00
Yonghua Huang
e0d40feaa8 HV:refine 'apic_page' & 'pir_desc' in 'struct acrn_vlapic'
- update 'apic_page' field in 'struct acrn_vlapic',
   from pointer type to 'struct lapic_regs' type.

 - delete 'pir' and update 'pir_desc' to 'vlapic_pir_desc'
   type.

 - fix potential memory leak in 'vlapic_create()'
   should free allocated memory in case of registering
   mmio handler failure.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-08-22 12:52:07 +08:00
Shiqing Gao
8924f6dabb hv: vmx: fix 'Array has no bounds specified'
MISRAC requires that the array size should be declared explicitly.

This patch fixes the issues caused by vm0_boot_context.

Fix pattern is like below:
   extern char start_of_ROM, end_of_ROM, start_of_FLASH;
   memcpy (& start_of_FLASH, & start_of_ROM, & end_of_ROM - &
start_of_ROM);

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-08-21 13:03:28 +08:00