Commit Graph

57 Commits

Author SHA1 Message Date
Zide Chen
d133f95d97 hv: fix MISRA-C violations "Pointer param should be declared pointer to const."
MIRSA-C requires the const qualifier should be applied to pointer parameters
that address data not subject to change in rule 120D.

Tracked-On #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-19 13:03:03 +08:00
Zide Chen
927c5172fa hv: vpci: fix MISRA-C violations related to variable declarations
78D: Global variable should be declared const.

Global variables should be declared constant wherever possible to
avoid unintentional modification.

27D: Variable should be declared static
  pci_ops_vdev_msi is not accessed by other files. Remove the declaration
  from the header and define it with the static qualifier; Because it's
  referenced by populate_msi_struct(), so move the define statements forward.

33D: No real declaration for external variable
  certain variables are available in sharing mode or partition mode only,
  so that the declarations in header files must be enclosed with
  CONFIG_PARTITION_MODE

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-19 09:21:24 +08:00
Zide Chen
3515ca1e65 hv: vpci: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-18 16:29:53 +08:00
Zide Chen
2028034151 hv: MISRA-C fix "identifier reuse" in vpci code
13X: Identifier reuse: tag vs component.
A tag name shall be a unique identifier

Change the following names:
  struct msi --> struct pci_msi
  struct msix --> struct pci_msix
  struct vpci --> struct acrn_vpci
  union cfgdata -> union pci_cfgdata

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-18 13:39:15 +08:00
Zide Chen
a3d2a7e726 hv: vpci: 2 MISRA-C violation fixes
36D Prototype and definition name mismatch
  pci_scan_bus() and sharing_mode_find_vdev() wrong parameter in prototype.
14D Attempt to change parameter passed by value.
  vmsix_table_rw() uses function parameter as local viarable.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-16 14:52:44 +08:00
Yonghua Huang
4fc5dcfc3e hv: enable SMAP in hypervisor
With SMAP enabled, hypervisor can't access pages that
owned by guest(either SOS or UOS), and an override is
is provided: stac()/clac() to enable/disable access to
guest's memory pages.

 Pre-conditon:
    Mark hypervisor owned pages as supervisor mode (U/S = 0),
       and set all othter memory pages as user mode (U/S = 1).

Tracked-On: #2056
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-14 15:24:26 +08:00
Li, Fei1
e3fc6c3c79 hv: use int32_t replace int
Since it's typedef in "include/lib/types.h"

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-12 13:08:10 +08:00
Li, Fei1
d36b44f23d hv: avoid to use "++" or "--" operators in an expression
Use these operators in an expression is considered dangerous.
So avoid to use it in an expression which is not in stand-alone
expressions and the 3rd expression of a for loop.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-12-07 16:39:58 +08:00
Shiqing Gao
f73cf21187 hv: fix 'Unused procedure parameter'
remove the unused procedure parameter

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-12-04 18:28:32 +08:00
Shiqing Gao
11102cfa45 hv: change the param type of mmio_write**
Input parameter of mmio_write64/mmio_write32/mmio_write16/mmio_write8
should be 'void *addr' rather than 'const void *addr' since the object
pointed by 'addr' is modified in these operations.

This patch change the param type of mmio_write** and update its usage
accordingly.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-12-04 09:10:54 +08:00
Binbin Wu
7003afbe74 hv: msix: fix bug when check if msix table access
The offset calculation should base on the MSI-x BAR address, not MSIX-table address.

Tracked-On: #1946
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-30 14:42:10 +08:00
Mingqiang Chi
5dcfc1336b hv:Rename ptdev to ptirq for some APIs
-- Rename the fowllowing APIs:
  ptdev_intx_pin_remap --> ptirq_intx_pin_remap
  ptdev_msix_remap  --> ptirq_msix_remap
  ptdev_add_intx_remapping --> ptirq_add_intx_remapping
  ptdev_remove_intx_remapping --> ptirq_remove_intx_remapping
  ptdev_add_msix_remapping --> ptirq_add_msix_remapping
  ptdev_remove_msix_remapping --> ptirq_remove_msix_remapping
  ptdev_intx_ack  --> ptirq_intx_ack
  ptdev_lookup_entry_by_sid --> ptirq_lookup_entry_by_sid
  ptdev_lookup_entry_by_vpin --> ptirq_lookup_entry_by_vpin
  ptdev_build_physical_msi --> ptirq_build_physical_msi
  ptdev_build_physical_rte --> ptirq_build_physical_rte
  alloc_entry   --> ptirq_alloc_entry
  release_entry --> ptirq_release_one_entry
  ptdev_activate_entry --> ptirq_activate_entry
  ptdev_deactivate_entry --> ptirq_deactivate_entry
  ptdev_intr_handle_irq --> ptirq_handle_intx
  ptdev_softirq --> ptirq_softirq
  ptdev_enqueue_softirq --> ptirq_enqueue_softirq
  ptdev_dequeue_softirq --> ptirq_dequeue_softirq
  get_vm_ptdev_intr_data --> ptirq_get_intr_data
  alloc_ptdev_entry_id --> ptirq_alloc_entry_id
  ptdev_intr_delay_callback --> ptirq_intr_delay_callback
  ptdev_dequeue_softirq --> ptirq_dequeue_softirq
  ptdev_interrupt_handler --> ptirq_interrupt_handler

-- Merge 'ptdev_release_all_entries' and 'release_all_entries'
   to 'ptirq_release_all_entries'

v2-->v3:
   Rename ptirq_release_one_entry to ptirq_release_entry
v1-->v2:
   still use ptdev_init instead of ptirq_init

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-30 13:27:49 +08:00
Mingqiang Chi
5b43aa8a65 hv:Rename ptdev to ptirq for some variables and structures
ptdev_remapping_info --> ptirq_remapping_info
ptdev_msi_info --> ptirq_msi_info
ptdev_vpin_source --> ptirq_vpin_source
ptdev_irq_entries --> ptirq_entries
ptdev_entry_bitmaps --> ptirq_entry_bitmaps

v1-->v2:
   still use ptdev_lock instead of ptirq_lock
Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-30 13:27:49 +08:00
Huihuang Shi
8dfb9bd9c0 hv: dm: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Reduce the count of the "return entries".
Fix the violations which is comply with the cases list below:
1.Function has 2 return entries.
2.The first return entry is used to return the error code of
checking variable whether is valid.

Fix the violations in "if else" format.
V1->V2:
    make the return value match to int32_t

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-29 15:03:48 +08:00
Huihuang Shi
5b6c611a1d hv: msix: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Reduce the count of the "return entries".
Fix the violations which is comply with the cases list below:
1.Function has 2 return entries.
2.The first return entry is used to return the error code of
checking variable whether is valid.

V1->V2:
  remove the unrelated code.

Fix the violations in "if else" format.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-28 14:34:12 +08:00
Zide Chen
3b24c34cbf hv: msix: corrently determine when the guest is changing Message Data/Addr
The guest could write the MSI-X Table fields in DWORD or QWORD. For
example the Message Address could be a QWORD write or two DWORD writes,
the Message Data could be a DWORD write or part of a QWORD write that
is combined with the Vector Control. This patch captures all the
possible combinations when the guest is configuring the MSI-X Table.

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-11-20 12:59:09 +08:00
Zide Chen
c41c0dab08 hv: properly initialize MSI-X table
Though guests are not supposed to read Message Data/Addr, it's still better
off to initialize them to 0.

vector_control should be initialize to zero besides the mask bit.

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-11-20 12:59:09 +08:00
Zide Chen
53971e1974 hv: fix 2 bugs in msix.c
- in vmsix_cfgwrite(), it should write the new value 'val'.
- in vmsix_table_mmio_access_handler(), mmio_gpa is a typo for intercepted_gpa.

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-11-20 12:59:09 +08:00
Zide Chen
5d013ed2ba hv: vpci: revert the temporary workaround of handling I/O port CF9
Revert the temporary workaround of calling allow_guest_pio_access() to
reset the I/O bitmap for CF9.

For CONFIG_ADDR register, only intercept I/O port CF8 to achieve these:

- In SOS, I/O bitmap for port CF9 is not set.
- In UOS or in partition mode, I/O requests to CF9/CFA/CFB won't be handled
  by pci_cfgaddr_io_read/write() any more.

Tracked-On: #1815
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-19 09:34:34 +08:00
Zide Chen
fe9a340ea9 hv: separate the PCI CONFIG_ADDR and CONFIG_DATA I/O port handlers
Register separate I/O emulation handlers for I/O port CF8 and CFC. This
makes the code simpler, and offers some flexibilities to be able to handle
CF8 and CFC ports differently.

Tracked-On: #1815
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-19 09:34:34 +08:00
Zide Chen
a646fcf761 hv: fix 'No brackets to then/else' in vpci code
This patch addes missing brackets for 'if/else' statements based on
MISRA-C requirements 12 S.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Reviewed-by: Huihuang Shi <huihuang.shi@intel.com>
2018-11-15 08:58:32 +08:00
Zide Chen
bad813ea31 hv: fix MISRA-C violations in vpci code: Function pointer is of wrong type
576S: Function pointer is of wrong type. C90 requires the elements of an
designated initializer to appear in a fixed order, the same as the order of
declaration. C99 relaxes this rule but seems MISRA-C sticks to C90 in this
regard.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Reviewed-by: Huihuang Shi <huihuang.shi@intel.com>
2018-11-15 08:58:32 +08:00
Zide Chen
d3f0edfe4f hv: fix MISRA-C violations in vpci code: 93S, 331S and 612S
- 331S: Literal value requires a U suffix.
- 612S: inline function should be declared static.
- 93S: Value is not of appropriate type. MISRA-C imposes strict type
  checking: no comparison between signed and unsigned, etc.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Huihuang Shi <huihuang.shi@intel.com>
2018-11-15 08:58:32 +08:00
Zide Chen
f84f1a216b hv: fix MISRA-C violations in vpci code: implicit conversion
458S: Implicit conversion: actual to formal param (MR): "The value of an
actual parameter shall not be implicitly converted to the type of a formal
parameter, if that conversion might result in the loss of information".

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Huihuang Shi <huihuang.shi@intel.com>
2018-11-15 08:58:32 +08:00
Shiqing Gao
155675350d hv: unify the function pointer assignment
Assign function pointer without the unary & operator.

Take 'register_io_emulation_handler' as an example:
void register_io_emulation_handler(struct acrn_vm *vm,
                const struct vm_io_range *range,
                io_read_fn_t io_read_fn_ptr,
                io_write_fn_t io_write_fn_ptr)

The last two parameters are function pointer.
Sometimes we use function designator directly, while sometimes
with the unary & operator, as shown below.
 - without &
   register_io_emulation_handler(vm, &range, vuart_read, vuart_write);
 - with &
   register_io_emulation_handler(vm, &pci_cfg_range,
                   &pci_cfg_io_read, &pci_cfg_io_write);

To unify the coding style, we will go with the first way.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-13 13:34:36 +08:00
Mingqiang Chi
9a009bcef2 hv:Replace dynamic memory with static for mmio
-- Config MAX_EMULATED_MMIO_REGIONS 16 in Kconfig
-- Add emulated mmio array and emulated mmio regions
   in vm structure
-- Remove mmio list in vm structure
-- Remove unregister_mmio_emulation_handler and
   vioapic_cleanup APIs

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-13 11:52:48 +08:00
Mingqiang Chi
73530055b6 hv:Replace dynamic memory with static for port io
-- Add emulated port io index
-- Add emulated pio array in vm structure
-- Remove port list in vm structure
-- Remove free_io_emulation_resource/register_io_handler/
   create_io_handler APIs

v2-->v3:
 -- not add 'is_emulated', check len == 0U
 -- Check if io_read/io_write handler is NULL before calling
 -- Replace ENUM with MACRO for emulated pio index to avoid
    MISRA-C violations

v1-->v2:
  -- Remove EMUL_PIO_NUM in Kconfig, add emulated pio index
     for PIC/PCI/UART/RTC/PM

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-09 13:05:04 +08:00
Shiqing Gao
b430b00a08 hv: fix 'Expression is not Boolean'
MISRA-C requires that the controlling expression of an if statement or
an iteration-statement shall be Boolean type.

v1 -> v2:
* update the U suffix of constant to let the type of operands
  to bit operations (&) is the same.
* update the type of 'i' from uint64_t to uint16_t in
  'profiling_set_control' since it is limited by phys_cpu_num,
  which is uint16_t.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-08 13:04:11 +08:00
Xiangyang Wu
99586e32cc HV:treewide:rename vm data structure
For data structure types "struct vm", its name is identical
with variable name in the same scope. This is a MISRA C  violation.

Naming convention rule:If the data structure type is used by multi
modules, its corresponding logic resource is exposed to external
components (such as SOS, UOS), and its name meaning is simplistic
(such as vcpu, vm), its name needs prefix "acrn_".

The following udpates are made:
struct vm *vm-->struct acrn_vm *vm

Tracked-On: #861

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2018-11-05 15:35:49 +08:00
Jason Chen CJ
8efd9edb82 hv: vPCI needs to handle reset IO port CF9 differently
Currently vpci treats IO port CF9 as a regular PCI CONFIG_ADDRESS port,
so that SOS can't do system reboot through port CF9.

This patch handles port CF9 in this way:
- SOS (vm0): it is allowed to actually access the physical IO port for byte
  accesses.
- UOS (non-vm0) or partitioning guests: any accesses to port CF9 are
  ignored.

Tracked-On: #1568
Signed-off-by: Zide Chen zide.chen@intel.com
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-11-05 14:42:50 +08:00
Shiqing Gao
e8229879a6 hv: use MMIO read/write APIs to access MMIO registers
MMIO registers might be changed at any time.
The changes might not be catched due to compiler optimization
if there is no 'volatile' keyword.

We have defined MMIO read/write APIs to address the above issue.
'volatile' keyword is being used in these defined MMIO read/write
APIs.

This patch updates the MMIO registers access implementation in
'msix.c' to use these defined MMIO read/write APIs.

v1 -> v2:
 * update the algorithm to get the address of high 32-bit of
   'pentry->addr'
   - previous way:
           &(pentry->addr) + 4U
           ===> &(pentry->addr) + 4 * 64 bits
           since 'pentry->addr' is 64 bits
   - new way:
           (char *)&(pentry->addr) + 4U
           ===> &(pentry->addr) + 4 * 8 bits
           since 'char' is 8 bits

Tracked-On: #1711
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-11-05 09:50:28 +08:00
Li, Fei1
0391f84c83 hv: mmu: replace dynamic memory allocation in memory
Replace dynamic memory allocation in memory management with static memory allocation.
Since the static memory allocation can guarantee the allocation never failed, so
split_large_page and construct_pgentry don't need to return a errno any more.
Besides, the destroy_ept don't need to free page any more. Instead, it would memset
the eptp to 0 to make sure we can't walk this paging table again.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-11-02 13:15:48 +08:00
Zide Chen
0255e62798 hv: resolve the negative impacts to UOS MSI/MSI-X remapping
After enabling vPCI in hypervisor for vm0, UOS may not able be launched
successfully. Consider this scenario (take MSI-X for example):

- DM makes hypercall to hypervisor to do MSI-X remapping on behalf of
  UOS guests.
- After the hypercall, VHM module in SOS kernel updates the physical
  MSI-X table with the physical Message Data/Addr.
- These MMIO write requests are intercepted by hypervisor, which will
  call ptdev_msix_remap() to do MSI-S remapping.

It may fail due to 2 possible reasons:

1) wrong target VM because:
  hypervisor thinks it's a VM0 MSI-X device but they have been registered
  as UOS guests through HC_SET_PTDEV_INTR_INFO hypercall.

2) wrong ptdev_msi_info->vmsi_data because:
  The virtual MSI-X table is supposed to hold virtual Message data/addr
  but the SOS VHM writes the physical ones to it.

This patch resolves these problems by ignoring the HC_VM_PCI_MSIX_REMAP
hypercall, so virtual and physical Message Data are the same from SOS'
perspective and it won't mess up the virtual PCI device in HV.

Also in HC_SET_PTDEV_INTR_INFO handler, vpci updates the target VM
when the PCI devices are assigned to different VMs.

The UOS' MSI/MSI-X remapping is triggered by hypervisor when SOS (either
DM or VHM) updates the Message Data/Addr.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
8c398f7d7e hv: fix issues when msi-x shares same BAR with other data structures
If PBA or other data structures reside in the same BAR with MSI-X,
devicemodel could emulate them and make hypercall SET_MEMORY_REGION
to setup EPT for vm0.

Hypervisor can not intercept the whole range of this BAR, but only
the minimum 4KB pages that cover the MSI-X Table.

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
5cbe079e24 hv: MSI-X Message Address write fix
Some PCI devices can not accept DWORD write to the MSI-X Table though
PCI Spec allows it:

PCI Spec 3.0 6.8.3.2 MSI-X Configuration: Specifically, software is
always permitted to fill in the Message Address and Message Upper Address
fields with a single QWORD write.

Tracked-On: #1568
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
dbe156e9f6 hv: fix misrac violations in vcpi code
Fixed the following violations:
- Widening cast on complex integer expression
- Casting operation to a pointer
- Static procedure is not explicitly called in code analysed

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
5555a2f85d hv: fix bug in sizing MSI-X Table Base Address Register
To sizing a 64-bit BAR, need to form the two 32-bit registers as a
64-bit words, before doing the calculation: inverting all bits and
incrementing by 1.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Li, Fei1
9e39732259 hv: l1tf: sanitize mapping for idle EPT
sanitize mapping for idel EPT

Tracked-On: #1672
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-11-01 11:21:15 +08:00
Zide Chen
83dbfe4fd3 hv: implement sharing_mode.c for PCI emulation in sharing mode
Compared with partition_mode.c, the major difference between them is
the list of PCI devices is statically defined or dynamically
enumerated and allocated.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
7c506ebc69 hv: implement msix.c for MSI-X remapping
Similar to MSI emulation, this patch emulates the Message Control word
within MSI-X Capability Structure.

Also it emulates MSI-X table. MSI-X remapping is triggered when the guest
is changing the Mask bit in Vector Control, or the Message Data/Addr when
MSI-X Enable bit is set.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
dcebdb8e98 hv: implement msi.c to handle MSI remapping for vm0
Emulate MSI Capability structure for vm0 in sharing mode:

- it intercepts the IO requests for MSI Capability structure, emulates
  the Message Control word, and bypasses all other I/O requests to the
  physical device.

- criteria to trigger MSI remapping: MSI Enable bit is being changed,
  Message Data/Addr is being changed when MSI Enable is set.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
6af47f249c hv: vpci: add callback functions to struct vpci
Add 'struct vpci_ops *ops' to 'struct vpci' so we have clearer structure:

- struct vpci: include struct vpci_ops pointing to different callback
  functions for partition or sharing mode repsectively.
- struct pci_vdev: includes struct pci_vdev_ops to handle different vpci
  functionalities:
      hostbridge emulation
      passthrough device BAR emulation
      msi/msi-x remapping

This patch moves the code around but doesn't change the underlying logic
in terms of PCI spec handling. More detailed implementation:

- create new file partition_mode.c to house the implementation of partition mode
  regarding the vpci layer.
- vpci.c: only keeps the abstract code which calls vpci->ops to functions
  in partition_mode.c, and potentially to sharing_mode.c.
- the following functions are moved to partition_mode.c and renamed with
  partition_mode prefix.
    - vpci_init() -> partition_mode_vpci_init()
    - vpci_cleanup() -> partition_mode_vpci_deinit()
    - pci_cfg_io_write() -> partition_mode_cfgread()
    - pci_cfg_io_read() -> partition_mode_cfgwrite()

Track-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
9cc1f57f63 hv: change function parameters: pci_pdev_read_cfg and pci_pdev_write_cfg
In order to allow these functions to be called without an associated
struct pci_pdev (for example, at the time of PCI bus enumeration), these
two functions can not take the struct vdev as input parameter.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00
Zide Chen
a6677e6e69 hv: create new file core.c and pci.c
- move the functions to access physical PCI configuration space from
  pci_pt.c to the new file dm/hw/pci.c, so they can be accessed in
  sharing mode as well. The new folder dm/hw is created in order to
  move APIs talking to physical PCI devices out of dm/vpci.
- move the common vpci code from header file pci_priv.h to core.c.
- move file include/dm/vpci/vpci.h one level up. It seems the folder
  include/dm/vpci is not necessary.
- This patch only moves code around, and doesn't make any logical
  changes. Besides removes the static keyword from pci_pdev_read_cfg()
  and pci_pdev_write_cfg()

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-24 18:11:02 +08:00
Zide Chen
4741fcfff2 hv: pci_priv.h code cleanup
- move most of the content of pci_priv.h to include/dm/pci.h.
  This allows other code outside dm/vpci to be able to share these macros.
- code cleanup: fix alignments etc.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-24 18:11:02 +08:00
Li, Fei1
cc89e52d5b hv: mmu: make page table operation no fault
Page table operation would not fault except:
1. the hypervisor it out of memory to allcate a page for page table operation
2. there is a bug with page table operation in hypervisor or devicemodle
While we assue that these would not happened in our platform when release, so
there is no need to check whether there is a fault with page table operation. However,
for debug version, we would panic the hypervisor if we can't meet the conditions really.

Tracked-On: #1124
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-10-10 09:36:51 +08:00
Shiqing Gao
74622d7d29 hv: merge hv_lib.h and hypervisor.h
merge hv_lib.h and hypervisor.h into one file

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-27 15:55:41 +08:00
Shiqing Gao
8787c06d3b hv: arch: fix 'Unused procedure parameter'
MISRA-C requires that there should be no unused parameters in
functions.

In some cases, we will keep the unused parameters.
vmexit handler is one example. It is used as function pointer.
Some of the vmexit handlers use the input parameter 'vcpu', some of
them don't. We still need to keep the unused parameters 'vcpu' for
those handlers don't use 'vcpu'.

This patch removes the unused parameters that is not being used
unconditionally.

v1 -> v2:
 * remove the non-implemented API 'vlapic_id_write_handler'

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-26 10:48:55 +08:00
Shiqing Gao
97aeb7f4ff hv: pgtable: fix 'Use of function like macro'
Convert HPA2HVA, HVA2HPA, GPA2HVA and HVA2GPA to inline functions.

v1 -> v2:
 * Modify the following statement.
   rsdp = biosacpi_search_rsdp((char *)hpa2hva((uint64_t)(*addr << 4)),
                                                                0x400);
   Instead of "(uint64_t)(*addr << 4)", "(uint64_t)(*addr) << 4U" would
   be clearer.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-07 11:11:06 +08:00
dongshen
36c4a27abc HV: Fix VPCI bugs found in integration testing for partition mode
Tracked-On: #1126
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2018-09-03 11:26:30 +08:00