Commit Graph

2641 Commits

Author SHA1 Message Date
Sainath Grandhi
8ffe6fc67a hv: Reserve space for VMs' EPT 4k pages after boot
As ACRN prepares to support servers with large amounts of memory
current logic to allocate space for 4K pages of EPT at compile time
will increase the size of .bss section of ACRN binary.

Bootloaders could run into a situation where they cannot
find enough contiguous space to load ACRN binary under 4GB,
which is typically heavily fragmented with E820 types Reserved,
ACPI data, 32-bit PCI hole etc.

This patch does the following
1) Works only for "direct" mode of vboot
2) reserves space for 4K pages of EPT, after boot by parsing
platform E820 table, for all types of VMs.

Size comparison:

w/o patch
Size of DRAM            Size of .bss
48 GB                   0xe1bbc98 (~226 MB)
128 GB                  0x222abc98 (~548 MB)

w/ patch
Size of DRAM            Size of .bss
48 GB                   0x1991c98 (~26 MB)
128 GB                  0x1a81c98 (~28 MB)

Tracked-On: #4563
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 21:13:37 +08:00
Qian Wang
da027ff622 HV: Changed enum to marco to pass MISRA-C check
hv: acpi: changed the enum "acpi_dmar_type" to macros to pass the
MISRA-C check

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
c20228d36f HV: simplified the logic of dmar_wait_completion
hv: vtd: simplified the logic of dmar_wait_completion

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
698ad6bd4d HV: renamed some structs more understandably
hv: pci: renamed some internal data structs to make them more
understandable

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
60704a5d9c HV: renamed some static functions related to dmar
hv: vtd: renamed some static functions from dmar_verb to verb_dmar

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
c2bcf9fade HV: simplified the logic of iommu_read/write64
hv: vtd: simplified the logic of iommu_read/write64

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
a1e081073f HV: Corrected return type of two static functions
hv: vtd: corrected the return type of get_qi_queue and get_ir_table to
void *

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
fc9f089902 HV: remove multi-return in drhd_find_iter
hv: dmar_parse: remove multi-return in drhd_find_iter

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Qian Wang
b55f414a9d HV: Removed unused member variable of iommu_domain and related code
hv: vtd: removed is_host (always false) and is_tt_ept (always true) member
variables of struct iommu_domain and related codes since the values are
always determined.

Tracked-On: #4535
Signed-off-by: Qian Wang <qian1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-04-01 10:43:54 +08:00
Li Fei1
ea2616fbbf hv: vlapic: minor fix about dereference vcpu from vlapic
Since vcpu if remove from vlapic, we could not dereference it directly.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-31 15:59:52 +08:00
Li Fei1
2b7168da9e hv: vmtrr: remove vcpu structure pointer from vmtrr
We could use container_of to get vcpu structure pointer from vmtrr. So vcpu
structure pointer is no need in vmtrr structure.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-31 10:57:47 +08:00
Li Fei1
1946661c51 hv: vpic: remove vm structure pointer from vpic
We could use container_of to get vm structure pointer from vpic. So vm
structure pointer is no need in vpic structure.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-31 10:57:47 +08:00
Li Fei1
0a7770cbb7 hv: vpci: remove vm structure pointer from vpci
We could use container_of to get vm structure pointer from vpci. So vm
structure pointer is no need in vpci structure.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-31 10:57:47 +08:00
Li Fei1
a7768fdb6a hv: vlapic: remove vcpu/vm structure pointer from vlapic
We could use container_of to get vcpu/vm structure pointer from vlapic. So vcpu/vm
structure pointer is no need in vlapic structure.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-31 10:57:47 +08:00
Li Fei1
7f342bf62f hv: list: rename list_entry to container_of
This function casts a member of a structure out to the containing structure.
So rename to container_of is more readable.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-31 10:57:47 +08:00
dongshen
1328dcb205 hv: extend union dmar_ir_entry to support VT-d posted interrupts
Exend union dmar_ir_entry to support VT-d posted interrupts.

Rename some fields of union dmar_ir_entry:
  entry --> value
  sw_bits --> avail

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-31 10:30:30 +08:00
dongshen
016c1a5073 hv: pass pointer to functions
Pass intr_src and dmar_ir_entry irte as pointers to dmar_assign_irte(),
which fixes the "Attempt to change parameter passed by value" MISRA C violation.

A few coding style fixes

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-31 10:30:30 +08:00
dongshen
0f3c876a91 hv: extend struct pi_desc to support VT-d posted interrupts
For CPU side posted interrupts, it only uses bit 0 (ON) of the PI's 64-bit control
, other bits are don't care. This is not the case for VT-d posted
interrupts, define more bit fields for the PI's 64-bit control.
Use bitmap functions to manipulate the bit fields atomically.

Some MISRA-C violation and coding style fixes

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-31 10:30:30 +08:00
dongshen
8f732f2809 hv: move pi_desc related code from vlapic.h/vlapic.c to vmx.h/vmx.c/vcpu.h
The posted interrupt descriptor is more of a vmx/vmcs concept than a vlapic
concept. struct acrn_vcpu_arch stores the vmx/vmcs info, so put struct pi_desc
in struct acrn_vcpu_arch.

Remove the function apicv_get_pir_desc_paddr()

A few coding style/typo fixes

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-31 10:30:30 +08:00
dongshen
b384d04ad1 hv: rename vlapic_pir_desc to pi_desc
Rename struct vlapic_pir_desc to pi_desc
Rename struct member and local variable pir_desc to pid

pir=posted interrupt request, pi=posted interrupt
pid=posted interrupt descriptor
pir is part of pi descriptor, so it is better to use pi instead of pir

struct pi_desc will be moved to vmx.h in subsequent commit.

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-31 10:30:30 +08:00
Zide Chen
1d2aea1ebd hv: some coding refinement in hypercall.c
- since now we don't need to print error messages if copy_to/from_gpa()
  fails, then in many cases we can simplify the function return handling.

  In the following example, my fix could change the 'ret' value from
  the original '-1' to the actual errno returned from copy_to_gpa(). But
  this is valid. Ideally we may replace all '-1' with the actual errno.

  - if (copy_to_gpa() < 0) {
  -	pr_err("error messages");
  -	ret = -1;
  - } else {
  -	ret = 0;
  - }
  + ret = copy_to_gpa();

- in most cases, 'ret' is declared with a default value 0 or -1, then the
  redundant assignment statements can be removed.

- replace white spaces with tabs.

Tracked-On: #3854
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-30 13:19:01 +08:00
Zide Chen
eef3b51eda hv: move error message logging into gpa copy APIs
In this way, the code looks simpler and line of code is reduced.

Tracked-On: #3854
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-30 13:19:01 +08:00
Li Fei1
4512ef7ec9 hv: cpuid: remove cpuid()
The cupid() can be replaced with cupid_subleaf, which is more clear.
Having both APIs makes reading difficult.

Tracked-On: #4526
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-25 13:26:58 +08:00
Sainath Grandhi
6b517c58f1 hv: Server platforms can have more than 8 IO-APICs
To support server platforms with more than 8 IO-APICs

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Sainath Grandhi
fe5a108c7b hv: vioapic init for SOS VM on platforms with multiple IO-APICs
For SOS VM, when the target platform has multiple IO-APICs, there
should be equal number of virtual IO-APICs.

This patch adds support for emulating multiple vIOAPICs per VM.

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Sainath Grandhi
f67ac09141 hv: Handle holes in GSI i.e. Global System Interrupt for multiple IO-APICs
MADT is used to specify the GSI base for each IO-APIC and the number of
interrupt pins per IO-APIC is programmed into Max. Redir. Entry register of
that IO-APIC.

On platforms with multiple IO-APICs, there can be holes in the GSI space.
For example, on a platform with 2 IO-APICs, the following configuration has
a hole (from 24 to 31) in the GSI space.

IO-APIC 1: GSI base - 0, number of pins - 24
IO-APIC 2: GSI base - 32, number of pins - 8

This patch also adjusts the size for variables used to represent the total
number of IO-APICs on the system from uint16_t to uint8_t as the ACPI MADT
uses only 8-bits to indicate the unique IO-APIC IDs.

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Sainath Grandhi
85217e362f hv: Introduce Global System Interrupt (GSI) into INTx Remapping
As ACRN prepares to support platforms with multiple IO-APICs,
GSI is a better way to represent physical and virtual INTx interrupt
source.
1) This patch replaces usage of "pin" with "gsi" whereever applicable
across the modules.
2) PIC pin to gsi is trickier and needs to consider the usage of
"Interrupt Source Override" structure in ACPI for the corresponding VM.

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Sainath Grandhi
2fe3004202 hv: Pass address of vioapic struct to register_mmio_emulation_handler
Changes the mmio handler data from that of the acrn_vm struct to
the acrn_vioapic.

Add nr_pins and base_addr to the acrn_vioapic data structure.

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Sainath Grandhi
dd6c80c305 hv: Move error checking for hypercall parameters out of assign module
Moving checks on validity of IOAPIC interrupt remapping hypercall parameters
to hypercall module

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Sainath Grandhi
06b59e0bc1 hv: Use ptirq_lookup_entry_by_sid to lookup virtual source id in IOAPIC irq entries
Reverts 538ba08c: hv:Add vpin to ptdev entry mapping for vpic/vioapic

ACRN uses an array of size  per VM to store ptirq entries against the vIOAPIC pin
and an array of size per VM to store ptirq entries against the vPIC pin.
This is done to speed up "ptirq entry" lookup at runtime for Level triggered
interrupts in API ptirq_intx_ack used on EOI.

This patch switches the lookup API for INTx interrupts to the API,
ptirq_lookup_entry_by_sid

This could add delay to processing EOI for Level triggered interrupts.
Trade-off here is space saved for array/s of size CONFIG_MAX_IOAPIC_LINES with 8 bytes
per data. On a server platform, ACRN needs to emulate multiple vIOAPICs for
SOS VM, same as the number of physical IO-APICs. Thereby ACRN would need around
10 such arrays per VM.

Removes the need of "pic_pin" except for the APIs facing the hypercalls
hcall_set_ptdev_intr_info, hcall_reset_ptdev_intr_info

Tracked-On: #4151
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-25 09:36:18 +08:00
Victor Sun
52f26cba8a hv: a few fixes for multiboot2 boot
- need to specify the load_addr in the multiboot2 address tag. GRUB needs
  it to correctly calculate the ACRN binary's load size if load_end_addr is
  a non-zero value.

- multiboot2 can be enabled if hypervisor relocation is disabled.

- print the name of the boot loader. This might be helpful if the boot
  loader, e.g. GRUB, inludes its version in the name string.

Tracked-On: #4441
Signed-off-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2020-03-24 08:44:20 +08:00
Li Fei1
e99ddf28c3 hv: vpci: handle the quirk part for pass through pci device cfg access in dm
There're some PCI devices need special handler for vendor-specical feature or
capability CFG access. The Intel GPU is one of them. In order to keep the ACRN-HV
clean, we want to throw the qurik part of PCI CFG asccess to DM to handle.

To achieve this, we implement per-device policy base on whether it needs quirk handler
for a VM: each device could configure as "quirk pass through device" or not. For a
"quirk pass through device", we will handle the general part in HV and the quirk part
in DM. For a non "quirk pass through device",  we will handle all the part in HV.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-20 10:08:43 +08:00
Li Fei1
e5c7a96513 hv: vpci: sos could access low severity guest pci cfg space
There're some cases the SOS (higher severity guest) needs to access the
post-launched VM (lower severity guest) PCI CFG space:
1. The SR-IOV PF needs to reset the VF
2. Some pass through device still need DM to handle some quirk.
In the case a device is assigned to a UOS and is not in a zombie state, the SOS
is able to access, if and only if the SOS has higher severity than the UOS.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-20 10:08:43 +08:00
Yuan Liu
9375c634dc hv: unmap SR-IOV VF MMIO when the VF physical device is disabled
To avoid information leakage, we need to ensure that the device is
inaccessble when it does not exist.

For SR-IOV disabled VF device, we have the following operations.
    1. The configuration space accessing will get 0xFFFFFFFF as a
       return value after set the device state to zombie.
    2. The BAR MMIO EPT mapping are removed, the accesssing causes
       EPT violation.
    3. The device will be detached from IOMMU.
    4. The IRQ pin and vector are released.

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-18 21:46:54 +08:00
Mingqiang Chi
14692ef60c hv:Rename two VM states
Rename:
  VM_STARTED --> VM_RUNNING
  VM_POWERING_OFF --> VM_READY_TO_POWEROFF

Tracked-On: #4320
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-13 10:34:29 +08:00
Victor Sun
a8c2ba03fc HV: add pci_devices.h for nuc6cayh and apl-up2
As pci_devices.h is included by <page.h>, need to prepare pci_devices.h
for nuc6cayh and apl-up2 board.

Also the #error info in generic/pci_devices.h should be removed, otherwise
the build will be failed in sdc/sdc2/industry scenarios.

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
2020-03-12 14:56:34 +08:00
Victor Sun
a68f655a11 HV: update ept address range for pre-launched VM
For a pre-launched VM, a region from PTDEV_HI_MMIO_START is used to store
64bit vBARs of PT devices which address is high than 4G. The region should
be located after all user memory space and be coverd by guest EPT address.

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 14:56:34 +08:00
Victor Sun
e74553492a HV: move create_sos_vm_e820 to ve820.c
ve820.c is a common file in arch/x86/guest/ now, so move function of
create_sos_vm_e820() to this file to make code structure clear;

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 14:56:34 +08:00
Victor Sun
a7b61d2511 HV: remove board specific ve820
Remove useless per board ve820.c as arch/x86/guest/ve820.c is common for
all boards now;

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 14:56:34 +08:00
Victor Sun
d7eac3fe6a HV: decouple prelaunch VM ve820 from board configs
hypervisor/arch/x86/configs/$(BOARD)/ve820.c is used to store pre-launched
VM specific e820 entries according to memory configuration of customer.
It should be a scenario based configurations but we had to put it in per
board foler because of different board memory settings. This brings concerns
to customer on configuration orgnization.

Currently the file provides same e820 layout for all pre-launched VMs, but
they should have different e820 when their memory are configured differently.
Although we have acrn-config tool to generate ve802.c automatically, it
is not friendly to modify hardcoded ve820 layout manually, so the patch
changes the entries initialization method by calculating each entry item
in C code.

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 14:56:34 +08:00
Victor Sun
4c0965d89e HV: correct ept page array usage
Currently ept_pages_info[] is initialized with first element only that force
VM of id 0 using SOS EPT pages. This is incorrect for logical partition and
hybrid scenario. Considering SOS_RAM_SIZE and UOS_RAM_SIZE are configured
separately, we should use different ept pages accordingly.

So, the PRE_VM_NUM/SOS_VM_NUM and MAX_POST_VM_NUM macros are introduced to
resolve this issue. The macros would be generated by acrn-config tool when
user configure ACRN for their specific scenario.

One more thing, that when UOS_RAM_SIZE is less then 2GB, the EPT address
range should be (4G + PLATFORM_HI_MMIO_SIZE).

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 14:56:34 +08:00
Yuan Liu
e9a99845f6 hv: refine read/write configuration APIs for vmsi/vmsix
change vmsi_read_cfg to read_vmsi_cfg, same applies to writing
change vmsix_read_cfg to read_vmsix_cfg, same applies to writing

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 10:40:02 +08:00
Li Fei1
4b6dd19ad1 hv: pci: rename CFG read/write function for PCI-compatible Configuration Mechanism
Move CFG read/write function for PCI-compatible Configuration Mechanism from
debug/uartuart16550.c to hw/pci.c and rename CFG read/write function for
PCI-compatible Configuration Mechanism to pci_pio_read/write_cfg to align with
CFG read/write function pci_mmcfg_read/write_cfg for PCI Express Enhanced
Configuration Access Mechanism.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-12 09:17:02 +08:00
Mingqiang Chi
790614e952 hv:rename several variables and api for ioapic
rename:
  ioapic_get_gsi_irq_addr --> gsi_to_ioapic_base
  ioapic_addr -->ioapic_base

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2020-03-11 13:26:15 +08:00
Li Fei1
fa74bf401d hv: vpci: pass through stolen memory and opregion memory for GVT-D
In order to add GVT-D support, we need pass through stolen memory and opregion memroy
to the post-launched VM. To implement this, we first reserve the GPA for stolen memory
and opregion memory through post-launched VM e820 table. Then we would build EPT mapping
between the GPA and the stolen memory and opregion memory real HPA. The last, we need to
return the GPA to post-launched VM if it wants to read the stolen memory and opregion
memory address and prevent post-launched VM to write the stolen memory and opregion memory
address register for now.
We do the GPA reserve and GPA to HPA EPT mapping in ACRN-DM and the stolen memory and
opregion memory CFG space register access emulation in ACRN-HV.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-11 10:59:23 +08:00
Zide Chen
659e5420df hv: add static check for CONFIG_HV_RAM_START and CONFIG_HV_RAM_SIZE
Hypervisor uses 2MB large page, and if either CONFIG_HV_RAM_START or
CONFIG_HV_RAM_SIZE is not aligned to 2MB, ACRN won't boot. Add static check
to avoid unexpected boot failures.

If CONFIG_RELOC is enabled, CONFIG_HV_RAM_START is not directly referred
by the code, but it causes problems because ld_text_end could be relocated
to an address that is not 2MB aligned which fails mmu_modify_or_del().

Tracked-On: #4441
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-03-11 10:37:50 +08:00
Yuan Liu
696f6c7ba4 hv: the VM can only deinit its own devices
VM needs to check if it owns this device before deiniting it.

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-11 08:35:30 +08:00
Yuan Liu
d8a19f9978 hv: refine naming
Change enable_vf/disable_vf to create_vfs/disable_vfs
Change base member of pci_vbar to base_gpa

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-11 08:35:30 +08:00
Yuan Liu
08ed45f4b4 hv: fix wrong VF BDF
The vf_bdf is not initialized when invoking pci_pdev_read_cfg function.

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-11 08:35:30 +08:00
Yuan Liu
7b429fe483 hv: prohibit PF from being assigned
We didn't support SR-IOV capability of PF in UOS for now, we should
hide the SR-IOV capability if we pass through the PF to a UOS.

For now, we don't support assignment of PF to a UOS.

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2020-03-11 08:35:30 +08:00