add BSP and AP initialization function.
and call uart16550_init to update uart_base_address
after init paging.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
this patch calculate riscv static pages number for page pool.
riscv donot need to map guest memory. use link script address
label to map code size.
For risc-v:
1) if the platform doesn't support PCIe devices
The address space layout for risc-v is like
| |
| MMIO |
| |
| ... |
| |
| RAM |
| |
For all its address space, one 1GB page table is enough which cover 512G
For MMIO or RAM, if its start address and end address is 1G aligned, there's no 2M
or 4K page table is needed. if their address are not 1G aligned, two 2M page table
is enough for MMIO or RAM. The issue here is that if we neetid 4K page entries for
different page attributes. So we need to reserve enough 4K page tables for that requirement.
2) if the platform support PCI devices, for the low MMIO range, another two 2MB page
table may needed. for the high MMIO range, its depends on the max physical address bits of
the platform and the high MMIO range reserved by the BIOS.
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Add hypervisor pagetable manipulate interface to riscv arch directory,
which is needed by the common interface, and add riscv ppt pgtable
structure implementation.
Tracked-On: #8831
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: hangliu1 <hang1.liu@intel.com>
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
move some funcitons like hpa2hva to common file.
change some files to include file from asm/pgtable.h to common/pgtable.h
Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The RISC-V calling convention defines a full descending stack, where 'sp'
points to the last used stack address. The current implementation of
cpu_ctx_save() subtracts only CPU_REGS_OFFSET_SCRATCH from 'sp', which
allocates 8 bytes too few and may overwrite the caller's stack contents.
Fix this by adjusting CPU_REGS_OFFSET_LAST to include the last slot,
ensuring the full context save/restore area is properly reserved.
Fixes: 6276763cd (hv: riscv: implement cpu_ctx_save and cpu_ctx_restore)
Tracked-On: #8827
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Use tp register directly for arch_get_pcpu_id. This can eliminate the
unnecessary mv instruction.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
implement arch_cpu_dead and arch_cpu_do_idle for riscv, arch_cpu_dead and
arch_cpu_do_idle will be called by common module.
Tracked-On: #8812
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Signed-off-by: Xue Bosheng <bosheng.xue@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Convert IRQ-related macros to static inline functions and introduce
wrappers for arch-specific implementations. This follows the style we
defined for multi-arch development.
This is a follow-up update for commit
a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h").
CPU_IRQ_ENABLE_ON_CONFIG -> local_irq_enable
CPU_IRQ_DISABLE_ON_CONFIG -> local_irq_disable
CPU_INT_ALL_DISABLE -> local_irq_save
CPU_INT_ALL_RESTORE -> local_irq_restore
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Fix a compilation error that may occur in some environments due to an
inconsistent type cast. The compiler reports a strict-aliasing violation:
acrn-hypervisor/hypervisor/include/arch/riscv/asm/cpu.h:73:18:
error: dereferencing type-punned pointer will break strict-aliasing rules
[-Werror=strict-aliasing]
73 | *(uint32_t *)(x) = val;
| ^~~~~
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
local_irq_save() is intended to read and clear the SIE bit in
sstatus (disabling interrupts). The current implementation mistakenly
clears all bits in sstatus.
This patch corrects the inline assembly so that only the SIE bit is affected,
ensuring proper interrupt save/disable semantics on RISC-V.
Fixes: a7239d126 ("[FIXME] hv: risc-v add denpended implementation in cpu.h")
Tracked-On: #8813
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements interrupt initialization and the basic
exception/interrupt handling flow on RISC-V.
init_interrupt() needs to be invoked during CPU initialization to
set up the trap vector and enable the interrupt.
RISC-V exception and interrupt handling includes:
- Saving and restoring CPU registers around traps
- Implementing handlers for:
- Supervisor software interrupt
- Supervisor timer interrupt
- Halting the CPU for all other interrupts and exceptions
------
TODOs:
1. add support for registering interrupt handlers via request_irq() and
further adoption of the common IRQ framework.
2. add support for external interrupt.
Tracked-On: #8813
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Enable acrnlog (memory logging) in release builds, default log level
is still controlled by DEBUG_OPTIONS/MEM_LOGLEVEL in scenario file.
Tracked-On: #8805
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
This patch adds the basic logics to bring up all APs in the C
entry of BSP boot. The mapping between logcial CPU IDs and physical
hart IDs is setup based on the pre-generated data from config tool
by parsing the device tree. Logical CPU ID BSP_CPU_ID will always
map to the BSP hart ID. The per pCPU logic ID is saved in tp register.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Extension Zihintpause (Pause hint) is mandatory for RVA23. asm_pause
is implemented based on "pause" instruction.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Use tp register to hold the current logical CPU ID. This follows the
same design as x86 which uses MSR_IA32_SYSENTER_CS for the same purpose.
riscv uses SBI HSM to start the APs.
Tracked-On: #8791
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
spinlock invokes CPU_INT_ALL_DISABLE & CPU_INT_ALL_RESTOE, bitops
invokes BITS_PER_LONG, add them to pass the build.
current implementation is macro, same as X86. later official mult-arch
change should refactor to static inline on both x86 and risc-v.
Tracked-On: #8803
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Move phys_cpu_num and pcpu_active_bitmap to common, which could be
only accessed by interfaces provided by smp.h.
v2->v3:
1. move ALL_CPUS_MASK/AP_MASK to common cpu.h
v1->v2:
1. preserve phys_cpu_num in x86 but implement arch_get_num_available_cpus()
to provide interface for common code to access.
2. change function name test_xx to check_xx
Tracked-On: #8801
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Move x86 architecture dependent per cpu data into a
seperate structure and embeded it in per_cpu_region.
caller could access architecture dependent member by
using prefix 'arch.'.
v2->v3:
move whose_iwkey, profiling_info and tsc_suspend to x86
v1->v2:
rebased on latest repo
Tracked-On: #8801
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Reviewed-by: Chen, Jian Jun<jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since there is no common IPI abstraction, the arch_ prefix is redundant.
This patch renames the functions as follows:
- arch_send_dest_ipi_mask -> send_dest_ipi_mask
- arch_send_single_ipi -> send_single_ipi
Tracked-On: #8799
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
This patch implements risc-v specific timer codes. Basically,
risc-v adapts to acrn timer framework with some specific
behaviors. So far, it enables sstc support in h-mode.
Tracked-On: #8792
Signed-off-by: Haicheng Li <haicheng.li@outlook.com>
Co-developed-by: Yong Li <yong.li@intel.com>
Signed-off-by: Yong Li <yong.li@intel.com>
Co-developed-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch provides dummy implementations of functions and data
structures required for the IPI and SMP call on RISC-V.
It serves as a placeholder to ensure RISC-V builds pass and
is not needed for the final merge.
Official implementations are still WIP by other engineers:
- To be provided in the library patchset (by Haoyu):
uint16_t ffs64(uint64_t value);
bool bitmap_test(uint16_t nr, const volatile uint64_t *addr);
void bitmap_clear_lock(uint16_t nr_arg, volatile uint64_t *addr);
void bitmap_clear_nolock(uint16_t nr_arg, volatile uint64_t *addr);
uint64_t atomic_cmpxchg64(volatile uint64_t *ptr, uint64_t old, uint64_t new);
- To be provided in the platform initialization patchset (by Hang):
void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
bool is_pcpu_active(uint16_t pcpu_id);
uint16_t get_pcpu_id(void);
----------
Changelog:
* Split per_cpu.h implementation into a separate commit.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since smpcall depends on the per_cpu_region data structure to access
smp_call_info_data, this patch adds the initial version of per_cpu
support on RISC-V. For now it only includes SMP call related info.
Further refinement will be done in the platform initialization patchset
(by Hang).
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the IPI for RISC-V using SBI interface.
There is no common IPI concept abstracted, due to the following reasons:
- RISC-V:
Software delivers an IPI to target CPUs via software interrupts.
The interrupt number is fixed for each privilege mode (e.g.,
Supervisor Software Interrupt = IRQ 1, Machine Software Interrupt = IRQ 3).
The actual purpose of the IPI is indicated by an IPI message type,
which is a software-level concept. When the IPI is received,
the target CPU must check the message type to determine the required action.
- x86:
Software delivers an IPI to target CPUs using a specific vector number.
During CPU initialization, software can assign dedicated vectors for
particular purposes. When the IPI is received, the target CPU could
directly invoke the handler bound to that vector.
Each architecture provides its own IPI implementation, and other SW modules
directly call these arch-specific functions.
------
Notes:
* To ensure RISC-V builds pass, an empty `include/arch/riscv/asm/cpu.h`
is added since `debug/logmsg.h` includes `asm/cpu.h`.
* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
Legacy SBI extensions are not supported in ACRN.
----------
Changelog:
* Updated commit message and code comments to state explicitly that
legacy SBI extensions are not supported in ACRN.
* Refined the prototype of sbi_send_ipi() to align with the SBI spec:
From: int64_t sbi_send_ipi(uint64_t mask)
To: int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
In ACRN it is invoked as sbi_send_ipi(dest_mask, 0UL), with mask_base
set to 0UL.
* Renamed send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() respectively.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the common SBI interfaces, including
sbi_ecall(), common macros and data structures.
Changelog:
* Renamed SBI_EXPERIMENTAL_x and SBI_VENDOR_x.
* Added description for sbi_ecall().
* Renamed SBI-related enums, macros, and data structures to align with
the SBI specification.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
