Commit Graph

488 Commits

Author SHA1 Message Date
Yonghua Huang
2af08d9619 HV: refine 'struct lapic_regs' definition.
- remove 'PAD3' & 'PAD4'
 - define local APIC registers by 'struct lapic_reg' type.

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 09:09:44 +08:00
Qi Yadong
8858634493 HV: update opcode when decode_two_byte_opcode()
The vie->opcode should be updated when decode_two_byte_opcode(),
otherwise for two bytes opcode emulate(movzx/movsx) will fail.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-09-14 09:26:48 +08:00
Junjun Shan
4fd5102edc hv:treewide:fix multiple MISRAC violations
MISRAC has requirements about literal value requires a U suffix and
signed/unsigned conversion with cast. This patch is used to solve
these violations.

v1->v2
 *Drop the cast of sz from uint32_t to int32_t, the signed/unsigned
  violation of nchars will be solved by other patch together with
  printf/sprintf/console/vuart/uart code.

 *Delete the unnecessary L suffix of shifting operand.

Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Reviewed by: Junjie Mao <junjie.mao@intel.com>
2018-09-13 11:12:29 +08:00
Yin Fengwei
44a2d77c32 hv: add SMAP/SMEP check during guest page walking
According to SDM 4.6 Access Rights definition, if SMAP/SMEP
is enabled, more conditions are used to decide the access rights
like SMAP/SMEP, EFLAGS.AC, R/W bit in every paging-structure entry
for page walking.

This patch add the check to guest page walking function and inject
page fault accordingly.

Tracked-On: #1207
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-13 09:21:59 +08:00
Yin Fengwei
d958d31e1b hv: fix the issue of movs emulation
The current movs emulation has issues:
1. it use gva to get/put data.
2. it only support src and dst operand are memory which does not
   apply to our case (one of them should be mmio and triggers
   EPT voilation).

This patch fix the issue by:
1. convert the address from gva to hva before access it.
2. handle mmio emulation.

Also fix the issue introduced by previous instruction reshuffle
patchset:
1. the desc validation should be only applied to none-64bit mode.
2. gva2gpa should be given correct guest virtual address.

Specailly for movs, we cache the dst gpa if the check during
movs decoding success. And use it directly during movs
emulation.

Tracked-On: #1207
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Tested-by: Qi Yadong <yadog.qi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-13 09:21:59 +08:00
Mingqiang Chi
60c05ace1a hv:Replace vlapic pointer with instance in vcpu_arch
-- update 'vlapic' in 'struct vcpu_arch' from pointer
   to instance
-- add inline function(vcpu_vlapic) in vcpu.h

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
aae5018bec hv:Move vlapic structure to vlapic.h
move structure vlapic_pir_desc/vlapic_timer/
acrn_vlapic from vlapic_priv.h to vlapic.h

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
fdb64095c4 hv:Replace dynamic memory allocation for apic access address
Replace pointer with static memory for apicv_apic_access_addr

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
887ebf0b08 hv: Replace dynamic memory allocation for MSR bitmap
Replace pointer with static memory for msr_bitmap
inside structure vm_arch.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
02e7edc063 hv: Replace dynamic memory allocation for I/O bitmaps
-- Replace pointer with static memory for io_bitmap
  inside structure vm_arch.
-- Refine allow_guest_pio_access/deny_guest_pio_access

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
eada04b800 hv:Replace dynamic memory allocation for vmcs region
Replace vmcs pointer with static memory for vmcs region
inside structure vcpu_arch.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Shiqing Gao
bcaede0c0e hv: treewide: fix 'Use of function like macro'
- convert function like macros to inline functions based on MISRA-C
  requirement
- remove some unused and duplicated macros

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-11 10:49:48 +08:00
Jason Chen CJ
8773dfb1f6 vlapic: unmap vlapic base only for SOS
as SOS mapped all memory at the beginning, so trap vlapic need unmap its
memory; for UOS, there is no need as UOS never mapped it.

Tracked-On: #1124
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Jason Chen CJ
457ac7408d vcpu: replace start_vcpu with run_vcpu
run_vcpu should be a more suitable name

Tracked-On: #1199
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Minggui Cao
99285f844a HV: improve pass-thru device interrupt process
for each pass-thru device and its entry owned by one VM, so
change the pass-thru device's softirq lock & entry list into
per VM, so one VM's PT device interrupt process will not
interfere with other VMs; especially in case one user OS
"interrupt storm" happens, it will have little effect on
service OS.

Tracked-On: #866
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-10 10:12:45 +08:00
Shiqing Gao
97aeb7f4ff hv: pgtable: fix 'Use of function like macro'
Convert HPA2HVA, HVA2HPA, GPA2HVA and HVA2GPA to inline functions.

v1 -> v2:
 * Modify the following statement.
   rsdp = biosacpi_search_rsdp((char *)hpa2hva((uint64_t)(*addr << 4)),
                                                                0x400);
   Instead of "(uint64_t)(*addr << 4)", "(uint64_t)(*addr) << 4U" would
   be clearer.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-07 11:11:06 +08:00
Shiqing Gao
f2f719cfa8 hv: fix 'Procedure is not called or referenced in code analysed'
MISRA-C requires that each function defined and declared shall be called
or referenced in code analyzed.

In some cases, we would like to keep the non-called functions for code
completeness, such as
vcpu_inject_extint/vcpu_inject_nmi/vcpu_inject_gp/vcpu_inject_pf
/vcpu_inject_ud/vcpu_inject_ac/vcpu_inject_ss.

This pacth removes some functions that are independent and are not
called in our code base.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-06 12:01:30 +08:00
Shiqing Gao
67038794af hv: treewide: convert some MACROs to inline functions
MISRA-C requires that each parameter in the MACRO shall be in brackets.

In some cases, adding brackets for all of the parameters may not be a
perfect solution.
For example, it may affect the code readability when there are many
parameters used in the MACRO.
And duplicated brackets will appear when one MACRO called another MACRO
which is using same parameters.

This patch convert some MACROs to inline functions to avoid such cases.

v1 -> v2:
 * Remove the unnecessary changes in hypervisor/bsp/uefi/efi/boot.h

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-04 12:27:18 +08:00
Shiqing Gao
54439ecae1 hv: treewide: fix 'Expression is not Boolean'
MISRA-C requires that the controlling expression of an if statement or
an iteration-statement shall be Boolean type.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-03 11:23:53 +08:00
Kaige Fu
f611012d28 HV: Refine two log info about vcpu and instr_emul
We have two same log message in decode_instruction. It's a little bit confusing.
So, this patch refine the log message to make it more explicit.

BTW, we refine one message in create_vcpu.

Tracked-On: #1136

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 11:23:15 +08:00
Shiqing Gao
96dba0d8fe hv: fix MISRA-C issues related to space or newline
This patch fixes the following issues:
- No newline after semi colon.
- No space after semi colon in for expression.
- No space between if, while, for and expresn.

v1 -> v2:
 * Fix the typo for the for loop change.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-09-03 09:35:15 +08:00
Li, Fei1
9257ecf4bb hv: mmu: cleanup mmu.h
Remove unused Macro defininion.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Sainath Grandhi
c102c44c16 hv: Device MSIs in partition mode ACRN
VMs in partition mode uses a kernel patch to switch to physical mode xAPIC.
The kernel patch together with this patch makes sure device MSIs use
physical mode as DM and physical APIC IDs in Destination field.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-09-03 09:32:15 +08:00
Shiqing Gao
10c64a5fca hv: fix MISRA-C issues related to for loop
This patch fixes the following issues:
- Assignment operation in expression.
- For loop incrementation is not simple.
- No brackets to loop body.
- Use of comma operator.

v1 -> v2:
 * Replace &x->y with &(x->y) based on our new coding rule

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-31 09:20:48 +08:00
Shiqing Gao
2a184f353c hv: code clean up regarding to guest_msrs
Change guest_msrs in vcpu data structure from pointer to array, which
could avoid the dynamic memory allocation.

v1 -> v2:
 * Remove the unnecessary initialization for guest_msrs[] since vcpu is
   allocated by calloc.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-28 11:08:48 +08:00
Mingqiang Chi
4e8798e018 hv:Replace vioapic pointer with instance in structure vm
-- rename struct vioapic --> struct acrn_vioapic
-- update 'vioapic' field in 'struct arch_vm' from pointer
   to instance
-- change vm_ioapic(vm) to inline, and move it to vm.h
-- change vioapic_init to void type

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Mingqiang Chi
29dbd1084d hv:Replace vuart pointer with instance in structure vm
-- update 'vuart' field in 'struct vm' from pointer
   to instance
-- replace MACRO with inline function for vm_vuart,
   and move it to vm.h
-- change vuart_init to void type
-- rename struct vuart -->struct acrn_vuart

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Mingqiang Chi
0b54946bac hv:Replace vpic pointer with instance in structure vm
-- update 'vpic' field in 'struct vm' from pointer
  to instance, and move it from 'struct vm' to 'struct arch_vm'
-- replace MACRO with inline function for vm_pic, and move it
   to vm.h
-- changed vpic_init to void type
-- removed vpic_cleanup
-- move struct acrn_vpic/i8259_reg_state from vpic.c to vpic.h

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Sainath Grandhi
925503ce36 hv: Build fix - ACRN partition mode
Patch to fix compile issue.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-24 11:17:33 +08:00
Yonghua Huang
7bc1a3f925 HV: Refine APICv capabilities detection
- by default, ACRN will not support platform without
   below APICv features:
    -- Use TPR shadow
    -- APIC-register virtualization

 - remove mmio emualtion of local APIC for guest

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-24 09:58:58 +08:00
Binbin Wu
f95d07dc43 hv: vtd: use EPT as translation table for PTDev in SOS
In current code, the address translation type for passthrough devices
in SOS is passthrough type, which means the device in SOS can access
the whole physcial memory.
This patch uses SOS EPT to translate address for passthrough
devices. So that the memory of VMM or trusty can be protected from
SOS PTDev.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:46:57 +08:00
Yin Fengwei
4579e57e7b hv: add gva check for the case gva is from instruction decode
For the instructions other than MOVS, one operand is register
and another one is memory which trigger EPT voilation. In this
case, there is one possibility that EPT voilation happens before
guest fault:
    the fault is triggered by related guest PTE access bit
    voilation (like write to a gva with R/W bit cleared in PTE).

So we do this kind of check and inject exception to guest
accordingly during instruction decoding phase.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
7dde0dfa4b hv: add GVA validation for MOVS
Unlike the other instructions we emulated, MOVS has two operands
both are memory.

So we need to check whether the operand is valid GVA. With VMX
enabled, the src operand is always checked first by VMX. Which
means if src operand is not valid GVA, it will trigger fault
in guest before trigger EPT. So we don't need to check src
operand. Only need to check dst operand here.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
b01a81279a hv: add new function to get gva for MOVS/STO instruction
Drop the get_gla function and add
 - get_gva_di_si_nocheck
   get gva from ES:DI and DS(other segment):SI without
   check faulure case
 - get_gva_di_si_check
   get gva from ES:DI and DS(other segment):SI with failure
   case checked

TODO:
  - Save dst_gpa and src_gpa for instruction emulation phase
    use.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
8480c98053 hv: move check out of vie_calculate_gla
We will do check only during instruction decode phase.
vie_calculate_gla will be called both in instruction emulation
phase, we move the check out of vie_calculate_gla.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
54c254169d hv: remove unnecessary check for gva
According to SDM vol3 25.1.1
With VMX enabled, following exception will be handled by guest
without trigger VM exit:
 - faults based on privilege level
 - general protection due to relevent segment being unusable
 - general protection due to offset beyond limit of relevent segment
 - alignment check exception

ACRN always assume VMX is enabled. So we don't need to these check
in instruction emulation. But we need to do page fault related check.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
5663dd7d14 hv: extend the decode_modrm
If rm show there is no SIB following rm field, we should get
base_register info from rm.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yonghua Huang
3b6ccf0c91 HV: remove callbacks registration for APICv functions
- call these functions directly, no need to register
     callbacks.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:11:21 +08:00
Li, Fei1
4bb8456de8 hv: ept: refine ept_mr_add base on mmu_add
Refine ept_mr_add base on mmu_add. The old map_mem could be removed
once this was done.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-08-23 11:10:26 +08:00
Zhi Jin
dcae438306 hv: add a hypercall for the hypervisor NPK log
The hypercall HC_SETUP_HV_NPK_LOG is added to enable/disable/configure
the hypervisor NPK log.

Signed-off-by: Zhi Jin <zhi.jin@intel.com>
Signed-off-by: Zhonghua Sun <zhonghua.sun@intel.com>
Reviewed-by: CHEN Gang <gang.c.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:09:25 +08:00
Yu Wang
a6c2065b2e hv: apicv: change the name of vapic to apicv
Remove the vapic name and unify to apicv.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Yu Wang
a0c625b85a hv: apicv: change the apicv related API with vlapic_apicv prefix
The apicv is one hardware acceleration feature of vlapic. All vlapic
APIs should keep vlapic_ as the prefix.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Yu Wang
74ff712085 hv: vlapic: local APIC ID related code cleaning up
From SDM Vol3 10.4.6:
Some processors permit software to modify the APIC ID. However, the
ability of software to modify the APIC ID is processor model specific.
Because of this, operating system software should avoid writing to the
local APIC ID register.

So to permit change APIC ID is not one *must* feature. Keep it simple,
we are also reject to modify it.

This patch does code cleaning up for LAPIC ID related emulation.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 08:55:30 +08:00
Mingqiang Chi
c43d0e4f01 hv:Changed several APIs to void type
Since these APIs always return 0,
change them to void type,
vcpu_set_cr0()
vmx_write_cr0()
vcpu_set_cr4()
vmx_write_cr4()
kick_notification()
tsc_deadline_handler()
dmar_fault_handler()
ptdev_interrupt_handler()

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-23 08:54:54 +08:00
Shiqing Gao
42aaf5d46f hv: code clean up regarding to % and / operations
- Clean up some code regarding to % and / operations since bit
  operations are faster.
        x % 64U ---> x & 0x3fU
        x % 32U ---> x & 0x1fU
        x % 16U ---> x & 0xfU
        x % 8U  ---> x & 0x7U
        x % 4U  ---> x & 0x3U
        x % 2U  ---> x & 0x1U

        x / 64U ---> x >> 6U
        x / 32U ---> x >> 5U
        x / 16U ---> x >> 4U
        x / 8U  ---> x >> 3U
        x / 4U  ---> x >> 2U
        x / 2U  ---> x >> 1U
- Minor changes regarding to coding styles

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-22 15:37:53 +08:00
Yonghua Huang
e0d40feaa8 HV:refine 'apic_page' & 'pir_desc' in 'struct acrn_vlapic'
- update 'apic_page' field in 'struct acrn_vlapic',
   from pointer type to 'struct lapic_regs' type.

 - delete 'pir' and update 'pir_desc' to 'vlapic_pir_desc'
   type.

 - fix potential memory leak in 'vlapic_create()'
   should free allocated memory in case of registering
   mmio handler failure.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-08-22 12:52:07 +08:00
Shiqing Gao
8924f6dabb hv: vmx: fix 'Array has no bounds specified'
MISRAC requires that the array size should be declared explicitly.

This patch fixes the issues caused by vm0_boot_context.

Fix pattern is like below:
   extern char start_of_ROM, end_of_ROM, start_of_FLASH;
   memcpy (& start_of_FLASH, & start_of_ROM, & end_of_ROM - &
start_of_ROM);

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-08-21 13:03:28 +08:00
Shiqing Gao
7a4dcfcc1a hv: treewide: fix 'Function prototype/defn param type mismatch'
Fix the parameter type mismatch between API declaration and definition.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-21 09:55:12 +08:00
Mingqiang Chi
40fd8893b4 hv:fixed several return value violations
-- change two timer callbacks to void type
-- ignore the return value for add_timer
-- add (void) before several functions(memset/memcpy/
   vcpu_get_xxx)

v1-->v2:
   ignore the return value for add_timer
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-20 09:51:07 +08:00
Mingqiang Chi
bdcc3aef22 hv: fixed compiling warning
removed some unnecessary variables and functions.

v1-->v2:
   Replace div-by-zero with an inline ASM code

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 12:36:53 +08:00
Sainath Grandhi
150b389120 hv: fix size issue in mptable guest copy - ACRN partition mode
1)Fix to take into account the size of proc entries in MPtable.
2)Change APIC ids to virtual APIC IDs

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-17 10:06:38 +08:00
Arindam Roy
d3db5a6705 HV: Add const qualifiers where required
V1:
In order to better comply with MISRA C,
add const qualifiers whereeven required.
In the patch, these are being added to pointers
which are normally used in "get" functions.

V2: Corrected the issues in the patch
pointed by Junjie in his review comments.
Moved the const qualifiers to the correct
places. Removed some changes which are not
needed.

V3: Updated patch comment.
This modifies a subset of all the functions
which might need constant qualifiers
for the their parameters.
This is not and exhaustive patch. This only
targets obvious places where we can use
the const qualifier. More changes will be
submitted in future patches, if required.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-08-17 10:02:12 +08:00
Yu Wang
e280d9569a hv: vmx_vapic: fix two build warnings
vlapic_vmx_vapic_set_tmr is nobody use now, remove it first to avoid
build warning.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 08:57:31 +08:00
Yu Wang
39b4fecab9 hv: apicv: explicit log for SMI IPI unsupported
ACRN currently do not support SMM and SMI. Print one explicit warning
for it.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 08:57:31 +08:00
Yu Wang
604b5a454b hv: apicv: remove APIC_OFFSET_SELF_IPI(0x3F0) register
From SDM Vol3 Table 10-1 Local APIC Register Address Map. The 0x3F0 is
reserved.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 08:57:31 +08:00
Yu Wang
93f91268c9 hv: apicv: remove x2apic related code
Currently, ACRN hasn't expose x2apic capability through cpuid.
And x2apic related code in vlapic.c has no real functionality. This
patch clear related code.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-17 08:57:31 +08:00
Sainath Grandhi
5b8c7a5b23 hv: VM BSP vcpu mode for ACRN partition mode
BSPs for VMs booted in ACRN partition mode start in protected mode.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-16 16:27:07 +08:00
Sainath Grandhi
022ef92b62 hv: Add vrtc emulation support for ACRN partition mode
This patch adds code to support read-only RTC support for guests
run by partition mode ACRN. It supports RW for CMOS address port 0x70
and RO for CMOS data port 0x71. Reads to CMOS RAM offsets are fetched
by reading CMOS h/w directly and writes to CMOS offsets are discarded.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-16 16:23:11 +08:00
Jason Chen CJ
f2a3e1fb76 quick fix: fix build failure for release version
conflicting types for ‘vcpu_dumpreg’

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-08-15 13:47:01 +08:00
Jason Chen CJ
f8f49d410f dump vcpu registers on correct vcpu
after updated cpu context get/set method, the vcpu_dumreg cmd is not
correct anymore as the registers may read from VMCS but meantime hv
shell may not be running on target vcpu.

this patch take use of smp_call_function for vcpu dumpreg and make the
dump always come from correct vcpu.

v2:
- use str pointer to get vcpu_dumpreg context instead of print out directly
  in notify handler.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 12:05:18 +08:00
Junjie Mao
6e96243b01 HV: io: drop REQ_STATE_FAILED
Now the DM has adopted the new VHM request state transitions and
REQ_STATE_FAILED is obsolete since neither VHM nor kernel mediators will set the
state to FAILED.

This patch drops the definition to REQ_STATE_FAILED in the hypervisor, makes
''processed'' unsigned to make the compiler happy about typing and simplifies
error handling in the following ways.

* (dm_)emulate_(pio|mmio)_post no longer returns an error code, by introducing a
  constraint that these functions must be called after an I/O request
  completes (which is the case in the current design) and assuming
  handlers/VHM/DM will always give a value for reads (typically all 1's if the
  requested address is invalid).

* emulate_io() now returns a positive value IOREQ_PENDING to indicate that the
  request is sent to VHM. This mitigates a potential race between
  dm_emulate_pio() and pio_instr_vmexit_handler() which can cause
  emulate_pio_post() being called twice for the same request.

* Remove the ''processed'' member in io_request. Previously this mirrors the
  state of the VHM request which terminates at either COMPLETE or FAILED. After
  the FAILED state is removed, the terminal state will always be constantly
  COMPLETE. Thus the mirrored ''processed'' member is no longer useful.

Note that emulate_instruction() will always succeed after a reshuffle, and this
patch takes that assumption in advance. This does not hurt as that returned
value is not currently handled.

This patch makes it explicit that I/O emulation is not expected to fail. One
issue remains, though, which occurs when a non-aligned cross-boundary access
happens. Currently the hypervisor, VHM and DM adopts different policy:

* Hypervisor: inject #GP if it detects that the access crossed boundary

* VHM: deliver to DM if the access does not complete falls in the range of a
  client

* DM: a handler covering part of the to-be-accessed region is picked and
  assertion failure can be triggered.

A high-level design covering all these components (in addition to instruction
emulation) is needed for this. Thus this patch does not yet cover the issue.

Tracked-On: #875
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 12:04:12 +08:00
Junjun Shan
ca83c09b9f hv: treewide: fix multiple MISRAC violations
MISARC has requirements about  Marco redefinition, usage of ++ or -- and
assignment operator in boolean expression. This patch is used to solve
these violations.

The modifications are summarized as following:
1.The HC_VM_SET_MEMORY_REGION, HC_VM_GPA2HPA, HC_VM_SET_MEMORY_REGIONS are
redefined twice in acrn_hv_des.h, so delete them to solve the macro
redefinition violations.

2.The macro BUS_LOCK are redefined in bits.h and atomic.h, then delete
the declaration in both two files, add a new declaration in cpu.h and
include the header file.

3.modify the code to solve the improper usage of -- operators in string.c.

4.modify the while loop to for loop to avoid assignment operator in
boolean expression in vlapic.c.

v1 -> v2:
 *Modify the format of commit logs and signed-off name.

 *Modify the code format from 'd = d-1;' to 'd--;' to be better.

Signed-off-by: Junjun Shan <junjun.shan@intel.com>
2018-08-15 11:21:09 +08:00
Kaige Fu
b5a233da9f HV: Enclose debug specific code with #ifdef HV_DEBUG
Thare some debug specific code which don't run on release version, such as vmexit_time,
vmexit_cnt, sbuf related codes, etc...

This patch encloses the codes with #ifdef HV_DEBUG.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 11:17:29 +08:00
Shiqing Gao
6744a179fc hv: treewide: fix 'Shifting value too far'
MISRA-C requires that shift operation cannot exceed the word length.

What this patch does:
- Add the pre condition for 'init_lapic' regarding to 'pcpu_id'
  Currently, max 8 physical cpus are supported.
  Re-design will be required if we would like to support more physical
   cpus.
  So, add the pre condition here to avoid the unintentional shift
   operation mistakes.

- Replace the id type with uint8_t in 'vlapic_build_id'
  - For VM0, it uses 'lapic_id' as its id, which is uint8_t.
  - For non VM0, it uses 'vcpu_id' as its id, which is uint16_t.
    Cast this id to uint8_t to make sure there is no loss of data after
     left shifting 24U.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 13:05:44 +08:00
Victor Sun
76e43ac7ce HV: handle trusty on vm reset
- clear run context when reset vcpu;

- destroy trusty without erase trusty memory when reset vm;

changelog:
	v1 -> v2: fix misra violation on calling memset();

Signed-off-by: Sun Victor <victor.sun@intel.com>
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Chi Mingqiang <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-14 09:55:58 +08:00
Yang, Yu-chu
6f1c5fa007 HV: Logical conjunction needs brackets under /arch/x86/guest
The bracket is required when the level of precedence of
the operators is less than 13. Add the bracket to logical
conjunctions. The commit applys the rule to the files under
hypervisor/arch/x86/guest/*

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-14 09:53:32 +08:00
Sainath Grandhi
7380c167ed hv: Add vuart flag to VM descriptions in partition mode
ACRN in partition mode emulates UART for the VMs directly launced
from HV. This patch adds an option to enable/disable vUART for a
VM.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-13 09:34:35 +08:00
Sainath Grandhi
9e02ef54c7 hv: Partition mode ACRN -kernel load and bootargs load address
For Partition mode ACRN, kernel load address and Boot args load address
are hardcoded. Boot args are currently passed from vm description for
each VM. Renamed init_vm0_boot_info to init_vm_boot_info.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-13 09:34:02 +08:00
Yonghua Huang
fc2701db45 HV: move vioapic.c & vpic.c to 'dm' folder
- 'hypervisor/dm' holds devices emulation source in hypervisor

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-08-10 18:50:38 +08:00
Shiqing Gao
98aa74bd6b hv: treewide: fix 'No default case in switch statement'
MISRAC requires that a switch statement shall contain a default clause.

This patch add the default clause and some comments for the ones
violated the rule.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-10 16:49:31 +08:00
Sainath Grandhi
a8fcc0fa4b HV: Add vm_id entry to VM description in partitioning mode
ACRN boots multiple OS in partitioning mode. This patch adds code to assign
vm_id in the vm data structure to be same as the one assigned at compile time.
This makes the vm id deterministic for each VM booted from HV directly.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-10 10:26:38 +08:00
Sainath Grandhi
0c88f9b800 hv: Build mptable for OS in partition mode
This patch is an extension to the commit 6643adff8b.
It uses the mptable API to build mptable for each VM booted by ACRN in partition mode.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-10 10:22:51 +08:00
Sainath Grandhi
e40b998d21 hv: Add EPT mapping for UOS in partitioning mode
Adding code to map memory for UOS in partitioning mode ACRN.
HPA starting above 4GB is used for UOS memory. Supports only contiguous memory
from host for UOS. Current implementation supports only 2 GB for UOS memory.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-10 10:22:06 +08:00
Yan, Like
c492a14e53 hv: pirq: do not indicate priority when allocate vector
It's not necessary to specify priority for dynamic allocated vector, because
nested irq is not supported on HV, and irq of any priority would cause VM exit.

This commit makes the following changes:
 - remove the argument indicating priority in struct irq_request_info and
   following functions:
    ptdev_activate_entry()
    find_available_vector()
    irq_desc_alloc_vector()
    normal_register_handler()
 - change the macro of vector ranges:
    VECTOR_DYNAMIC_START/END for dynamically allocable vectors;
    VECTOR_FIXED_START/END for fixed allocated vectors, such as vector for
    timer etc.

Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-10 10:20:31 +08:00
Mingqiang Chi
229bf32eb5 hv:Refine destroy_secure_world API
-- add clear trusty memory flag
  In some cases such as UOS power off or UOS full reset,
  need to clear trusty memory,no need to clear memory such as
  UOS S3 or UOS system reset,then add a flag to distinguish it
  when destroy secure world.
-- Restore trusty memory to guest normal world.
-- Moved free trusty EPT inside destroy_secure_world
  In some cases such as UOS S3 or UOS system reset,
  only need to free trusty EPT, this patch move free
  trusty EPT inside destroy_secure_world.
  Because PD/PT are shared in both secure world's EPT
  and normal world's EPT,before freeing trusty EPT,
  it will memset all PDPTEs except trusty memory,
  then call 'free_ept_mem', it can only free trusty EPT,
  and does't affect shared normal world EPT.

v2-->v3:
    -- Used new mmu api ept_mr_add when restore trusty memory
       to SOS and normal world
    -- Dropped this patch "Removed reverted page tables for trusty memory"
       because map_mem will be removed in future
       It will have a patch, need to update this api(ept_mr_add),
       it will not create inverted page tables for trusty memory.

v1-->v2:
   -- free trusty ept
       still use free_ept_mem, not add a new api,but need to
       memset pdptes except trusty memory
   -- Removed reverted page tables for trusty memory.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-10 10:17:09 +08:00
Shiqing Gao
40196d16af hv: treewide: fix 'inline function should be declared static'
MISRAC does not allow the use of an inline function with external
linkage.

What this patch does:
- Add the static keyword for the function that is only used in the
  definition file.
- Remove the inline keyword for the function that is used in multiple
  files.

v1 -> v2:
 * Move some functions to headers as static inline function if it is
    possible

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-10 10:16:04 +08:00
dongshen
86180bd4ce HV: Calling into VPCI init/unit functions for partition hypervisor
V4:
 - Clear address cache info after a full cf8/cfc access
 - Add NULL pointer checking when calling init/deinit ops

V3:
 - Do not use ASSERT
 - Loop through the vdev list defined in vm_desctiption table to call the vdev init/unit functions
 - Make the cached vbdf info struct per vm instead of per pcpu

V2:
 - Fixed MISRA violations

Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2018-08-10 10:09:00 +08:00
Binbin Wu
2b22e88b51 hv: init: rm the code of creating guest init page table
If SOS start from 64bit mode, it will use the page table
created by bootloader or BIOS. HV doesn't need to create
page table for it.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-09 16:43:58 +08:00
Binbin Wu
33e1149b29 hv: init: unify init logic for vm0 bsp
In current code, VM0 BSP start mode is hardcoded, in this patch VM0 BSP
start mode is decided by the boot context prepared by bootloader/BIOS.

In current code, VM0 BSP VMCS is override only on UEFI platform.
In this patch, VM0 BSP VMCS is override on both SBL & UEFI platforms.

Also restructure the code of guest init code.
In this patch, a vcpu run_context is initilaized first according to vcpu mode.
Then write the value to vmcs according to run_context value.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-09 16:43:58 +08:00
Binbin Wu
43db87cfed hv: rename acrn_efi.h to vm0_boot.h
The structures defined in acrn_efi.h is x86 related, move it
to acrh/x86/guest/.
Also, the headfile will be used on both SBL & UEFI platforms,
rename it to vm0_boot.h

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-09 16:43:58 +08:00
Qi Yadong
2fc3bdec40 HV: trusty: new hypercall to save/restore context of secure world
New field in VM's structure:
    sworld_snapshot: save cpu_context of secure world.

New hypercall: HC_SAVE_RESTORE_SWORLD_CTX
    In UOS S3 suspend path: trusty kernel driver will call this hypercall
    to require Hypervisor save context of secure world.
    In UOS S3 resume path: virtual firmware will call this hypercall to
    require Hypervisor restore context of secure world.

New bit in secure_world_control.flag:
    ctx_saved: indicate whether cpu_context of secure world is saved.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-09 15:09:15 +08:00
Qi Yadong
b5b769f45a HV: trusty: refine secure_world_control
Define Bitmap flag to indicate secure world's state:
    supported: 0(not supported), 1(supported)
    active:    0(inactive), 1(active)

Refine secure_world_memory:
    base_gpa_in_sos: base_gpa from SOS's view
    base_gpa_in_uos: base_gpa from UOS's view, this is the original base_gpa
                     allocated by bootloader.
    Recording above GPA is for usage of trusty EPT destroy and re-create.
    There is an assumption: the secure world's memory address is contiguous
    in both SOS and physical side.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-09 15:09:15 +08:00
Sainath Grandhi
ff96453993 hv: Boot multiple OS for Partitioning mode ACRN
ACRN in partitioning mode boots multiple OS. Adding code to parse
VM description structure and a reference description structure for
booting 2 OSes.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-09 15:01:57 +08:00
Yin Fengwei
10f0bb012a hv: remove push/pop instruction emulation.
It's not reasonable to use push/pop against mmio. So we remove
the push/pop emulation.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-09 14:46:13 +08:00
Yin Fengwei
fa9fec50e9 hv: inject invalid opcode if decode instruction fails
We inject invalid opcode if instruction decode fails.

We don't support many instruction. If new type guest hit
the invalid opcode and it's necessary to emulate that
instruction, we could add new instruction then.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-09 14:46:13 +08:00
Yin Fengwei
96e99e3a72 hv: use more reliable method to get guest DPL.
The DPL from SS access right field is always correct according
to SDM. We use it instead of using CS selector.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-09 14:46:13 +08:00
Yin Fengwei
63fe48c27f hv: get correct fault address for copy_to/from_gva
When doing copy_to/from_gva, it's possible the guest no page
happens on none-first page. In this case, we need get correct
fault address from gva2gpa.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
2018-08-09 14:46:13 +08:00
Shiqing Gao
4106fadeb3 hv: treewide: fix 'Switch empty default has no comment'
This patch add some comments after the default and before the break
in the switch statement based on MISRA-C requirement.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-08 16:01:57 +08:00
Sainath Grandhi
04b4c9110c hv: Adding a wrapper on top of prepare_vm0
Added prepare_vm function as a wrapper function on top of prepare_vm0.
This makes adding support for partition mode ACRN to boot multiple
VMs from HV cleaner.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-08 15:53:46 +08:00
Kaige Fu
b78aa347e0 HV: instr_emul: Make vm_update_register/rflags as void
vm_update_register calls vm_get/set_register to update register and vm_update_rflags
calls vm_update_register to update RFLAGS.

We have make vm_get/set_register as non-failed function in previous patch.
So, this patch make the vm_update_register/rflags as void.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-08 09:59:04 +08:00
Kaige Fu
12726dbfc9 HV: instr_emul: Make vie_read/write_bytereg as non-failed function
vie_read/write_bytereg call vm_get/set_register to get/set byteregs.

We have make vm_get/set_register as non-failed function in previous patch.
So, this patch make the vie_read/write_bytereg as non-failed function too.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-08 09:59:04 +08:00
Kaige Fu
59c0f355c8 HV: instr_emul: Make vm_set/get_register as non-failed function
Originally, vm_set/get_register return -EINVAL when "vcpu == NULL" or reg is invalid.
But, we don't check the return value actually and there is no chance we get an
null-vcpu and invalid reg in current implementation.

This patch add pre-assumptions about valid parameters before the function and make
them as non-failed functions.

  - static uint64_t vm_get_register(struct vcpu *vcpu, enum cpu_reg_name reg)
  - static void vm_set_register(struct vcpu *vcpu, enum cpu_reg_name reg, uint64_t val)

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-08 09:59:04 +08:00
Kaige Fu
b6b7e75ee4 HV: instr_emul: Make vm_get_seg_desc a void function
Originally, vm_get_seg_desc return -EINVAL when "vcpu == NULL" or seg is invalid.
But, we don't check the return value actually and there is no chance we get an
null-vcpu and invalid seg in current implementation.

This patch adds pre-assumptions and makes the function as void.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-08 09:59:04 +08:00
Kaige Fu
820b5e4965 HV: instr_emul: Remove dead code
This patch just removes some dead codes related to Instruction Emulation.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-07 12:09:22 +08:00
Kaige Fu
f03ae8d09c HV: instr_emul: Rearrange logic of instr_emul*
Originally, there is cross-references between instr_emul.h and instr_emul_wrapper.h.
User must include both of them when calling instruction emulation functions. This
will raise up some confusion and inconvenience.

So we rearrange the logic of instruction emulation code as following:

  - External API -- defined in instr_emul.h
     * decode_instruction(struct vcpu *vcpu)
     * emulate_instruction(struct vcpu *vcpu)

  - Make all other functions as static in instr_emul.c

  - Remove instr_emul_wrapper.c/h

No functional change.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-07 12:09:22 +08:00
Kaige Fu
ce79d3aa24 HV: instr_emul: Handle error gracefully
ASSERT is too strict for HV when error happens during emulating instruction.
This patch remove all ASSERT and return a negative error code when failing to
emulate instruction.

Originally, getcc will return -EINVAL when opsize are not one of (1, 2, 4, 8).
But theoretically, opsize in current implementation can only be one of (1, 2, 4, 8).
So, we will always get valid "cc".

This patch add a pre-assumption and make sure that getcc always return valid value.

For the current code, #GP will be injected to guest if something goes wrong with
instruction emulation.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-07 12:09:22 +08:00
Kaige Fu
8836abef21 HV: instr_emul: Unify params passing to emulate_xxx
There are so many __unused prefix spaning the emulate_xxx functions. This patch
unify the parameters of emulate_xxx to avoid it.

  - All emulate_xxx functions are defined as emulate_xxx(struct vcpu *vcpu, instr_emul_vie *vie)
    or emulate_xxx(struct vcpu *vcpu, instr_emul_vie *vie, struct vm_guest_paging *paging).

  - Move mmio_read/write to instr_emul.c and call them directly.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-07 12:09:22 +08:00
Jason Chen CJ
8a95b2abdc vcpu: add ext context support for world switch
move most of fields from run_context into ext_context for world switch.
these fields do not need doing runtime save/restore during vm exit/entry.

v3:
- update cr0/cr4 registers switch method

v2:
- use struct name ext_context instead of saved_context
- updated according to previous v2 patch

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-07 09:55:13 +08:00
Jason Chen CJ
3d5d6c96ec vcpu: add get/set register APIs
there will be 3 types of vcpu runtime contexts:
- runtime contexts always saved/restored during VM exit/entry, which
  include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and
  msr for spectre control (ia32_spec_ctrl)
- runtime contexts on-demand cached/updated during VM exit/entry, which
  include frequently used registers rsp, rip, efer, rflags, cr0 and cr4
- runtime contexts always read/write from/to VMCS, which include left
  registers not in above

this patch add get/set register APIs for vcpu runtime contexts, and unified
the save/restore method for them according to above description.

v3:
- update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4,
  use on-demand cache for reading, but always write to VMCS for writing.

v2:
- use reg_cached/reg_updated for on-demand runtime contexts
- always read/write cr3 from/to VMCS

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-07 09:55:13 +08:00
Shiqing Gao
b4a2ff5022 hv: treewide: fix 'Prototype and definition name mismatch'
Fix the parameter name mismatch between API declaration and definition.

v2 -> v3:
 * Fix two more violations which are missed in previous report.
   shell_puts and console_write

v1 -> v2:
 * Replace 'ret_desc' with 'desc'

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-06 16:04:40 +08:00
Yu Wang
6e86d4841d hv: vioapic: set remote IRR to zero once trigger mode switch to edge
In some special scenarios, the LAPIC somehow hasn't send EOI to IOAPIC
which cause the Remote IRR bit can't be clear. To clear it, some OSes
will use EOI Register to clear it for 0x20 version IOAPIC, otherwise
use switch Trigger Mode to Edge Sensitive to clear it.

This patch emulate this IOAPIC behavior to satisfy this requirement.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
1e1886794e hv: vioapic: remove EOI register support
The IOAPIC specification defined EOI register for 0x20 version. The
original vioapic code implemented this register but the version was
still export as 0x11.

Tried to set 0x20, the Linux kernel has't access this EOI register,
still rely on lapic to send eoi.

From Linux ioapic driver comments, it says that only send EOI via EOI
register when met IOAPIC hardware bug.

This patch removes all 0x20 IOAPIC code to reduce the code size.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
f96f048f71 hv: vioapic: change the variable type of pin to uint32_t
To make vioapic simpler, avoid lots of code to convert variable type
between uint8_t and uint32_t.

This patch changes all variable type of pin related variables to
uint32_t instead of original uint_8.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
b13882f8bd hv: vioapic: improve the vioapic reset flow
During ioapic reset, some registers need to be set to the default value
which defined in ioapic spec.

So far, the vioapic function only be called by ioapic itself in
ioapic_init. And just invoked after calloc the vioapic object, so all
the content are already set to zero. But this vioapic_reset function be
exported as one API which maybe invoked by other scenarios in future.

So this patch resolves this potential issue.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
86de47b142 hv: vioapic: correct the ioapic id mask
The APIC ID field should be bit 24:27 in IOAPIC Identification register.
The bits 28:31 are reserved bits which need to be avoid touched.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
68cbdb39de hv: vioapic: avoid deliver unnecessary interrupt for level trigger
For level sensitive trigger mode, the vioapic should not deliver extra
interrupt to vlapic if the previous one hasn't received EOI.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
771c6db321 hv: vioapic: refine vioapic_mmio_rw function
Merge multiple if to switch-case. And set 0xFFFFFFFFU as the default
value of undefined address.

And the IOREGSEL register only bits 7:0 are defined, so mask the other
bits for read operation.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
f0d2291fe2 hv: vioapic: check vector prior to irr in EOI write emulation
Check the vector first to avoid unnecessary irr check.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Yu Wang
fc4162918a hv: vioapic: refine vioapic mmio access related code
1, Remove vioapic_mmio_read/vioapic_mmio_write, and combine them to
vioapic_mmio_rw.

2, The vioapic_read/write are used for emulate the ioapic indirect
access logic. So change their name with vioapic_indirect as the prefix.

Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-06 12:32:35 +08:00
Mingqiang Chi
7345677bbb hv:cleanup vmid related code
Remove structure vm_attr
Wrap two APIs alloc_vm_id and free_vm_id

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-06 12:27:53 +08:00
Sainath Grandhi
6643adff8b HV: Adding mptable support for partition mode ACRN
Partitioning mode of ACRN needs to build mptable for UOS.
UOS uses mptable instead of ACPI tables.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-03 13:36:40 +08:00
Kaige Fu
c27e25052b HV: instr_emul: Move op_byte from vie_op to instr_emul_vie
one/two_byte_opcodes is indexed by op_byte. So vie_op->op_byte is unnecessary.
This patch remove it and add a new variable opcode to instr_emul_vie.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-03 13:05:12 +08:00
Kaige Fu
baf055ec21 HV: instr_emul: Using size2mask array directly
There are size2mask array to convert addsize to corresponding mask and function
vie_size2mask doing the same thing except validation check of addrsize.
Theoretically, addrsize can only be one of (1, 2, 4, 8). So, the check of addrsize
is unnecessary.

This patch remove vie_size2mask and use size2maks directly.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-03 13:05:12 +08:00
Kaige Fu
b6a0a36cd1 HV: instr_emul: Remove vie_read_register
We have vm_set/get_register here. There is no need to wrap the function with
vie_read_register.

This patch remove it.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-03 13:05:12 +08:00
Arindam Roy
37026590c9 HV: Rename functions, variables starting with "_"
In order to comply with MISRA C rules, renamed vairables
and function names starting with "_".
The major changes invloves mostly static function
names, as they are being called inside the same file
by a wrapper function.

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-08-03 12:49:01 +08:00
Mingqiang Chi
a3b44a2fa8 hv:Replace 0(cpu_id) with BOOT_CPU_ID
Replace 0(pcpu_id/vcpu_id) with BOOT_CPU_ID

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-03 11:27:52 +08:00
Mingqiang Chi
ae8836d960 hv:fix return value violation for vioapic_get_rte
Change this API to void type
Add pre-condition, state the input parameters are not NULL.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 14:47:43 +08:00
Mingqiang Chi
61782d7430 hv:Rename port/mmio read and write APIs
mmio_write_long --> mmio_write32
mmio_write_word --> mmio_write16
mmio_write_byte --> mmio_write8
mmio_read_long  --> mmio_read32
mmio_read_word  --> mmio_read16
mmio_read_byte  --> mmio_read8

io_write_long --> pio_write32
io_write_word --> pio_write16
io_write_byte --> pio_write8
io_read_long  --> pio_read32
io_read_word  --> pio_read16
io_read_byte  --> pio_read8
io_write      --> pio_write
io_read       --> pio_read

setl --> set32
setw --> set16
setb --> set8

igned-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-08-02 14:03:38 +08:00
Yin Fengwei
f576f97ea8 hv: add vm restart API
And export the API to DM. DM will do system reboot/S3 resume based
on this API.

Also add the pre-assumption description for some vm APIs.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 13:14:03 +08:00
Xiangyang Wu
77c3917544 HV:treewide:avoid using multiple # or ## in a macro
In the C99 standard, the order of evaluation associated with
multiple #, multiple ## or a mix of # and ## preprocessor
operator is unspecified. For this case, gcc 7.3.0 manual
does not specify related implementation. So it is unsafe
to use multiple # or ## in a macro.
BTW, there are some macros with one or more "##" which are
not used by hypervisor.

Update relate codes to avoid using multiple # or ## in a macro;
Remove unused macros with one or more "##";
Remove "struct __hack;" at the end of GETCC since it is useless.

Note:
     '##' operator usage constraints: A ## preprocessing token shall
     not occur at the beginning or at the end of a replacement list
     for either form of macro definition.
V1--V2:
	Update relate codes to avoid using multiple # or ## in a macro.
V2-->V3:
	Remove unused macros with one or more "##";
	Remove "struct __hack;" at the end of GETCC since it is useless.

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-02 13:10:16 +08:00
Huihuang Shi
1664e0c842 HV:fix rest integer violations
Fix integer related violations.
V1->V2:
  clean all memset/calloc integer violations excpet bsp/boot directory

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-02 09:51:58 +08:00
Shiqing Gao
51c75e9e3c hv: treewide: fix 'Function prototype/defn param type mismatch'
Fix the parameter type mismatch between API declaration and definition.

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-01 15:53:29 +08:00
Victor Sun
00bfde3cde HV: rename resume_vm to start_vm in hypercall api
Currently we don't support resume VM in HC API, the real meaning
of the code is to start VM.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-01 12:06:54 +08:00
Xiangyang Wu
6e77a8d5f1 HV:treewide:rename enum vpic_wire_mode, stack_canary, segment_override, pde_index
For data structure types "enum vpic_wire_mode, struct stack_canary",
its name is identical with variable name in the same scope.
This MISRA C  violation is detected by static analysis tool.
For variables "segment_override, pde_index", its name is identical
with function name. This MISRA C  violation is detected.
Naming convention rule:Variable name can be shortened from
its data structure type name.

The following udpates are made:
enum vpic_wire_mode vpic_wire_mode-->enum vpic_wire_mode wire_mode
struct stack_canary stack_canary-->struct stack_canary stk_canary
uint8_t segment_override:1 --> uint8_t seg_override:1
uint32_t pde_index--> uint32_t pde_idx

V1-->V2:
	Remove update "enum cpu_state cpu_state-->enum cpu_state state"
	and "enum irqstate irqstate-->enum irq_ops_mode ops_mode", other
	patch will cover it.
V2-->V3:
	Update "uint32_t pde_index--> uint32_t pde_idx".

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2018-07-31 11:20:21 +08:00
Wei Liu
52fe9f419f hv: use macro instead of specify number
use macro instead of specify number

Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-31 11:17:11 +08:00
Xiangyang Wu
8e2c730043 HV:VLAPIC:add suffix "_fn" for function pointer
For some function pointer type, its name is identical with
variable name in the same scope. This MISRA C violation is
detected.

Naming convention rule:If the type is function
pointer, its name needs suffix "_fn".

The following udpates are made:
*apicv_set_intr_ready-->*apicv_set_intr_ready_fn
*apicv_pending_intr-->*apicv_pending_intr_fn
*apicv_set_tmr-->*apicv_set_tmr_fn
*apicv_batch_set_tmr-->*apicv_batch_set_tmr_fn
*apicv_intr_accepted-->*apicv_intr_accepted_fn
*apicv_post_intr-->*apicv_post_intr_fn
*enable_x2apic_mode-->*enable_x2apic_mode_fn

V1-->V2:
	Update function pointer when it is used as calling
	since no need to dereference a function pointer
	before calling.

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-31 10:33:22 +08:00
Xiangyang Wu
2c95a8c4aa HV:treewide:rename struct pic and iommu_domain
For data structure types "struct pic and struct iommu_domain",
its name is identical with variable name in the same scope.
This MISRA C  violation is detected.

Naming convention rule:If the data structure type is used by only one
module and its name meaning is simplistic, its name needs prefix
shorten module name.
Naming convention rule:Variable name can be shortened from its
data structure type name.

The following udpates are made:
struct pic pic-->struct i8259_reg_state i8259
struct iommu_domain iommu_domain-->struct iommu_domain iommu

V1-->V2:
	Update "struct iommu_domain iommu_domain-->struct iommu_domain iommu"

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-31 10:33:22 +08:00
Junjie Mao
17771c0ac2 HV: io: refine state transitions of VHM requests
Instead of using two members for maintaining the state of a VHM request, this
patch replaces the transitions with a single state. Basically the lifecycle of a
VHM request shall be:

    FREE -> PENDING -> PROCESSING -> COMPLETE -> FREE -> ...

The structure header of vhm_request has more details of the transitions access
limitations under different states.

Also drop the set but unused member vcpu.ioreq_pending.

For backward-compatibility, the obsolete 'valid' member is still kept and
maintained before SOS and DM adapts to the new state transitions.

v2 -> v3:

    * Use complete_ioreq to mark an I/O request finished in
      dm_emulate_(pio|mmio)_post.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-31 10:22:03 +08:00
Junjie Mao
d8179519b9 HV: io: add post-work for PCICFG and WP requests
Currently no post-work is done for I/O requests of type PCICFG or WP. The
impacts include:

    1. ''valid'' in VHM request buffers are left as 1 even after the I/O request
       completes. This violates the pre-condition of acrn_insert_request_wait()
       but does not cause failures since a new I/O request can never happen
       before the previous one completes.

    2. Values read from PCI configuration spaces are never passed to UOS.

This patch adds the post-work for these two kinds of I/O requests. The post-work
for port I/O is invoked for PCICFG since it is essentially a port I/O and the
request structure is compatible. No post-work is needed for WP as it is only
triggered for EPT violations on writes, while post-work is mainly for reads.

v2 -> v3:

    * Consistently use 0/1 (not false/true) for the ''valid'' member.
    * Add comments to suggest when the hypervisor can see REQ_PCICFG and why
      dm_emulate_pio_post also works in such cases.
    * Rename: mark_ioreq_done -> complete_ioreq
    * Rename: complete_request -> emulate_io_post
    * Rename: hcall_notify_req_finish -> hcall_notify_ioreq_finish

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-07-31 10:22:03 +08:00
Xiangyang Wu
c477211d4e HV:treewide:rename struct key_info, pir_desc, map_params
For data structure types "struct key_info, struct pir_desc,
struct map_params", its name is identical with variable name
in the same scope. This MISRA C  violation is detected by
static analysis tool.
Naming convention rule:If the data structure type is used by only one
module and its name meaning is simplistic, its name needs prefix
shorten module name.

The following udpates are made:
struct key_info-->struct trusty_key_info
struct pir_desc-->struct vlapic_pir_desc
struct map_params-->struct mem_map_params

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-30 10:18:39 +08:00
Xiangyang Wu
8205c9a482 HV:INSTR_EMUL:Rename struct vie, vie_op, and emul_ctxt
For data struct type struct vie, emul_ctxt, its name
is identical with variable name in the same scope.
This MISRA C violation is detected by static analysis
tool.
According to naming convention rule: If the data structure
type is used by only one module and its name meaning is
simplistic, its name needs prefix shorten module name.
Follow the same rule, data structure name "vie_op" needs
to be renamed;

The following updates are made in this patch:
struct vie-->struct instr_emul_vie
struct vie_op-->struct instr_emul_vie_op
struct emul_ctxt-->struct instr_emul_ctxt

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-30 10:16:36 +08:00
Xiangyang Wu
3446e84ea5 HV:treewide:rename struct timer as struct hv_timer
The variable timer's name is identical with struct
timer s name. This MISRA C violation is detected
by static analysis tool.
According to naming convention rule: If the data
structure type is used by multi modules, its
corresponding logic resource is only used by
hypervisor/host and isn't exposed to external
components (such as SOS, UOS), its name meaning
is simplistic (such as timer), its name needs prefix
"hv_".

Rename struct timer as struct hv_timer.
Replace regular expression:s/struct timer\([ ),;\t\*]\+\)
/struct hv_timer\1

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-30 10:16:36 +08:00
Arindam Roy
a2fe964de8 HV: Rename functions beginning with "_"
V1:
In order to remove MISRA C violations for rule
219S, rename functions, macros whose name
starts with "_".
Also removed some __mmio functions because they are
duplicates and are not used anywhere.
Renamed functions like __assert, to asm_assert,
because they were only wrappers around asm calls.

V2:
Over and above the changes on V1, modified bitmap
functions names to lock (corresponding to unlock)
introduced in V1

Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2018-07-30 10:11:54 +08:00
Xiangyang Wu
c01e675582 HV:VLAPIC:rename variable vlapic_timer in the struct and function
The variable vlapic_timer's name is identical with struct
vlapic_timer's name. This MISRA C violation is detected
by static analysis tool.

Rename variable vlapic_timer as vtimer.
Replace regular expression: s/vlapic_timer\([ ;,.)\-]\+\)/vtimer\1

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2018-07-27 12:39:24 +08:00
Huihuang Shi
59771ff461 HV:treewide:fix "Reference parameter to procedure is reassigned"
Parameter's type which is pointer should not be changed in the
scope of function,assign it's value to local variable to fixed
it out.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 12:17:12 +08:00
Xiangyang Wu
58b42baa74 HV:treewide:rename struct vpic as struct acrn_vpic
There are many naming violations detected by static analysis
tool. Data structure type name is the same as variable name.
According to naming convention rules, If the data structure
type is used by multi modules and its name meaning is
simplistic (such as vcpu, vm), its name needs prefix "acrn_".

Rename struct vpic as struct acrn_vpic.
Replace regular expression:s/struct vpic\([ ),;\t\*]\+\)/struct acrn_vpic\1

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 11:27:12 +08:00
Xiangyang Wu
33fdfd05f1 HV:treewide:rename struct vlapic as struct acrn_vlapic
There are many naming violations detected by static analysis
tool. Data structure type name is the same as variable name.
According to naming convention rules, If the data structure
type is used by multi modules and its name meaning is
simplistic (such as vcpu, vm), its name needs prefix "acrn_".

Rename struct vlapic as struct acrn_vlapic
Replace regular expression:s/struct vlapic\([ ),;\t\*]\+\)/struct acrn_vlapic\1

Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 11:27:12 +08:00
Junjie Mao
88f74b5dbb HV: io: unify vhm_request req and mem_io in vcpu
The current struct vcpu has two members, namely 'struct vhm_request req' and
'struct mem_io mmio', that hold similar info, including the address, direction, size,
value and status of mmio reqeusts.

As a step towards a unified framework for both MMIO/PIO, this patch unifies
these two members by a tailored version of vhm_reqeust, mostly with the reserved
fields dropped. The definitions to request types, directions and process status
are reused.

Handling errors during emulations will be revisited after the I/O emulation
paths are unified. Thus for this patch the mmio.mmio_status in inherited by
io_req.processed which is not yet properly processed.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 10:50:19 +08:00
Yonghua Huang
45d6f72b51 HV:refine 'create_vm()' to avoid potential crash and memory leak
hypervisor will crash if user try to call hypercall
  HC_CREATE_VM in infinite style.

  actually, the number of VMs hypervisor can support
  depends on the bit width of 'vmid_bitmap'.should
  return error in case of overflow.

  other cleanup for this function to avoid memory leak
  in case of failure.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-27 10:40:28 +08:00
Li, Fei1
236bb10e4d hv: mmu: refine delete page table mapping
Merge mmu_modify with mmu_del to mmu_modify_or_del(..., type).
While type is MR_MODIFY, the actual action is doing mmu_modify; while
type is MR_DEL, the actual action is doing mmu_del.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 12:46:34 +08:00
Li, Fei1
34c6862a28 hv: hypercall: add support to change guest page write permission
Add hcall_change_vm_page_wp_perm to change guest one page write permission.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 12:46:34 +08:00
Huihuang Shi
5189bcd272 HV:treewide:fix "Attempt to change parameter passed by value"
In the function scope,the parameter should not be
changed as Misra required.
V1->V2 recover some violations because of ldra's false positive.
V2->V3 sync local variable' type to parameter's type with the prefix of const.

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-26 09:35:52 +08:00
Jason Chen CJ
2dca23c7c9 add hypercall hc_sos_offline_cpu support
SOS boot with all physicall cpus, before running UOS, it should free
CPU resource by offline not used cpus
- first do standard cpu offline flow
- then call hcall_sos_offline_cpu hypercall to release cpu resource really

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-25 17:18:14 +08:00
Jason Chen CJ
589c72382a add CONFIG_VM0_DESC support
if defined CONFIG_VM0_DESC, HV will use predefined vm0_desc to config
VM0, otherwise, HV will run VM0 with all physical cpus.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-25 17:18:14 +08:00
Zheng, Gen
6788c09c39 hv: bug fix on operating spin_lock
In vioapic emulating code, the vioapic spinlock is taken twice
in the same context.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-07-25 15:34:02 +08:00
Binbin Wu
586b527e2c hv: cpu: remove general-purpose register mapping in instruction emulation
The general-purpose register layout is identical to instructio emulation context.
So no need to do the mapping.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2018-07-25 13:05:38 +08:00
Binbin Wu
b2802f3d1d hv: cpu: align general-purpose register layout with vmx
In current code, general-purpose register layout in run_context is not align with the
general-purpose register index when vmexit. So hv needs to map the index used during
vmexit to the index of the general-purpose register in run_context.
This patch align the layout, so that no mapping needed.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-25 13:05:38 +08:00
Li, Fei1
f7f04ba67f hv: mmu: minor fix about hv mmu && ept modify
1. fix some description for hv mmu_modify
2. add pml4_page input parameter for ept_mr_modify to keep align with
ept_mr_add and ept_mr_del which will support add or delete MR for trusty.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-24 12:48:45 +08:00
Li, Fei1
502e3e2e65 hv: mmu: refine set guest memory region API
1. rename set_vm_memmap to set_vm_memory_region
2. split ept_mmap into ept_mr_add and ept_mr_del

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-24 12:48:45 +08:00
Xiangyang Wu
27fbf9b215 HV:treewide:Fixing pointer castings
In the hypervisor, there are many casts from
an void pointer to integer pointer, then from
integer pointer to structure pointer.
These pointer castings are detected by static analysis
tool. All pointer casts are violations, There are
some duplicated pointer cast. This will make deviation
analysis complex.
BTW, there are one useless pointer casting and one
wrong pointer casting in the hypervisor.

Remvoe duplicated pointer casts to make deviation analysis
simple;
Remove one useless pointer casting;
Update one wrong pointer casting.

Note: There are many void type pointer casts, non-void type
pointer is casted to void type pointer, char type pointer casts,
non-char type pointer is casted to char type pointer. These pointer
casting is need by the memory management module, IO moudle etc.
Deviation analysis will be made and recoded in the analysis report.

V1-->V2:
	Fix mixing pointer and array voilation.
V2-->V3:
	Remvoe pointer casting from integer pointer into
	non-void/non-char pointer directly;
	Remove redundant type conversion.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-24 10:56:24 +08:00