Commit Graph

928 Commits

Author SHA1 Message Date
Sainath Grandhi
a7389686a7 hv: Precondition checks for vcpu_from_vid for lapic passthrough ICR access
Since the vapic_id is from VM, need to check for pre-condition before passing
vcpu_id to vcpu_from_vid. This is in the path of LAPIC passthrough ICR
access

Tracked-On: #3170
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-30 10:10:21 +08:00
Binbin Wu
7a915dc397 hv: vmsr: present sgx related msr to guest
Present SGX related MSRs to guest if SGX is supported.

- MSR_IA32_SGXLEPUBKEYHASH0 ~ MSR_IA32_SGXLEPUBKEYHASH3:
  SGX Launch Control is not supported, so these MSRs are read only.
- MSR_IA32_SGX_SVN_STATUS:
  read only
- MSR_IA32_FEATURE_CONTROL:
  If SGX is support in VM, opt-in SGX in this MSR.
- MSR_SGXOWNEREPOCH0 ~ MSR_SGXOWNEREPOCH1:
  The two MSRs' scope is package level, not allow guest to change them.
  Still leave them in unsupported_msrs array.

Tracked-On: #3179
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-29 11:24:13 +08:00
Binbin Wu
1724996bc5 hv: vcpuid: present sgx capabilities to guest
If sgx is supported in guest, present SGX capabilities to guest.
There will be only one EPC section presented to guest, even if EPC
memory for a guest is from muiltiple physcial EPC sections.

Tracked-On: #3179
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-29 11:24:13 +08:00
Binbin Wu
65d437283e hv: vm: build ept for sgx epc reource
Build EPT entries for SGX EPC resource for VMs.
- SOS: EPC resrouce will be removed from EPT of SOS, don't support SGX virtualization for SOS.
- Non-SOS: build ept mapping for EPC resource for guest.
  Guest base address and size is specified in vm configuration.

Tracked-On: #3179
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-29 11:24:13 +08:00
Yin Fengwei
c5cfd7c200 vm state: reset vm state to VM_CREATED when reset_vm is called
When we call reset_vm() function to reset vm, the vm state
should be reset to VM_CREATED as well.

Tracked-On: #3182
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-29 10:43:03 +08:00
Binbin Wu
7e80a6eee3 hv: vm: enable iommu after vpci init
In current code, vpci do the pci enumartion and add pci devices to the
context table of iommu.
Need to enable iommu DMA address translation later than vpci init.
Otherwise, in UEFI platform, there will be a shot time that address translation
is enabled, but the context table is not setup.
For the devices active in UEFI environment will have problem on address translation.

Tracked-On: #3160
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-24 11:46:44 +08:00
Zide Chen
bfc08c2812 hv: move msr_bitmap from acrn_vm to acrn_vcpu_arch
At the time the guest is switching to X2APIC mode, different VCPUs in the
same VM could expect the setting of the per VM msr_bitmap differently,
which could cause problems.

Considering different approaches to address this issue:
1) only guest BSP can update msr_bitmap when switching to X2APIC.
2) carefully re-write the update_msr_bitmap_x2apic_xxx() functions to
   make sure any bit in the bitmap won't be toggled by the VCPUs.
3) make msr_bitmap as per VCPU.

We chose option 3) because it's simple and clean, though it takes more
memory than other options.

BTW, need to remove const modifier from update_msr_bitmap_x2apic_xxx()
functions to get it compiled.

Tracked-On: #3166
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-24 11:37:13 +08:00
Victor Sun
1fe5711170 HV: validate pstate by checking px ctl range
The previous function just check the pstate target value in PERF_CTL msr
by indexing px data control value which comes from ACPI table, this would
bring a bug in the case that guest is running intel_pstate_driver:
the turbo pstate target value from intel_pstate driver is in a range
instead of fixed value in ACPI _PSS table, thus the turbo px request would
be rejected. This patch fixed this issue.

Tracked-On: #3158

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-24 11:36:54 +08:00
Mingqiang Chi
04ccaacb9c hv:not allow SOS to access prelaunched vm memory
filter out prelaunched vm memory from e820 table
and unmap prelaunched vm memory from ept table
before boot service OS

Tracked-On: #3148
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-05-23 19:01:48 +08:00
Zide Chen
5a23f7b664 hv: initial host reset implementation
- add the GUEST_FLAG_HIGHEST_SEVERITY flag to indicate that the guest has
  privilege to reboot the host system.

- this flag is statically assigned to guest(s) in vm_configurations.c in
  different scenarios.

- implement reset_host() function to reset the host. First try the ACPI
  reset register if available, then try the 0xcf9 PIO.

Tracked-On: #3145
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-23 18:24:17 +08:00
Sainath Grandhi
536c69b9ff hv: distinguish between LAPIC_PASSTHROUGH configured vs enabled
ACRN supports LAPIC emulation for guests using x86 APICv. When guest OS/BIOS
switches from xAPIC to x2APIC mode of operation, ACRN also supports switching
froom LAPIC emulation to LAPIC passthrough to guest. User/developer needs to
configure GUEST_FLAG_LAPIC_PASSTHROUGH for guest_flags in the corresponding
VM's config for ACRN to enable LAPIC passthrough.

This patch does the following

1)Fixes a bug in the abovementioned feature. For a guest that is
configured with GUEST_FLAG_LAPIC_PASSTHROUGH, during the time period guest is
using xAPIC mode of LAPIC,  virtual interrupts are not delivered. This can be
manifested as guest hang when it does not receive virtual timer interrupts.

2)ACRN exposes physical topology via CPUID leaf 0xb to LAPIC PT VMs. This patch
removes that condition and exposes virtual topology via CPUID leaf 0xb.

Tracked-On: #3136
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-05-23 11:15:31 +08:00
yliu79
c5391d2592 HV: remove unused function vcpu_inject_ac
Change-Id: I4b139e78c372d0941923fc8260db7a3578a894f2
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
26de86d761 HV: remove unused function copy_to_gva
Change-Id: I18a6c860ba4bcec4e5915fa6a2a18ed1ecb20fff
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
163c63d21f HV: remove unused function resume_vm
Change-Id: Ia6b6617e55044b5555a2d80c26a4ef7d7e56b7fa
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
yliu79
c68c6e4af2 HV: remove unused function shutdown_vcpu
Change-Id: Ia6f9aa4d2d603d23bc0cb9c3b12032d1a96504db
Tracked-On: #3123
Signed-off-by: yliu79 <ying2.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:36:03 +08:00
Minggui Cao
fc1cbebe31 HV: remove vcpu arch lock, not needed.
the pcpu just write its own vmcs, not need spinlock.
and the arch.lock not used other places, remove it too.

Tracked-On: #3130

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-22 16:35:26 +08:00
Jason Chen CJ
238d8bbaa2 reshuffle init_vm_boot_info
now only SOS need decide boot with de-privilege or direct boot mode, while
for other pre-launched VMs, they should use direct boot mode.

this patch merge boot/guest/direct_boot_info.c &
boot/guest/deprivilege_boot_info.c into boot/guest/vboot_info.c,
and change init_direct_vboot_info() function name to init_general_vm_boot_info().

in init_vm_boot_info(), depend on get_sos_boot_mode(), SOS may choose to init
vm boot info by setting the vm_sw_loader to deprivilege specific one; for SOS
using DIRECT_BOOT_MODE and all other VMS, they will use general_sw_loader as
vm_sw_loader and go through init_general_vm_boot_info() for virtual boot vm
info filling.

this patch also move spurious handler initilization for de-privilege mode from
boot/guest/deprivilege_boot.c to boot/guest/vboot_info.c, and just set it in
deprivilege sw_loader before irq enabling.

Changes to be committed:
	modified:   Makefile
	modified:   arch/x86/guest/vm.c
	modified:   boot/guest/deprivilege_boot.c
	deleted:    boot/guest/deprivilege_boot_info.c
	modified:   boot/guest/direct_boot.c
	renamed:    boot/guest/direct_boot_info.c -> boot/guest/vboot_info.c
	modified:   boot/guest/vboot_wrapper.c
	modified:   boot/include/guest/deprivilege_boot.h
	modified:   boot/include/guest/direct_boot.h
	modified:   boot/include/guest/vboot.h
	new file:   boot/include/guest/vboot_info.h
	modified:   common/vm_load.c
	modified:   include/arch/x86/guest/vm.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-05-20 18:49:59 +08:00
Zide Chen
865ee2956e hv: emulate ACPI reset register for Service OS guest
Handle the PIO reset register that is defined in host ACPI:

Parse host FADT table to get the host reset register info, and emulate
it for Service OS:

- return all '1' for guest reads because the read behavior is not defined
  in ACPI.
- ignore guest writes with the reset value to stop it from resetting host;
  if guest writes other values, passthru it to hardware in case the reset
  register supports other functionalities.

Tracked-On: #2700
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Zide Chen
26f08680eb hv: shutdown guest VM upon triple fault exceptions
This patch implements triple fault vmexit handler and base on VM types:

- post-launched VMs: shutdown_target_vm() injects S5 PIO write to request
  DM to shut down the target VM.
- pre-launched VMs: shut down the guest.
- SOS: similarly, but shut down all the non real-time post-launched VMs that
  depend to SOS before shutting down SOS.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Zide Chen
9aa3fe646b hv: emulate reset register 0xcf9 and 0x64
- post-launched RTVM: intercept both PIO ports so that hypervisor has a
  chance to set VM_POWERING_OFF flag.
- all other type of VMs: deny these 2 ports from guest access so that
  guests are not able to reset host.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Zide Chen
8ad0fd98a3 hv: implement NEED_SHUTDOWN_VM request to idle thread
For pre-launched VMs and SOS, VM shutdown should not be executed in the
current VM context.

- implement NEED_SHUTDOWN_VM request so that the BSP of the target VM can shut
  down the guest in idle thread.
- implement shutdown_vm_from_idle() to shut down target VM.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-15 11:20:12 +08:00
Li, Fei1
86f5993bc9 hv: vlapic: fix tpr virtualization when VID is not enabled.
1) According SDM Vol 3, Chap 29.1.2, Any VM exit caused by TPR virtualization
is trap-like: the instruction causing TPR virtualization completes before the VM
exit occurs (for example, the value of CS:RIP saved in the guest-state area of
the VMCS references the next instruction). So we need to retain the RIP.
2) The previous implement only consides the situation the guest will reduce the
TPR. However, the guest will increase it. So we need to update the PPR before we
find a deliverable interrupt. For examples: a) if the guest increase the TPR before
a irq windows vmexit, we need to update the PPR when check whether there has a pending
delivery interrupt or not; b) if the guest increase the TPR, then an external irq raised,
we need to update the PPR when check whether there has a deliverable interrupt to inject
to guest.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-05-15 08:59:39 +08:00
Li, Fei1
a68dadb74a hv: vm: minor fix about vRTC
For prelaunched VM, Service OS and postlaunched RT VM, we only need the vRTC
provides backed-up date, so we could use the simple vRTC which implemented
in hypervisor. For postlaunched VM (which is not a RT VM), we needs the device
module to emulate the vRTC for it.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
2019-05-15 08:59:39 +08:00
Li, Fei1
bdae8efb7f hv: instr_emul: fix movzx return memory opsize wrong
There're some instructions which not support bit 0(w bit) flag but which
memory opcode size is fixed and the memory opcode size is not equal to the
register opcode size. In our code, there is movzx (which opcode is 0F B7)
which memory opcode size is fixed to 16 bits. So add a flag VIE_OP_F_WORD_OP
to indicate a instruction which memory opcode size is fixed to 16 bits.

Tracked-On: #1337
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-13 11:53:51 +08:00
Binbin Wu
a581f50600 hv: vmsr: enable msr ia32_misc_enable emulation
Add MSR_IA32_MISC_ENABLE to emulated_guest_msrs to enable the emulation.
Init MSR_IA32_MISC_ENABLE for guest.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
8e310e6ea1 hv: vcpuid: modify vcpuid according to msr ia32_misc_enable
According to SDM Vol4 2.1, modify vcpuid according to msr ia32_misc_enable:
- Clear CPUID.01H: ECX[3] if guest disabled monitor/mwait.
- Clear CPUID.80000001H: EDX[20] if guest set XD Bit Disable.
- Limit the CPUID leave maximum value to 2 if guest set Limit CPUID MAXVal.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
ef19ed8961 hv: vcpuid: reduce the cyclomatic complexity of function guest_cpuid
This patch reduces the cyclomatic complexity of the function guest_cpuid.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
2019-05-09 16:35:15 +08:00
Binbin Wu
f0d06165d3 hv: vmsr: handle guest msr ia32_misc_enable read/write
Guest MSR_IA32_MISC_ENABLE read simply returns the value set by guest.
Guest MSR_IA32_MISC_ENABLE write:
- Clear EFER.NXE if MSR_IA32_MISC_ENABLE_XD_DISABLE set.
- MSR_IA32_MISC_ENABLE_MONITOR_ENA:
  Allow guest to control this feature when HV doesn't use this feature and hw has no bug.

vcpuid update according to the change of the msr will be covered in following patch.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:35:15 +08:00
Jason Chen CJ
41ac9e5d10 rename function & definition from firmware to guest boot
The interface struct & API changes like below:
  struct uefi_context->struct depri_boot_context
  init_firmware_operations()->init_vboot_operations()
  init_firmware()->init_vboot()
  firmware_init_irq()->init_vboot_irq()
  firmware_get_rsdp()->get_rsdp_ptr()
  firmware_get_ap_trampoline()->get_ap_trampoline_buf()
  firmware_init_vm_boot_info()->init_vm_boot_info()

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:33:44 +08:00
Jason Chen CJ
20f97f7559 restruct boot and bsp dir for firmware stuff
currently, ACRN hypervisor can either boot from sbl/abl or uefi, that's
why we have different firmware method under bsp & boot dirs.
but the fact is that we actually have two different operations based on
different guest boot mode:
1. de-privilege-boot: ACRN hypervisor will boot VM0 in the same context as
native(before entering hypervisor) - it means hypervisor will co-work with
ACRN UEFI bootloader, restore the context env and de-privilege this env
to VM0 guest.
2. direct-boot: ACRN hypervisor will directly boot different pre-launched
VM(including SOS), it will setup guest env by pre-defined configuration,
and prepare guest kernel image, ramdisk which fetch from multiboot modules.

this patch is trying to:
- rename files related with firmware, change them to guest vboot related
- restruct all guest boot stuff in boot & bsp dirs into a new boot/guest dir
- use de-privilege & direct boot to distinguish two different boot operations

this patch is pure file movement, the rename of functions based on old assumption will
be in the following patch.

Changes to be committed:
	modified:   ../efi-stub/Makefile
	modified:   ../efi-stub/boot.c
	modified:   Makefile
	modified:   arch/x86/cpu.c
	modified:   arch/x86/guest/vm.c
	modified:   arch/x86/init.c
	modified:   arch/x86/irq.c
	modified:   arch/x86/trampoline.c
	modified:   boot/acpi.c
	renamed:    bsp/cmdline.c -> boot/cmdline.c
	renamed:    bsp/firmware_uefi.c -> boot/guest/deprivilege_boot.c
	renamed:    boot/uefi/uefi_boot.c -> boot/guest/deprivilege_boot_info.c
	renamed:    bsp/firmware_sbl.c -> boot/guest/direct_boot.c
	renamed:    boot/sbl/multiboot.c -> boot/guest/direct_boot_info.c
	renamed:    bsp/firmware_wrapper.c -> boot/guest/vboot_wrapper.c
	modified:   boot/include/acpi.h
	renamed:    bsp/include/firmware_uefi.h -> boot/include/guest/deprivilege_boot.h
	renamed:    bsp/include/firmware_sbl.h -> boot/include/guest/direct_boot.h
	renamed:    bsp/include/firmware.h -> boot/include/guest/vboot.h
	modified:   include/arch/x86/multiboot.h

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-09 16:33:44 +08:00
Yin Fengwei
8626e5aa3a vm_state: Update vm state VM_STATE_INVALID to VM_POWERED_OFF
Replace the vm state VM_STATE_INVALID to VM_POWERED_OFF.
Also replace is_valid_vm() with is_poweroff_vm().
Add API is_created_vm() to identify VM created state.

Tracked-On: #3082
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-08 16:58:41 +08:00
Victor Sun
e2d723d4fa HV: enable acpi pm1a register info fixup
Previously ACPI PM1A register info was hardcoded to 0 in HV for generic boards,
but SOS still can know the real PM1A info so the system would hang if user
trigger S3 in SOS. Enabling PM1A register info fixup will let HV be able to
intercept the operation on PM1A and then make basic function of S3 work for
all boards;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-07 11:39:51 +08:00
Mingqiang Chi
da9ed0eda9 hv:remove some unnecessary includes
remove some unnecessary includes

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2019-05-07 09:10:13 +08:00
Zide Chen
5f87e716b8 hv: release IOMMU irte when releasing ptirq remapping entries
IRTE is freed if ptirq entry is released from remove_msix_remapping() or
remove_intx_remapping(). But if it's called from ptdev_release_all_entries(),
e.g. SOS shutdown/reboot, IRTE is not freed.

This patch adds a release_cb() callback function to do any architectural
specific cleanup. In x86, it's used to release IRTE.

On VM shutdown, vpci_cleanup() needs to remove MSI/MSI-X remapping on
ptirq entries, thus it should be called before ptdev_release_all_entries().

Tracked-On: #2700
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-06 18:25:37 +08:00
Conghui Chen
dd86a78e75 HV: rename 'type' in struct io_request
Rename 'type' in struct io_request to 'io_type' to be more readable.

Tracked-On: #3061
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-06 18:25:20 +08:00
Conghui Chen
e6670b32f4 HV: rename structure acrn_vm_type
Rename structure acrn_vm_type to acrn_vm_load_order as it is used to
indicate the load order instead of the VM type.

Tracked-On: #2291
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-05 11:50:36 +08:00
Yonghua Huang
be2fe2a44d hv:remove accessing shared log buffer cases between stac/clac
Shared buffer is allocated by VM and is protected by SMAP.
Accessing to shared buffer between stac/clac pair will invalidate
SMAP protection.This patch is to remove these cases.
Fix minor stac/clac mis-usage,and add comments as stac/clac usage BKM

Tracked-On: #2526
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-05-05 10:00:32 +08:00
Sainath Grandhi
9214c84600 hv: Rename NORMAL_VM to POST_LAUNCHED_VM
The name NORMAL_VM does not clearly reflect the attribute that these VMs
are launched "later". POST_LAUNCHED_VM is closer to the fact
that these VMs are launched "later" by one of the VMs launched by ACRN.

Tracked-On: #3034
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-29 09:19:51 +08:00
Li, Fei1
536bc5bd12 hv: instr_emul: fix operand size decode
1) For some instructions (like movsx, movzx which we support), there're two operands
and the source operand size is not equal to the dest operand size. In this case,
if we update the memory operand size according to the bit 0(w bit) of opcode,
we will lost the register operand size. This patch tries to fix this by calculating
memory operand size when we want to use it.
2) Calculate memory operand size form operand size and the bit 0(w bit) of opcode
when we want to operate on memory operand.

Tracked-On: #1337
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-28 11:53:24 +08:00
Victor Sun
3bb4308361 HV: check vm id param when dispatching hypercall
If the vmcall param passed from guest is representing a vmid, we should
make sure it is a valid one because it is a pre-condition of following
get_vm_from_vmid(). And then we don't need to do NULL VM pointer check
in is_valid_vm() because get_vm_from_vmid() would never return NULL.

Tracked-On: #2978

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-26 16:21:14 +08:00
Zide Chen
1b7d33a426 hv: separate host e820 and SOS ve820
There are 2 reasons why SOS ve820 has to be separated from host e820:
- in hybrid mode, SOS may not own all the host memory.
- when SOS is being re-launched, it needs an untainted version of host
  e820 to create SOS ve820.

This patch creates sos_e820 table for SOS and keeps host e820 intact
during SOS creation.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-26 16:20:50 +08:00
Conghui Chen
235d886103 HV: vuart: enable vuart console for VM
In previous code, only for pre-launched VM, hypervisor would create
vuart console for each VM. But for post-launched VM, no vuart is
created.
In this patch, create vuart according to configuration in structure
acrn_vm_config. As the new configuration is set for pre-launched VM and
post-launched VM, and the vuart initialize process is common for each
VM, so, remove CONFIG_PARTITION_MODE from vuart related code.

Tracked-On: #2987
Signed-off-by: Conghui Chen <conghui.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 11:21:54 +08:00
Victor Sun
2362e58509 HV: correct usage of GUEST_FLAG_IO_COMPLETION_POLLING
The guest flags of GUEST_FLAG_IO_COMPLETION_POLLING work for NORMAL_VM only;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 11:07:21 +08:00
Yin Fengwei
578592b566 vlapic: refine IPI broadcast to support x2APIC mode
According to SDM 10.6.1, if dest fields is 0xffU for register
ICR operation, that means the IPI is for broadcast.

According to SDM 10.12.9, 0xffffffffU of dest fields for x2APIC
means IPI is for broadcast.

We add new parameter to vlapic_calc_dest() to show whether the
dest is for broadcast. For IPI, we will set it according to
dest fields. For ioapic and MSI, we hardcode it to false because
no broadcast for ioapic and MSI.

Tracked-On: #3003
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-25 09:12:16 +08:00
Kaige Fu
a85d11ca7a HV: Add prefix 'p' before 'cpu' to physical cpu related functions
This patch adds prefix 'p' before 'cpu' to physical cpu related functions.
And there is no code logic change.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-24 10:50:28 +08:00
li bing
25741b62db HV: fix the issue of ACRN_REQUEST_EXCP flag is not cleared.
the problem is : System will crash when run crashme.
The root cause of this problem is that when the ACRN_REQUEST_EXCP flag is set by calling
the vcpu_make_request function, the flag is not cleared.
Add the following statement to the vcpu_inject_exception function to fix the problem:
bitmap_test_and_clear_lock(ACRN_REQUEST_EXCP, &vcpu->arch.pending_req);
Tested that one night, there was no crash.

Tracked-On: #2527
Signed-off-by: bing.li<bingx.li@intel.com>
Acked-by:      Eddie Dong<eddie.dong@intel.com>
2019-04-23 15:17:13 +08:00
Li, Fei1
28d50f1b96 hv: vlapic: add apic register offset check API
Add apic rgister offset check before do vlapic read/write.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
70dd254456 hv: vmsr: refine x2apic MSR bitmap setting
In theory, we should trap out all the x2apic MSR access if APICv is not enabled.
When "Use TPR shadow" and "Virtualize x2APIC mode" are enabled, we could disable
TPR interception; when APICv is fully enabled, besides TPR, we could disable all
MSR read, EOI and self-IPI interception; when we pass through lapic to guest, we
could disable all the MSR access interception except XAPICID/LDR read and ICR write.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
0c347e607a hv: vlapic: wrap APICv check pending delivery interrupt
When in fully APICv mode, we enable VID. All pending delivery interrupts
will inject to VM before VM entry. So there is no pending delivery interrupt.
However, if VID is not enabled, we can only inject pending delivery interrupt
one by one. So we always need to do this check.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
037fffc203 hv: vlapic: wrap APICv inject interrupt API
apicv_advanced_inject_intr is used if APICv fully features are supported,
it uses PIR to inject interrupt. otherwise, apicv_basic_inject_intr is used.
it will use VMCS INTR INFO field to inject irq.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
1db8123c2d hv: virq: refine pending event inject coding style
In order to combine vlapic_apicv_inject_pir and vcpu_inject_vlapic_int.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
fde2c07c0a hv: vlapic: minor fix about APICv inject interrupt
When VID is enabeld, we should always inejct the pending interrupts when vm enter.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Li, Fei1
846b5cf6b7 hv: vlapic: wrap APICv accept interrupt API
The APICv ops is decided once the APICv feature on the physical platform is detected.
We will use apicv_advanced_ops if the physical platform support fully APICv feature;
otherwise, we will use apicv_basic_ops.
This patch only wrap the accept interrupt API for them.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 15:16:56 +08:00
Yonghua Huang
f991d179b0 hv: fix possible buffer overflow in vlapic.c
Possible buffer overflow will happen in vlapic_set_tmr()
  and vlapic_update_ppr(),this path is to fix them.

Tracked-On: #1252
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-23 13:43:25 +08:00
Li, Fei1
2c13ac7400 hv: vmcs: minor fix about APICv feature setting
1) Shouldn't try to set APIC-register virtualization if the physical doesn't
support APICV advanced mode.
2) Remove all APICv features VMCS setting when LAPIC is passed through to guest.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-23 09:47:36 +08:00
Li, Fei1
4fc2009770 hv: instr_emul: check the bit 0(w bit) of opcode when necessary
Not every instruction supports the operand-size bit (w). This patch try to correct
what done in commit-id 9df8790 by setting a flag VIE_OP_F_BYTE_OP to indicate which
instruction supports the operand-size bit (w).

This bug is found by removing VMX_PROCBASED_CTLS2_VAPIC_REGS VMCS setting when the
physical doesn't support this APICv feature. However, if emulated this in MRB board,
the android can't boot because when switch to trusty world, it will check
"Delivery Status" in ICR first. It turns out that this Bit Test instruction is not
emulated correctly.

Tracked-On: #1337
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-04-23 09:47:36 +08:00
Kaige Fu
91c1408197 HV: Reset physical core of lapic_pt vm when shutdown
The physical core of lapic_pt vm should be reset for security and
correctness when shutdown the vm.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Kaige Fu
565f3c723a HV: Clear DM set guest_flags when shutdown vm
Currently, the previous configurations about guest_flags set by DM will
not be cleared when shutdown the vm. Then it might bring issue for the
next dm-launched vm.

For example, if we create one vm with LAPIC_PASSTHROUGH flag and shutdown it.
Then the next dm-launched vm will has the LAPIC_PASSTHROUGH flag set no matter
whether we set it in DM.

This patch clears all the DM set flags when shtudown vm.

Tracked-On: #2991
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:58:20 +08:00
Zide Chen
a3207b2bc2 hv: allocate vpid based on vm_id and vcpu_id mapping
Currently vpid is not released in reset_vcpu() hence the vpid resource
could be exhausted easily if guests are re-launched.

This patch assigns vpid according to the fixed mapping of runtime vm_id
and vcpu_id to guarantee the uniqueness of vpid.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-04-22 19:57:28 +08:00
Victor Sun
9673f3dad4 HV: validate target vm in hypercall
- The target vm in most of hypercalls should be a NORMAL_VM, in some
exceptions it might be a SOS_VM, we should validate them.

- Please be aware that some hypercall might have limitation on specific
target vm like RT or SAFETY VMs, this leaves "TODO" in future;

- Unify the coding style:

	int32_t hcall_foo(vm, target_vm_id, ...)
	{
		int32_t ret = -1;
		...

		if ((is_valid_vm(target_vm) && is_normal_vm(target_vm)) {
			ret = ....
		}

		return ret;
	}

Tracked-On: #2978

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-22 19:57:03 +08:00
Cai Yulong
887d41683b hv: check vm state before creating a VM
If launch two UOS with same UUID by acrn-dm, current code path will
return same VM instance to the acrn-dm, this will crash the two UOS.

Check VM state and make sure it's in VM_STATE_INVALID state before
creating a VM.

Tracked-On: #2984
Signed-off-by: Cai Yulong <yulongc@hwtc.com.cn>
2019-04-22 15:18:03 +08:00
Zide Chen
aee9f3c666 hv: reset per cpu sbuf pointers during vcpu reset
When shutting down SOS VM, the shared sbuf is released from guest OS, but
the per cpu sbuf pointers in hypervisor keep inact. This creates a problem
that after SOS is re-launched, hypervisor could write to the shared
buffer that no longer exists.

This patch implements sbuf_reset() and call it from reset_vcpu() to
reset sbuf pointers.

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-04-19 16:20:34 +08:00
Li, Fei1
56acaacc29 hv: vlapic: add TPR below threshold implement
Add TPR below threshold implement for "Virtual-interrupt delivery" not support.
Windows will use it to delay interrupt handle.

Complete all the interrupts in IRR as long as they are higher priority than
current TPR. Once current IRR priority is less than current TPR enable TPR
threshold to IRR, so that if guest reduces the TPR threshold, it would be good
to take below TPR threshold exit and let interrupts to go thru.

Tracked-On: #1842
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-04-19 11:11:54 +08:00
Yuan Liu
b1e68453bd hv: enable vMCE from guest CPUID
Enable vMCE feature to boot windows guest.

vMCE is set in EDX from Microsoft TLFS spec, to support windows guest
vMCA and vMCE should be supported by guest CPUID.

Support MSR_IA32_MCG_CAP and MSR_IA32_MCG_STATUS reading when vMCE is enabled,
but they are not emulated yet, so return 0 directly.

Tracked-On: #1867
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-18 09:00:42 +08:00
Sainath Grandhi
824caf8ce0 hv: Remove need for init_fallback_iommu_domain and fallback_iommu_domain
In the presence of SOS, ACRN uses fallback_iommu_domain which is the same
used by SOS, to assign domain to devices during ACRN init. Also it uses
fallback_iommu_domain when DM requests ACRN to remove device from UOS domain.
This patch changes the design of assign/remove_iommu_device to avoid the
concept of fallback_iommu_domain and its setup. This way ACRN can commonly
treat pre-launched VMs bringup w.r.t. IOMMU domain creation.

Tracked-On: #2965
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-04-17 11:42:36 +08:00
Yonghua Huang
46480f6e23 hv: add new hypercall to fetch platform configurations
add new hypercall get platform information,
 such as physical CPU number.

Tracked-On: #2538
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-15 22:14:13 +08:00
Sainath Grandhi
16a2af5715 hv: Build mptable for guest if VM type is Pre-Launched
ACRN builds mptable for pre-launched VMs. It uses CONFIG_PARTITION_MODE
to compile mptable source code and related support. This patch removes
the macro and checks if the type of VM is pre-launched to build mptable.

Tracked-On: #2941
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-15 15:51:02 +08:00
Victor Sun
445999af5d HV: make vm id statically by uuid
Currently VM id of NORMAL_VM is allocated dymatically, we need to make
VM id statically for FuSa compliance.

This patch will pre-configure UUID for all VMs, then NORMAL_VM could
get its VM id/configuration from vm_configs array by indexing the UUID.

If UUID collisions is found in vm configs array, HV will refuse to
load the VM;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 13:45:32 +08:00
Victor Sun
6071234337 HV: use term of UUID
The code mixed the usage on term of UUID and GUID, now use UUID to make
code more consistent, also will use lowercase (i.e. uuid) in variable name
definition.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 13:45:32 +08:00
Li, Fei1
4557033a3a hv: vlapic: minor fix about vlapic write
1) In x2apic mode, when read ICR, we want to read a 64-bits value.
2) In x2apic mode, write self-IPI will trap out through MSR write when VID isn't enabled.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-04-12 10:11:10 +08:00
Li, Fei1
fa8fa37cdf hv: vlapic: remove vlapic_rdmsr/wrmsr
We could call vlapic API directly, remove vlapic_rdmsr/wrmsr to make things easier.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-04-12 10:11:10 +08:00
Mingqiang Chi
69627ad7b6 hv: rename io_emul.c to vmx_io.c
renamed:  arch/x86/guest/io_emul.c -> arch/x86/guest/vmx_io.c
renamed:  include/arch/x86/guest/io_emul.h
	   -> include/arch/x86/guest/vmx_io.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 10:09:26 +08:00
Mingqiang Chi
2b79c6df6a hv:move some common APIs to io_req.c
Now the io_emul.c is relates with arch,io_req.c is common,
move some APIs from io_emul.c to io_req.c as common like these APIs:
register_pio/mmio_emulation_handler
dm_emulate_pio/mmio_complete
pio_default_read/write
mmio_default_access_handler
hv_emulate_pio/mmio etc

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 10:09:26 +08:00
Mingqiang Chi
0a1c016dbb hv: move 'emul_pio[]' from strcut vm_arch to acrn_vm
Move ‘emul_pio[]/default_io_read/default_io_write’
from struct vm_arch to struct acrn_vm

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 10:09:26 +08:00
Mingqiang Chi
35c8437bbc hv:move 'fire_vhm_interrupt' to io_emul.c
-- this api is related with arch_x86, then move to x86 folder
-- rename 'set_vhm_vector' to 'set_vhm_notification_vector'
-- rename 'acrn_vhm_vector' to 'acrn_vhm_notification_vector'
-- add an API 'get_vhm_notification_vector'

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-12 10:09:26 +08:00
Sainath Grandhi
6915264740 hv: Use virtual APIC IDs for Pre-launched VMs
For Pre-launched VMs, ACRN uses mptable for reporting APIC IDs to guest OS.
In current code, ACRN uses physical LAPIC IDs for vLAPIC IDs.
This patch is to let ACRN use vCPU id for vLAPIC IDs  and also report the same
when building mptable. ACRN should still use physical LAPIC IDs for SOS
because host ACPI tables are passthru to SOS.

Tracked-On: #2934
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2019-04-11 20:04:58 +08:00
Sainath Grandhi
f22347346e hv: Remove separate interrupt routine for pre-launched VMs
As vector re-mapping is enabled for pre-launched/partition mode VMs,
there is no more need for separate interrupt routine i.e.
partition_mode_dispatch_interrupt.

Tracked-On: #2879
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-04-04 17:51:36 +08:00
Sainath Grandhi
5b795a3312 hv: add the support of vector remapping for pre-launched VMs
For pre-launched VMs MSI/MSI-x configuration writes are not intercepted by ACRN.
It is pass-thru and interrupts land in ACRN and the guest vector is injected into
the VM's vLAPIC. With this patch, ACRN intercepts MSI/MSI-x config writes and take
the code path to remap interrupt vector/APIC ID as it does for SOS/UOS.

Tracked-On: #2879
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-04-04 17:51:36 +08:00
Kaige Fu
336ed72250 HV: Minor refinement about RTVM pm MACRO and comments
This patch mainly does the following:
  - Replace prefix RT_VM_ with VIRTUAL_.
  - Remove the check of "addr != RT_VM_PM1A_CNT_ADDR" as the handler is specific for this addr.
  - Add comments about the meaning of return value.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-04 00:27:55 +08:00
Huihuang Shi
b316bf8a39 hv: fix "Else alternative missing in if."
All if . . else if constructs shall be
terminated with an else statement.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com
2019-04-03 09:20:55 +08:00
Qi Yadong
6d582f62d2 hv: trusty: minor change of coding style
Refine return value checking in functions.

Tracked-On: #2874
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-02 21:38:17 +08:00
Yan, Like
ede1459e19 hv: fix the vm pointer check before use
After using get_vm_from_vmid(), vm pointer is always not NULL. But there are still many NULL pointer checks.
This commit replaced the NULL vm pointer check with a validation check which checks the vm status.
In addition, NULL check for pointer returned by get_sos_vm() and get_vm_config() is removed.

Tracked-On: #2520
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-02 16:29:51 +08:00
Jian Jun Chen
cee45a80d9 hv: add default handlers for PIO/MMIO access
Add the default handlers for PIO and MMIO access which returns all
FFs on read and discards write. These default handlers are registered
when SOS VM or pre-launched VM is created.

v3 -> v4:
- use single layer if in hv_emulate_pio
- change the implementation of pio_default_read

v2 -> v3:
- use runtime vm type instead of CONFIG_PARTITION_MODE
- revise the pio/mmio emulation functions
- revise the pio/mmio default read functions according to MISRA C
- revise the commit message

v1 -> v2:
- add default handlers members in struct acrn_vm and add interfaces
  to register default handlers for PIO and MMIO.

Tracked-On: #2860
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-04-01 11:16:37 +08:00
Kaige Fu
382acfaf28 HV: Using INIT to kick vCPUs off when RTVM poweroff by itself
When RTVM is trying to poweroff by itself, we use INIT to
kick vCPUs off the non-root mode.

For RTVM, only if vm state equal VM_POWERING_OFF, we take action to pause
the vCPUs with INIT signal. Otherwise, we will reject the pause request.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-29 16:17:44 +08:00
Kaige Fu
2771b46b1d HV: Add one delmode parameter to make_reschedule_request
This patch makes make_reschedule_request support for kicking
off vCPU using INIT.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-29 16:17:44 +08:00
Kaige Fu
8ad5adced7 HV: Set vm state as with VM_POWERING_OFF when RTVM poweroff by itself
We set the vm state as VM_POWERING_OFF when RTVM is trying to poweroff by itself.
We will check it when trying to pause vCPUs of RTVM. Only if vm state equal to
VM_POWERING_OFF, we take action to pause the vCPUs of RTVM. Otherwise, we will
reject the pause request.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2019-03-29 16:17:44 +08:00
Kaige Fu
83d11bbff8 HV: Register S5 pio handler for dm-launched RTVM
The virtual pm port of RTVM is intercepted by HV. But the HV needs to inform the DM as well.
So we will forward the virtual S5 request to DM too

The handler in HV just set the pm state flag (VM_POWERING_OFF) which indicate that the RTVM is powering
off by itself. Meanwhile, there are data resources in VHM and DM should be released once we handle the PM
of RTVM in HV. So, return to DM to go through the entire VM destroy cycles to release the resources.
During the cycles, the DM will try to pause vm through hypercall. In the hypercall handler in HV, we will
check the pm state flag. If it is set, pause all the vCPUs of the vm. Otherwise, reject the request.

In this way, we can make sure that RTVM can only trigger its s5 by itself. All
other S5 request from external will be rejected.

Here is sequence chart of RTVM s5.

   poweroff
+-----------+              +----------+           +-----------+         +----------+
|    vBSP   |              |    vAPs  |           |    HV     |         |    DM    |
+-----+-----+              +----------+           +-----+-----+         +-----+----+
      |                         |                       |                     |
      |   Stop all other cpus   |                       |                     |
      +----------------------------+                    |                     |
      |                         |  |Disable LAPIC       |                     |
      |                         +<-+                    |                     |
      |                         |                       |                     |
      |                         +--+                    |                     |
      |                         |  |HLT in              |                     |
      | All other cpus stopped  |  |non-root mode       |                     |
      +----------------------------+                    |                     |
      |     Call ACPI method to enter s5                |                     |
      +-------------------------+---------------------> |                     |
      |                         |   Set s5 flag         |                     |
      |                         | <---------------------+                     |
      |                         |   APs paused          | Re-inject IOREQ TO DM
      |                         | +-------------------> +-------------------> +
      |                         |                       |   Pause VM          |
      |                         |   Check S5 flag:      | <-------------------+
      |                         |    - If set, pause vm |  VM paused          |
      |                         |    - If no, reject    | +-----------------> +--+
      |                         |                       |  Destroy VM         |  |Deinit works
      |                         |                       | <--------------------<-+
      |                         |                       |  VM destroyed       |
      |                         |                       | +-----------------> |
      +                         +                       +                     +

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2019-03-29 16:17:44 +08:00
Kaige Fu
1c0d7f78d0 HV: HV: make io_read_fn_t return true or false
This patch makes io_read_fn_t return true or false instead of void.
Returning true means that the handler in HV process the request completely.
Returning false means that we need to re-inject the request to DM after
processing it in HV.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
2019-03-29 16:17:44 +08:00
Kaige Fu
3b2ad67788 HV: make io_write_fn_t return true or false
This patch makes io_write_fn_t return true or false instead of void.
Returning true means that the handler in HV process the request completely.
Returning false means that we need to re-inject the request to DM after
processing it in HV.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-29 16:17:44 +08:00
Kaige Fu
ed286e3239 HV: Introduce a new API is_rt_vm
This patch checks if the GUEST_FLAG_RT is set when GUEST_FLAG_LAPIC_PASSTHROUGH is set.
If GUEST_FLAG_RT is not set while GUEST_FLAG_LAPIC_PASSTHROUGH is set, we will refuse
to boot the VM.

Meanwhile, this patch introduces a new API is_rt_vm.

Tracked-On: #2865
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-29 16:17:44 +08:00
Yonghua Huang
868778a68b hv: fix vulnerability when VM is destroyed
In hypervisor fuzzing test, hypervisor will hang
 if issuing HV_VM_SET_MEMORY_REGIONS hypercall after
 target VM is destroyed.

 this patch is to fix above vulnerability.

Tracked-On: #2849
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-03-27 09:20:12 +08:00
wenlingz
3effbb05a2 Revert "hv: vmsr: add IA32_MISC_ENABLE to msr store area"
This reverts commit 98b3d98ac5.
2019-03-26 13:59:21 +08:00
Li, Fei1
40168e73ee hv: vlapic: remove TPR set/get API
Since we always enable "Use TPR shadow", so operate on TPR will not
trigger VM exit. So remove these APIs.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-03-25 13:31:51 -07:00
Li, Fei1
4a683ed10e hv: vlapic: minor fix for update_msr_bitmap_x2apic_apicv
Shouldn't trap TPR since we always enable "Use TPR shadow"

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-25 13:31:51 -07:00
Binbin Wu
98b3d98ac5 hv: vmsr: add IA32_MISC_ENABLE to msr store area
Currently MSR IA32_MISC_ENABLE is passthrough to guest.
However, guest may change the value of this MSR, which will cause issue in hypervisor.
This patch uses VMX MSR store area to isolate the MSR IA32_MISC_ENABLE between guest and host.

TODO:
Some bits of the MSR IA32_MISC_ENABLE is not just per core, but per package.
So need to check if need to prevent guest from setting or clearing these bits that may affect other cores.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-03-22 13:32:01 +08:00
Binbin Wu
273381b372 hv: vmsr: rename msr_num to msr_index in struct msr_store_entry
Rename the field msr_num to msr_index, which is more accurate,
in struct msr_store_entry.

Tracked-On: #2834
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-03-22 13:32:01 +08:00
Yan, Like
93ed2af165 hv: passthru TSC_ADJUST to VM with lapic pt
Linux access TSC_ADJUST to verify it has not tampered every time when enter idle.
So for RTVM running rt-linux, the access will cause vm exit which affect real-time performance.

This commit pass through TSC_ADJUST to VM with lapic_pt, to avoid TSC_ADJUST caused vm_exit.
For other VMs, TSC_ADJUST msr access is still trapped and emulated.

Tracked-On: #2813
Signed-off-by: Yan, Like <like.yan@intel.com>
2019-03-20 13:35:28 +08:00
Binbin Wu
f32b59d73d hv: disable mpx capability for guest
This patch hide Memory Protection Extention (MPX) capability from guest.

- vCPUID change:
  Clear cpuid.07H.0.ebx[14]
  Clear cpuid.0DH.0.eax[4:3]
- vMSR change:
  Add MSR_IA32_BNDCFGS to un-supported MSR array.
- XCR0[4:3] is not allowed to set by guest.

Tracked-On: #2821
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-20 13:07:31 +08:00
Zide Chen
5398c901f6 hv: remove CONFIG_PARTITION_MODE for pre-launched VM vE820 creation
Preparing for hybrid mode:

- create vE820 for pre-launched VMs and do other init code when the
  vm_config->type is PRE_LAUNCHED_VM.
- create ve820.c for each board because without wrapping by
  CONFIG_PARTITION_MODE, ve820_entry[] needs to be visible even when
  compiling target boards that haven't enabled pre-launched VMs.
- remove create_prelaunched_vm_e820() from vm.c and implement board
  specific function for each $(CONFIG_BOARD)/ve820.c. The reasons being:
  - don't need to define ve820_entry[32] for those boards that don't
    support pre-launched VMs.
  - more importantly, this makes it much easier to create different per-VM
    vE820 when it's needed.

Tracked-On: #2291
Signed-off-by: Zide Chen <zide.chen@intel.com>
2019-03-19 14:28:43 +08:00
Victor Sun
ca6e341147 HV: add vrtc for sharing mode
Previously vrtc is for partition mode only, now enable it for sharing mode;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-19 13:45:32 +08:00
Qi Yadong
1b79f28efe hv: update CR0/CR4 on demand in run_vcpu()
Suppose run_ctx.cr0/cr4 are correct when do world switching, so call
vcpu_set_cr0/cr4() to update cr0/cr4 directly before resume to guest.
This design is only for trusty world switching.

Tracked-On: #2773
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-19 09:57:08 +08:00
dongshen
19c5342506 HV: remove vdev ops for sharing mode
Remove vdev ops for sharing mode, directly call the corresponding functions
instead of calling the ops callbacks (indirectly)

Remove alloc_pci_vdev() and merge its code into init_vdev_for_pdev() to simplify code

Remove @pre for local variables

Change the return value from int32_t to void to comply with misra c and
add ASSERT in the functions (if necessary) to verify the assumptions for debug build:
 vmsi_init
 vmsix_init
 vmsi_deinit
 vmsix_deinit

Add @pre for vmsix_init_helper and make it a void function, use ASSERT to verify
the assumption for debug build.

Add ASSERT in get_sos_vm

Tracked-On: #2534
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-18 10:08:10 +08:00
Li, Fei1
79cfb1cf58 hv: vmconfig: format guest flag with prefix GUEST_FLAG_
To make the code more readable.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-16 17:14:12 +08:00
Li, Fei1
c018b853e9 hv: vmtrr: hide mtrr if hide_mtrr is true
Now we only configure "hide MTRR" explicitly to false for SOS. For other VMs,
we don't configure it which means hide_mtrr is false by default.
And remove global config MTRR_ENABLED

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-16 17:14:12 +08:00
Qi Yadong
ff41c008ce hv: trusty: refine control registers switching method
Remove vmx_cr0/vmx_cr4 from ext_context structure, they are duplicated
with cr0/cr4 fields in run_context.
Switch cr0/cr4 of run_context structure on demand when do world switch.

Remove vmx_cr0_read_shadow/vmx_cr4_read_shadow from ext_context structure.
These fields should be same for both normal world and secure world.

Tracked-On: #2773
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-15 10:08:25 +08:00
Zide Chen
518a82d80b hv: cleanup some hva/hpa conversion code
The init page tables installed in either cpu_primary.S or trampoline.S
are 1:1 mapping and won't be changed in the future.

The 'actual' hypervisor page table installed in enable_paging() is 1:1
mapping currently but it could be changed in the future. Both hva2hpa() and
hpa2hva() are implemented based on these page tables and can't be used
when the init page tables take effect.

This patch does the following cleanup:

- remove all hva2hpa()/hpa2hva() before calling enable_paging()
- get_hv_image_base() returns HVA, not HPA. So add hva2hpa() for all cases
  that are called afte enable_paging().

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
2019-03-15 09:03:14 +08:00
Qi Yadong
95d1e40283 hv: refactor seed management
New component to maintain seed retrieval and derivation: seed.

1. Retrieve seed from bootloader in Hypervisor's boot stage.
2. Derive virtual seed for Guest/Trusty if need.

Tracked-On: #2724
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Reviewed-by: Zhu Bing <bing.zhu@intel.com>
2019-03-14 10:38:17 +08:00
Arindam Roy
3158c851ae HV: Modularize boot folder
In order to remove the usage of hypervisor.h,
modularize the boot folder.
Current changes include modifications to remove
usage of acrn_vm structure pointer, from some of
the call, and remove calls to hypervisor.h,
as and when deemed fit.

Removed hva2gpa, as this was not used anywhere else
after the changes.

Tracked-On: #2694
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-14 09:05:53 +08:00
Jason Chen CJ
286731d9d1 hv:move instr_emul_ctxt instance to struct vcpu
move instr_emul_ctxt instance from struct per_cpu_region
to struct vcpu, and rename it from g_inst_ctxt to inst_ctxt

Tracked-On: #1842
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-13 14:04:20 +08:00
Mingqiang Chi
5331b39520 hv:remove 'cpu_mode' from struct vm_guest_paging
now the 'cpu_mode' is unused in struct vm_guest_paging,
and there is the  same variable in struct acrn_vcpu_arch

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-13 14:04:20 +08:00
Tw
9b24620e16 hv: merge SBL and UEFI related stuff under boot
This patch mainly unifies init_vm_boot_info's implementation between SBL and
UEFI.

Tracked-On: #2708
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-13 10:26:55 +08:00
Li, Fei1
f769f7457b hv: vlapic: add combined constraint for APICv
Add two functions to combine constraint for APICv:
is_apicv_basic_feature_supported: check the physical platform whether support
"Use TPR shadow", "Virtualize APIC accesses" and "Virtualize x2APIC mode"
is_apicv_advanced_feature_supported: check the physical platform whether support
"APIC-register virtualization", "Virtual-interrupt delivery" and
"Process posted interrupts".

If the physical platform only support APICv basic feature, enable "Use TPR shadow"
and "Virtualize APIC accesses" for xAPIC mode; enable "Use TPR shadow" and
"Virtualize x2APIC mode" for x2APIC. Otherwise, if the physical platform support
APICv advanced feature, enable APICv feature for xAPIC mode and x2APIC mode.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-12 20:37:06 +08:00
Kaige Fu
2b74e1a91e HV: PAE: Add stac()/clac() in local_gva2gpa_pae
Accessing memory of guest will cause page fault when SMAP is enabled.
This patch stac()/clac() correspondingly to get rid of this situation.

Tracked-On: #2713
Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-12 09:28:35 +08:00
Sainath Grandhi
137892fdd5 hv: Remove multiple definitions for dmar translation structures
Except for few translation structures in x86 IOMMU, all translation
structures are 128-bit. All the translation structures used by ACRN
are 128 bit. So removed multiple definitions and defined a struct
that accomodates 128 bit entries.

Tracked-On: #2668
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-03-08 15:23:20 +08:00
Zide Chen
bf1aa5c134 hv: destroy IOMMU domain after vpci_cleanup()
In partition mode, unassign_iommu_device() is called from vpci_cleanup(),
so when shutdown_vm() is called, unassign_iommu_device() could fail because
of "domain id mismatch" and DMAR is not cleared.

Also move destroy_ept() after the call to destroy_iommu_domain().

Tracked-On: #2700
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-08 13:20:11 +08:00
Victor Sun
649406b049 HV: refine location of platform_acpi_info header
platform_acpi_info.h should be BOARD specific so move the header file
to configs/$(CONFIG_BOARD)/ folder.

So the target acpi info file detect process is:

Compiler search for $(CONFIG_BOARD)_acpi_info.h under
hypervisor/arch/x86/$(CONFIG_BOARD)/ first (the file is supposed to be
generated by offline tool so it is not included in original source), if
found, then the file is the target acpi info file. If not and at the
same time the ENFORCE_VALIDATED_ACPI_INFO Kconfig was set, the compiler
will stop and hint user to add target acpi info file by offline tool.
If ENFORCE_VALIDATED_ACPI_INFO was unset, then compiler will continue to
search for platform_acpi_info.h as target acpi info file under
hypervisor/arch/x86/$(CONFIG_BOARD) folder (with this file we could bypass
ENFORCE_VALIDATED_ACPI_INFO check and benifit for development). If this
file is not exist, then hypervisor/arch/x86/configs/platform_acpi_info.h
will be included as final target acpi info.

The process should work for UEFI path also, with a valid platform acpi
info file, S3/S5 should work on UEFI platform.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-08 10:34:14 +08:00
Mingqiang Chi
55f52978db hv:move several tsc APIs to timer.c
-- change 'tsc_khz' to static
-- move these APIs from rtl.h to timer.c
   us_to_ticks()
   ticks_to_us()
   ticks_to_ms()
   rdtsc()

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-07 20:23:22 +08:00
Yan, Like
741501c2e3 hv: refine vlapic_calc_dest()
This commit extracts the common logic of vlapic_calc_dest() and vlapic_calc_dest_lapic_pt()
to static inline functions, in order to make vlapic_calc_dest() clean and easy to read.

Tracked-On: #1842
Signed-off-by: Yan, Like <like.yan@intel.com>
2019-03-06 11:43:51 +08:00
Li, Fei1
ca3d4fca55 hv: vlapic: move LVT IRQ vector check to vlapic_fire_lvt
We could simple the vector check for LVT IRQ by move this check to
vlapic_fire_lvt when the IRQ is fixed mode.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-05 13:33:36 +08:00
Li, Fei1
473d31c073 hv: vlapic: add vector check for x2apic SELF IPI
Set when the local APIC detects an illegal vector (one in the range 0 to 15)
in the message that it is sending. This occurs as the result of a write to the
ICR (in both xAPIC and x2APIC modes) or to SELF IPI register (x2APIC mode only)
with an illegal vector.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-05 13:33:36 +08:00
Li, Fei1
e5d3a49894 hv: vlapic: call vlapic_accept_intr directly in vlapic_set_error
LVT ERROR is an edge and fixed mode interrupt. We could call vlapic_accept_intr
to fire it directly. Otherwise, if LVT ERR vector is invalid, an invalid
interrupt will be accepted in IRR.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-05 13:33:36 +08:00
Zide Chen
2b35c07857 hv: do EPT mapping only for physical memory backed GPA on pre-launched VMs
Currently for pre-launched VMs, HV intends to do EPT mapping for all GPA
space, which implies that it wastes HPA to back PCI hole and other vE820
entries that are not backed by physical memory.

This patch solves this issue and fixes ve820 entries whose length is not
aligned to 4K, and changes the lowmem entry's start GPA from 1MB to 2MB.

Tracked-On: #2587
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-03-05 10:05:24 +08:00
Shiqing Gao
da14c96135 hv: simplify get_primary_vcpu and vcpu_from_vid
This patch simplifies `get_primary_vcpu` and `vcpu_from_vid`.
The target_vcpu could be get from the index directly.

Tracked-On: #1842
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-04 13:45:02 +08:00
Li, Fei1
3d0d8609cc hv: vlapic: correct wrong use of vector
Correct wrong use of vector where lvt_index should be used.

Tracked-On: #1842
Signed-off-by: Min He <min.he@intel.com>
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-03-04 13:44:15 +08:00
Xinyun Liu
0943a836bd [hv] set ECX.bit31 to indicate the presence of a hypervisor
ECS.bit31 is not used and always return 0 in SDM Vol.2A 3-195. It's a
standard way to indicate whether there is a hypervisor.

Tracked-On: #2490
Ref: https://lwn.net/Articles/301888/
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-03-04 13:43:48 +08:00
Victor Sun
0d90515bf6 HV: refine is_lapic_pt
- Do not refer vm_configs[] directly in vm module;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-01 10:32:49 +08:00
Victor Sun
1bb15c64a6 HV: modularization vm config code
- move sanitize_vm_config() from vm.c to vm_config.c;

- move get_vm_config() from vm.h to vm_config.h;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-03-01 10:32:49 +08:00
yuhong.tao@intel.com
3b2784ec1b HV: CAT: support config CAT from acrn_vm_config
When CAT is supported, UOS can setup acrn_vm_config.clos, to use CAT
feature. Eg.,

struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
    {
        .guest_flags |= CLOS_REQUIRED,
        .clos = 1,
    },
};

sanitize_vm_config() will check if CAT is supported and
vm_configs.clos is valid.

Tracked-On: #2462
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-28 11:22:29 +08:00
Li, Fei1
2e60adef7c hv: vmcs: simplify update EOI-exit bitmap
1) The previous implementaion will recalculate the whole EOI-exit bitmap for
each RTE once the destination, trigger mode, delivery mode or vector of a RTE
has changed and update the EOI-exit bitmap for each vcpu of the VM.
In this patch, only set the corresponding bit of EOI-exit bitmap for
a vcpu when a level triggered interrupt has accepted in IRR or clear the
corresponding bit of EOI-exit bitmap for a vcpu when a dege triggered interrupt
has accepted in IRR which means only update a bit of EOI-exit bitmap in a vcpu
when updating TMR.
2) Rename set eoi_exit related API to set eoi_exit_bitmap.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-27 15:28:37 +08:00
Mingqiang Chi
511d4c158b hv:cleanup console.h
--move several uart API declarations from console.h to uart16550.h
 --move several shell API declarations from console.h to shell.h
 --add dbg_cmd.h, move 'handle_dbg_cmd' declaration from console.h
   to dbg_cmd.h
 --move debug/uart16550.h to include/debug/uart16550.h since some
   uart APIs will be called by external files

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>

	modified:   arch/x86/guest/vm.c
	modified:   arch/x86/init.c
	modified:   bsp/uefi/cmdline.c
	modified:   debug/console.c
	modified:   debug/dbg_cmd.c
	modified:   debug/uart16550.c
	modified:   debug/vuart.c
	modified:   hw/pci.c
	modified:   include/arch/x86/multiboot.h
	modified:   include/debug/console.h
	new file:   include/debug/dbg_cmd.h
	new file:   include/debug/shell.h
	renamed:    debug/uart16550.h -> include/debug/uart16550.h
2019-02-27 11:12:48 +08:00
Zide Chen
94e1227559 hv: code style fix for partition mode specific code
There are still some misra-c violations when CONFIG_PARTITION_MODE is defined.

arch/x86/configs:
- remove the unused macro: PRE_LAUNCH_VM_NUM
- pt_dev.c: VMx_CONFIG_PCI_PTDEV_NUM has been defined in partition_config.h,
  should not hard code them again in pt_dev.c.
- ve820.c: use "UL" suffix instead of "U" for 64 bits variables.

vmid is uint16_t in ACRN, so vuart_vmid should be uint16_t as well.

Fix another few other miscellaneous misra-c violations.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-26 14:00:32 +08:00
Li, Fei1
987ddafa6b hv: vlapic: refine apicv_post_intr to internal function
Rename vlapic_post_intr to apicv_post_intr and move it to internal function
since it's only used in vlaic.c.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-02-25 14:17:27 +08:00
Li, Fei1
5dd6e79fe7 hv: vlapic: refine vlapic_enabled to internal function
Since it's only used in vlaic.c

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-25 14:17:27 +08:00
Li, Fei1
e218efd576 hv: vm: move vm_active_cpus to vm.h
Move vm_active_cpus from vlapic.c to vm.h since it's vm related
not vlapic related.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-25 14:17:27 +08:00
Mingqiang Chi
ac7a8a7249 hv:merge MACROs E820_MAX_ENTRIES and NUM_E820_ENTRIES
merge E820_MAX_ENTRIES and NUM_E820_ENTRIES
to E820_MAX_ENTRIES.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-02-22 13:14:36 +08:00
Binbin Wu
02ae775bfa hv: pae: fix a issue of loading pdptrs when handle cr4
PDPTE registers should be loaded in PAE paging mode.
However, current code load PDPTE registers in long mode.

Tracked-On: #2561
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-21 18:54:22 +08:00
Binbin Wu
253852419a hv: pae: fix bug when calculate PDPT address
There are two bugs related to PDPT address calculation for PAE mode.

1. Current code doesn't ignore the "Ignored" fileds when load pdpt registers.
Mask the "Ignored" fileds according to SDM Figure 4-7 Vol3.

2. Current code only ignores 4bits instead of 5bits in low "Ignored" filed when
calculate PDPT address in PAE mode for guest memory address translation.

Tracked-On: #2561
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-21 18:54:22 +08:00
Mingqiang Chi
b24a8a0f59 hv:cleanup header file for guest folder
cleanup arch/x86/guest, only include some necessary
header files, doesn't include hypervisor.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
	modified:   arch/x86/guest/assign.c
	modified:   arch/x86/guest/ept.c
	modified:   arch/x86/guest/guest_memory.c
	modified:   arch/x86/guest/instr_emul.c
	modified:   arch/x86/guest/io_emul.c
	modified:   arch/x86/guest/pm.c
	modified:   arch/x86/guest/trusty.c
	modified:   arch/x86/guest/ucode.c
	modified:   arch/x86/guest/vcpu.c
	modified:   arch/x86/guest/vcpuid.c
	modified:   arch/x86/guest/virq.c
	modified:   arch/x86/guest/virtual_cr.c
	modified:   arch/x86/guest/vlapic.c
	modified:   arch/x86/guest/vm.c
	modified:   arch/x86/guest/vmcall.c
	modified:   arch/x86/guest/vmcs.c
	modified:   arch/x86/guest/vmexit.c
	modified:   arch/x86/guest/vmsr.c
	modified:   arch/x86/guest/vmtrr.c
	modified:   arch/x86/pm.c
	modified:   include/arch/x86/guest/assign.h
	modified:   include/arch/x86/guest/ept.h
	modified:   include/arch/x86/guest/guest_memory.h
	modified:   include/arch/x86/guest/instr_emul.h
	modified:   include/arch/x86/guest/io_emul.h
	modified:   include/arch/x86/guest/trusty.h
	modified:   include/arch/x86/guest/vcpu.h
	modified:   include/arch/x86/guest/vmcs.h
	modified:   include/arch/x86/io_req.h
	modified:   include/arch/x86/irq.h
	modified:   include/arch/x86/lapic.h
	modified:   include/arch/x86/mmu.h
	modified:   include/arch/x86/pgtable.h
	modified:   include/common/ptdev.h
	modified:   include/debug/console.h
2019-02-21 10:38:30 +08:00
Mingqiang Chi
75f6cab554 hv:cleanup header file for per_cpu.h
remove hypervisor.h from per_cpu.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-02-21 10:38:30 +08:00
Mingqiang Chi
04c30fb380 hv:move 2 APIs from hypervisor.h to guest_memory.c
move gva2hva() & hva2gpa() to guest_memory.c,
we will remove hypervisor.h in the future.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-02-21 10:38:30 +08:00
Binbin Wu
827fffedda hv: exception: fault type exception should set resume flag in rflags
According to SDM 17.3.1.1, for any fault-class exception except a
debug exception generated in response to an instruction breakpoint,
the value pushed for RF is 1.

This patch set Resume Flag for fault class exceptions.

Tracked-On: #2405
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-20 13:21:45 +08:00
Peter Fang
caab595ed4 hv: vlapic: properly initialize DCR
DCR is initialized to 0 which means divisor shift is 1. Currently, both
are initialized to 0 which result in incorrect APIC timer counts if the
vLAPIC's DCR is never programmed.

This bug was exposed by OVMF because OVMF does not program DCR during
LAPIC initialization.

Tracked-On: #2543
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-19 09:43:55 +08:00
Binbin Wu
2fd6e119ca hv: vmcall: hv should not change guest RAX vmcall is undefined
HV passes the return value of vmcall by register RAX unconditionally.
However, if the vmcall is undefined for a guest, RAX value of guest vcpu
should not be changed.

According to SDM Vol. 3C 30-9, VMCALL is allowed from any CPL in guest.
VMCALL is NOT allowed from  CPL > 0 in vmx root mode.
ACRN hypervisor doesn't call VMCALL in vmx root mode, though.

In current code, ACRN also deny VMCALL from CPL > 0 in guest.
So for this case, #GP will not be injected, instead, modify the RAX to
notify the return value.

Tracked-On: #2405
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-18 11:56:42 +08:00
Binbin Wu
3e0c0550a4 hv: vmcall: unsupported vmcall from UOS should be handle first.
ACRN HV hide VMX capability from guest. Only vmcall from SOS or some
specific vmcall from UOS are allowed.
Unsupported vmcall from UOS should be considered a "not in VMX operation" case,
and should be handled first according to SDM Vol. 3C 30-9.

Tracked-On: #2405
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-18 11:56:42 +08:00
Arindam Roy
f660d9cf80 HV: Remove snoopy_mem from iommu
Removed the remaining reference of acrn vm from
inside of vtd.c.
Removed usage of snoopy_mem, and added code to achieve
the same using iommu_snoop.
Initialize iommu_snoop to true in create deault iommu.

Tracked-On: #2496
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
2019-02-14 10:16:21 +08:00
Arindam Roy
de8d85753e HV: Modularize vtd.c to remove acrn_vm usage
This patch is a modified one. It removes the usage
of acrn_vm struct from inside vtd.c.
It also puts struct iommu_domain inside vtd.h,
from vtd.c.
It modifies the signature of init_iommu_domain
in order to remove dependency on acrn_vm from
inside vtd.c.
Incorporated comments from Jason and Eddie.
Changed the name of sos_vm_domain to
fallback_iommu_domain
Removed any reference of sos_vm from vtd.[c|h]
files, including comments.

Tracked-On: #2496
Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-02-06 08:53:46 +08:00
Mingqiang Chi
229fbdd81d hv:cleanup header file for vcpu.c & vcpu.h
For vcpu.c and vcpu.h,only include some necessary
header files, doesn't include hypervisor.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-03 13:50:42 +08:00
Mingqiang Chi
3d878a9123 hv:cleanup header file for vm.c & vm.h
-- now hypervisor.h is the universal set of header file,
   this patch doesn't include hypervisor.h, only include
   some necessary header files for vm.c and vm.h
-- move 'struct vcpuid_entry' from vm.h to vcpuid.h
-- remove dead code 'enum vm_privilege_level'
-- move 'enum vpic_wire_mode' from vm.h to vpic.h

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-03 13:50:42 +08:00
Shiqing Gao
b5f4757650 hv: refine guest.h
- move functions related vmexit from `guest.h` to `vmexit.h`
- move functions related msr from `guest.h` to `msr.h`
- move functions related vm_sw_loader from `guest.h` to `vm.h`
- move function `vmx_vmrun` from `guest.h` to `vcpu.h`
- move MACROs related to vcpu from `guest.h` to `vcpu.h`
- move MACRO `E820_MAX_ENTRIES` from `guest.h` to `e820.h`
- move MACROs related to irq from `guest.h` to `irq.h`
- rename `guest.h` to `guest_memory.h`

Tracked-On: #2503
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-03 13:00:42 +08:00
Mingqiang Chi
af1e5d5742 hv:remove several redundancy variables related memory
Remove redundancy code since they are not used now.
-- remove 'max_ram_blk_base' & 'max_ram_blk_size' in
   struct e820_mem_params
-- remove 'gpa_lowtop' in struct vm_hw_info
-- remove MACRO 'UOS_DEFAULT_START_ADDR'

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-02 22:59:34 +08:00
Victor Sun
0f745b4d15 HV: e820 refinement
- add e820 info in struct acrn_vm;

- rename rebuild_sos_vm_e820() to create_sos_vm_e820();

- add create_prelaunched_vm_e820() for partition mode;

- rename create_e820_table() to create_zeropage_e820() and merge for
  both sharing mode and partition mode;

- move create_xxx_vm_e820() to vm.c;

- move create_zeropage_e820() to vm_load.c;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-02 11:53:37 +08:00
Li, Fei1
ce19dd423e hv: vlapic: make vlapic deliver interrupt related functions more readable
Rename vlapic_deliver_intr to vlapic_receive_intr: ioapic/msi device
deliver an interrupt to lapic.
Rename vlapic_pending_intr to vlapic_find_deliverable_intr: find a
deliverable interrupt which pending in irr and its priority large than ppr.
Rename vlapic_intr_accepted to vlapic_get_deliverable_intr: get the deliverable
interrupt from irr and set it in isr (which also raise ppr update)

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-02-02 09:31:49 +08:00
Yonghua Huang
123c2b5fa4 hv: rename MACROs 'VMX_CRx_MASK"
CRx 'guest/host mask' is widely used when talking
  about CR0/CR4 virtualization in SDM spec,
  rename them to 'VMX_CRx_GUEST_HOST_MASK'.

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-01 16:49:39 +08:00
Shiqing Gao
49623fc073 hv: refine guest.c
- move `vcpumask2pcpumask` from `guest.c` to `vcpu.c`
- move `prepare_sos_vm_memmap` from `guest.c` to `vm.c`
- rename `guest.c` to `guest_memory.c`

Tracked-On: #2484
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-02-01 16:30:55 +08:00
Sainath Grandhi
970821462b hv: Use Interrupt Remapping format for programming interrupt sources
When a corresponding IOMMU is found for the device, this patch adds
support to program Interrupt Remapping hardware RTEs and the original
interrupt sources (MSI or IOAPIC) with IR format.

Tracked-On: #2426
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
2019-02-01 15:54:55 +08:00
Yonghua Huang
0f5c6e2c18 HV: fix address type violation for MSR_LOAD/STORE
According to SDM 24.7.2, these two MSRs should be
  configured with physical address.

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-31 22:23:41 +08:00
Yan, Like
17f4cd18a3 hv: fix dest of IPI for CPU with lapic_pt
With lapic_pt based on vlapic, guest always see vitual apic_id.
We need to convert the virtual apic_id from guest to physical apic_id
before writing ICR.

SMP for VM with lapic_pt is supported with this fix.

Tracked-On: #2351
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-31 18:18:44 +08:00
Tw
39ffd29aa3 schedule: add magic number at the bottom of schedule stack
Add this magic number to prevent potential overflow when dumping
host stack.

Tracked-On: #2455
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-31 11:28:29 +08:00
Li, Fei1
2474c60141 hv: replace improper use of panic with ASSERT
Panic should only be used when system booting. Once the system boot done,
it could never be used. While ASSERT could be used in some situations, such
as, there are some pre-assumption for some code, using ASSERT here for debug.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@inte.com>
2019-01-31 11:09:39 +08:00
Mingqiang Chi
7da9161d7d hv:no need to use lock for the bit operations of local variable
Use bitmap_set_nolock/bitmap_clear_nolock instead of
bitmap_set_lock/bitmap_clear_lock for the local variable.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-31 08:25:33 +08:00
Mingqiang Chi
2b2dbe43d7 hv:move some files to guest folder
move the following files to guest folder:
renamed:    arch/x86/assign.c -> arch/x86/guest/assign.c
renamed:    arch/x86/ept.c -> arch/x86/guest/ept.c
renamed:    arch/x86/io_emul.c -> arch/x86/guest/io_emul.c
renamed:    arch/x86/trusty.c -> arch/x86/guest/trusty.c
renamed:    arch/x86/virq.c -> arch/x86/guest/virq.c
renamed:    arch/x86/virtual_cr.c -> arch/x86/guest/virtual_cr.c
renamed:    arch/x86/vmcs.c -> arch/x86/guest/vmcs.c
renamed:    arch/x86/vmexit.c -> arch/x86/guest/vmexit.c
renamed:    arch/x86/vmx_asm.S -> arch/x86/guest/vmx_asm.S
renamed:    include/arch/x86/assign.h ->
	    include/arch/x86/guest/assign.h
renamed:    include/arch/x86/io_emul.h ->
	    include/arch/x86/guest/io_emul.h
renamed:    include/arch/x86/trusty.h ->
            include/arch/x86/guest/trusty.h
renamed:    include/arch/x86/virtual_cr.h ->
            include/arch/x86/guest/virtual_cr.h
renamed:    include/arch/x86/vmcs.h -> include/arch/x86/guest/vmcs.h
renamed:    include/arch/x86/vmexit.h ->
            include/arch/x86/guest/vmexit.h

After these files movement, all the files in arch/x86 are native
hardware related, and all the files in arch/x86/guest are
virtualiztion related.

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-01-30 20:43:04 +08:00
Minggui Cao
723ff1f4ee HV: modularization improve UEFI macro control code
1. in UEFI bsp code, not need UEFI macro; it is controlled in makefile.
2. in vm/acpi/interrupt code, unify the API name for SBL & UEFI.
3. remove unnecessary header including and unused code.

Tracked-On: #1842
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-01-30 16:11:39 +08:00
Binbin Wu
c6d2908f70 hv: vmexit: add handler for vmexit not supported for guest
Acrn doesn't support nested virtualization, so vmx operations should be
undefined opcode for guest.
Current code handle vmx operations with unhandled_vmexit_handler.
According to the spec, if guest execute vmx operation instruction, a #UD
exception should be inject.
This patch inject a #UD exception when guest execute vmx operation instruction.

Tracked-On: #2405
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-29 13:13:38 +08:00
Mingqiang Chi
cc2c0c3a9a hv:Move several inline APIs from vm.h to *.c
-- move vm_pic() from vm.h to vpic.c since it is
   only used in vpic.c
-- move vm_ioapic() from vm.h to vioapic.c
   change vioapic_reset(struct acrn_vioapic *vioapic) -->
          vioapic_reset(struct acrn_vm *vm)
   then vm_vioapic() is only used in vioapic.c
-- move vm_vuart() from vm.h to vuart.c,
   now this api is used in vuart.c and shell.c

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-01-29 11:29:59 +08:00
Yan, Like
b038ade21c hv: fix misra-c violations in reused partition mode functions
Fixed violations in vlapic_x2apic_pt_icr_access()
- Procedure has more than one exit point;
- Value is not of appropriate type;
- Narrower init conversion without cast;
- Implicit conversion: actual to formal param (MR)
Fixed violation in switch_apicv_mode_x2apic()
- No space between if, while, for and expresn.

Tracked-On: #861
Signed-off-by: Yan, Like <like.yan@intel.com>
2019-01-29 09:50:07 +08:00
Yan, Like
e2cecfb560 hv: send IPI instead of irq injection to notify vcpu with lapic pt
For VM with local apic pt for realtime scenatios, we support virtio device with PMD backend.
But we still need to inject MSI to notify the front-end, to avoid changing the front-end drivers.

Since the lapic is passed through, irq injection to vlapic won't work.
This commit fix it by sending IPI with vector need to inject.

Tracked-On: #2351
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-28 19:47:33 +08:00
Yan, Like
a073ebeeca hv: extend lapic pass-through for DM launched VM
This commit extend lapic pass-through for DM launched VM, generally for hard RT scenarios.
Similar to the partition mode, the vlapic is working under the xapic mode at first, only
when x2apic mode is enabled, lapic is passed through, because the physical LAPICs are
under x2apic mode.

Main changes includes:
- add is_lapic_pt() to check if a vm is created with lapic pt or not, to combine
  codes of partition mode and DM launched vm with lapic passthrough, including:
  - reuse the irq delievery function and rename it to dispatch_interrupt_lapic_pt();
  - reuse switch_apicv_mode_x2apic();
  - reuse ICR handling codes to avoid malicious IPI;
- intercept ICR/APICID/LDR msr access when lapic_pt;
- for vm with lapic passthrough, irq is always disabled under root mode.

Tracked-On: #2351
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-28 19:47:33 +08:00
Yonghua Huang
c853eb4bc2 hv: remove redundant code for virtual interrupt injection
- vlapic_pending_intr() is called only for case no
    APICv/VID(Virtual Interrupt Delivery) feature support,
    in this case, there is no need to test VID case.

  - remove 'apicv_pending_intr()' function.

Tracked-On: #2427
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-28 11:36:17 +08:00
Sainath Grandhi
6d5456a0df hv: Bit Representation for IOAPIC RTE
As we enable Interrupt Remapping, bit positions in IOAPIC RTEs
have a different syntax for programming. ACRN should handle original
format for vIOAPIC as well IR representation for physical IOAPIC.
This patch adds bit granularity IOAPIC RTE.

Tracked-On: #2407
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2019-01-26 23:25:34 +08:00
Sainath Grandhi
7d57eb056e hv: Add bit representation for MSI addr and data
As we enable Interrupt Remapping, bit positions in MSI address and
data registers have a different syntax for programming. This patch adds
bit granularity for MSI address and data structs.

Tracked-On: #2407
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2019-01-26 23:25:34 +08:00
Victor Sun
66e0023029 HV: sanitize vm config
Add a API to sanitize vm_configs[] array, in this API, we will do sanity
check for VM configurations and refill some fields in vm_configs[]. If
sanity check is failed, the HV would reject to boot.

About pcpu_bitmap of SOS_VM:

We should not hard code pcpu_bitmap for SOS_VM, this is not convenient for
unconfigured boards. The pcpu_bitmap follows a very simple rule:

All physical CPUs except ocuppied by Pre-launched VMs are all belong to
SOS_VM. In this way, the pcpu_bitmap of a SOS_VM is decided by pcpu_bitmap
status in PRE_LAUNCHED_VMs.

To get the correct pcpu_bitmap of SOS_VM, We need to setup another rule, that
the vm_configs[] array should follow the order of PRE_LAUNCHED_VM - SOS_VM
strictly.

With this patch enabled, the pcpu_bitmap field of sos vm config is not needed
to configure;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-25 21:30:49 +08:00
Yonghua Huang
ee066a7f1c hv: fix possible buffer overflow in 'vcpu_set_eoi_exit()'
'vector' should be no greater than 0xff,else
 'eoi_exit_bitmap[]' will overflow.

Tracked-On: #1252
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-25 11:26:45 +08:00
Yonghua Huang
88eeae3f1f hv: remove unused fields in 'struct acrn_vcpu'
below fields are defined but not used.
- sync, pause_cnt & dbg_req_state.

Tracked-On: #861
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-25 11:26:33 +08:00
Victor Sun
d0eb83aa0c HV: move Kconfig IOREQ_POLLING to acrn vm config
Previously I/O emulation completion mode mode was configured in Kconfig:

	config IOREQ_NOTIFICATION
	       bool "Notification mode"
	       help
	         When I/O request is completed, SOS will mark the completion status and
	         notify hypervisor via hypercall. Hypervisor will finish the post work
	         when notification is received.

	config IOREQ_POLLING
	       bool "Polling mode"
	       help
	         When I/O request is completed, SOS will only mark completion status
	         without notifying hypervisor. Hypervisor will poll the completion
	         status and finish the post work.

Now move this configuration to guest_flags of acrn_vm_config struct.

	if ((vm_config->guest_flags & IO_COMPLETION_POLLING) != 0U) {
		I/O with polling;
	} else {
		I/O with notification;
	}

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-25 10:24:18 +08:00
Jason Chen CJ
fb41ea5cfb io_emul: remove pending_pre_work
Now we do not need pending_pre_work anymore, as we can make sure IO request
VCPU resume from where it paused.

Now only three fixed points will try to do schedule:
- vcpu_thread: before vm entry, will check reschedule flag and to it if needed
- default_idle: loop check reschedule flag to see if need switch out
- io request: if IO REQ need DM's handle, it will schedule out

Tracked-On: #2394
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2019-01-23 16:21:17 +08:00
Jason Chen CJ
4fc54f952e schedule: add full context switch support
this patch added full context switch support for scheduling, it make sure
each VCPU has its own stack, and added host_sp field in struct sched_object
to record host stack pointer for each switch out object.

Arch related function arch_switch_to is added for context switch.

To benefit debugging, a name[] field is also added into struct sched_object.

Tracked-On: #2394
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2019-01-23 16:21:17 +08:00
Shiqing Gao
5e94788689 hv: vlapic: remove calcvdest
- remove `calcvdest` and use `vlapic_calcdest` directly

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-23 13:43:09 +08:00
Minggui Cao
173b534b05 HV: modularization cleanup instr_emul header file
separate the private macro/structure/functions, which are just used
in instr_emul.c;

and move instr_emul.h to public include path.

Tracked-On: #1842
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-22 10:50:30 +08:00
Victor Sun
18dbdfd5d7 HV: replace lapic_pt with guest flag in vm_config
The member of lapic_pt in acrn_vm_config will be replaced by
guest_flag of LAPIC_PASSTHROUGH;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
23f8e5e598 HV: replace memory config with acrn_vm_mem_config
The member of mem_size and start_hpa in acrn_vm_config struct will
be replaced with the acrn_vm_mem_config struct;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
253b25937b HV: remove vm_config pointer in acrn_vm struct
For each vm_array[] item, its config is located in corresponding
index of vm_configs[], so vm_config pointer is not needed any more.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
7bf9b1be2c HV: enable pcpu bitmap config for partition mode
All the legacy cpu configration in vm_description.c are all cleaned up;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
2e32fba536 HV: remove sworld_supported in acrn_vm_config
We will use guest_flags of SECURE_WORLD_ENABLED to check wthether
sworld is supported.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
ec199d9609 HV: add get_sos_vm api
This patch creates a new get_sos_vm() api to replace get_vm_from_vmid(0U)
because VM 0 might not be SOS VM now;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
f3014a3c89 HV: show correct vm name per config
The patch will show correct VM name per its configuration. As we do not
validate vm id when call get_vm_from_vmid() any more, we only show VM's
states which their VM type are defined;

If VM name is not configured in config file, then the name is specified
with vm id, i.e. "ACRN VM_(vm id)"

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
e6117e0d5b HV: refine launch vm interface
When pcpu enter guest mode, it will call launch_vms() function to launch
VMs in global vm_configs array.

In launch_vms() function, current pcpu will go through vm_config array list
and check whether it is a bsp of configured VM, if yes then it will prepare
corresponding VM and start it. The index of vm_config array will be specified
to VM id.

The first least significant bit in pcpu_bitmap means the bsp of the VM.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Victor Sun
49e6deaf26 HV: rename the term of vm0 to sos vm
Under sharing mode, VM0 is identical with SOS VM. But the coupling of
SOS VM and VM 0 is not friendly for partition mode.

This patch is a pure term change of vm0 to sos VM, it does not change
any code logic or senmantic.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 18:03:31 +08:00
Mingqiang Chi
1d98b7012d hv: move 'setup_io_bitmap' to vm.c
move this api from io_emul.c to vm.c to avoid reverse
dependency

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-01-21 13:49:54 +08:00
Victor Sun
c4a230f313 HV: rename the term of vm_description to vm_config
This patch is a pure term change of vm_description to vm_config,
the struct name of vm_description is changed to acrn_vm_config.

The patch does not change any code logic or senmantic.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-18 11:50:00 +08:00
Minggui Cao
f45605dd49 HV: modularization to separate CR related code
1. move the CR related code from vmcs/vcpu to vCR source files.
2. also add virtual_cr.h to acrn.doxyfile to avoid doc failure.

Tracked-On: #1842
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-01-18 10:50:18 +08:00
Mingqiang Chi
6372548e11 hv:Fix violation "Cyclomatic complexity greater than 20" in instr_emul.c
Split decode_prefixes() to 2 small APIs

v1-->v2:
    split decode_prefixes to 2 APIs

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-17 11:22:02 +08:00
Yan, Like
6641bc7949 hv: remove ACRN_REQUEST_TMR_UPDATE and unnecessary codes
Because ACRN_REQUEST_TMR_UPDATE is not needed anymore, this commit remove
the MACRO definition and its related logic, including following functions:
- apicv_batch_set_tmr()
- vlapic_apicv_batch_set_tmr()
- vlapic_set_tmr_one_vec()
- vioapic_update_tmr()

Tracked-On: #2343
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-17 08:48:22 +08:00
Yan, Like
fc61536b07 hv: rework EOI_EXIT_BITMAP update logic
This commit changes the EOI_EXIT_BITMAP as follows:
- add a eoi_exit_bitmap to vlapic structure;
- go through all the RTEs and set eoi_exit_bitmap in the vlapic structure when related RTE fields are modified;
- add ACRN_REQUEST_EOI_EXIT_UPDATE, if eoi_exit_bitmap changed, request the corresponding vcpu to write the bitmap
  to VMCS.

Tracked-On: #2343
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-17 08:48:22 +08:00
Yan, Like
f15cc7d6de hv: set/clear TMR bit like hardware behave
Current ACRN implementation update TMR bits one time only when related RTE fields changed,
which is not acting like actual hardware.

From SDM vol3 10.8.4:
"Upon acceptance of an interrupt into the IRR, the corresponding TMR bit is cleared for
edge-triggered interrupts and set for leveltriggered interrupts."

This commit change the ACRN implementation to set/clear corresponding TMR bit when inject
intr to vlapic.

Tracked-On: #2343
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-17 08:48:22 +08:00
Chaohong guo
dc6d1d5fa7 HV: fix MISRA issue in apicv_pending_intr()
Remove multi-return statement in apicv_pending_intr().

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-15 13:48:19 +08:00
Chaohong guo
aebb971d41 HV: misra clean for guest.c file
to meeting MISRA, add more bracks for if conditions; also a small
change to copy_gpa() to fix DD flow complaint from MISRA

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-15 13:48:19 +08:00
Chaohong guo
6a1c865671 HV: add empty else statement for if condition in vlapic.c
To meeting MISRA, add empty else {} for corresponding if-else-if {}.
Also, remove a DD flow violation in vlapic_free()

Tracked-On: #861
Signed-off-by: Chaohong guo <chaohong.guo@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-01-15 13:48:19 +08:00
Zide Chen
b30dfb1da8 hv: fix MISRA-C violations in vmsr.c
In enable_msr_interception(), by removing the local pointer declarations and
all pointer arithmetic operations, the following violations are fixed.

- Use of pointer arithmetic.
- Pointer arithmetic is not on array.
- Pointer not checked for null before use.

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-15 08:49:34 +08:00
Li, Fei1
65f3383d62 hv: coding style: remove unnecessary conditional operators
Condtional operators which will add code cyclomatic complexity. So replace the
unnecessary conditional operators.

Tracked-On: #861
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-01-14 15:33:05 +08:00
Zide Chen
92d7018249 hv: fix 2 minor MISRA-C violations in inst_emul.c
Signed integral type cast to unsigned. :  (unsigned long and long)

Tracked-On: #861
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-01-12 10:04:51 +08:00